WO2001067498A1

WO2001067498A1 - Method for producing a field effect transistor with side wall oxidation

Info

Publication number: WO2001067498A1
Application number: PCT/DE2001/000628
Authority: WO
Inventors: Wolfram Langheinrich; Helmut Wurzer
Original assignee: Infineon Technologies Ag
Priority date: 2000-03-07
Filing date: 2001-02-16
Publication date: 2001-09-13
Also published as: DE10011885A1; DE10011885C2

Abstract

The invention relates to a method for producing a field effect transistor with side wall oxidation. According to said method, isolation layers (dh, dv) of differing thicknesses are formed, in particular by the implantation of isolation layer growth-inhibitors (x) and by the subsequent thermal formation of a thermal isolation layer (5) on the surface of a semiconductor substrate (1) and on the side walls of a gate stack (GS). In particular, the reliability of a gate isolation layer (2) and a retention characteristic of the field effect transistor are substantially improved by said method.

Description

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1

on a semiconductor substrate 1, a gate insulation layer 2 and a gate layer 3 are stacked. Source and drain regions S and D formed in the semiconductor substrate 1 and approaching the gate insulation layer 2 thus result in a field effect transistor as used, for example, in DRAM, flash, etc. memory cells. So-called spacers or auxiliary layers SP are usually used on the side walls of the gate insulation layer 2 and the gate layer 3 for lateral insulation or for forming heavily doped source and drain regions. However, the disadvantage of such a conventional field effect transistor is, in particular, the sharp edge or corner of the gate layer 3 that occurs in the gate insulation layer 2. More specifically, when applying normal operating voltages, such as those used in a memory matrix for selecting rows and columns, Due to the sharp-edged shape, very high field strengths E are formed between the gate layer 3 and the source and drain regions S and D, as a result of which leakage currents result in the field effect transistor and thus the charge holding times of memory cells are deteriorated. In particular, this causes a so-called GIDL leakage current (gate induced drain leakage).

To avoid such leakage currents, which result in particular from the high field strengths E at the edges of the gate layer 3, a so-called sidewall oxidation is usually carried out, which essentially rounds off the sharp edges or corners of the gate layer 3 and consequently the Field strengths E are standardized or reduced.

FIG. 2 shows a simplified sectional view of such a conventional field effect transistor with side wall oxidation. In FIG. 2, reference numeral 1 again designates a semiconductor substrate, reference numeral 2 a gate insulation layer and reference numeral 3 a gate layer. In the semiconductor substrate 1 there are in turn source and drain regions S and D.

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become gentle. Furthermore, such a conventional manufacturing process is extremely complex.

The invention is therefore based on the object of providing a method for producing a field-effect transistor with sidewall oxidation, in which field-effect transistors with excellent charge-holding properties can be formed in a simple and inexpensive manner.

According to the invention, this object is achieved by the measures of claim 1.

In particular, by implanting insulation layer growth inhibitors into the surface of the semiconductor substrate or the gate stack and subsequently thermally forming a thermal insulation layer, a self-adjusting process is obtained in which strong side wall oxidation and weak oxidation are carried out in a particularly simple and inexpensive manner of the semiconductor substrate surface takes place.

N, N ₂ or a nitride is preferably incorporated as an insulation layer growth inhibitor into the surface of the semiconductor substrate or of the gate stack. Since such implant materials are already implemented in standard processes, the manufacturing process can be implemented without additional effort.

The implantation of the insulation layer growth inhibitor is preferably carried out perpendicular to the surface of the semiconductor substrate, as a result of which a uniformly thick insulation layer is obtained on the side walls of the gate stack. In this way, so-called bird beaks or birds peaks are formed both on the source and on the drain side, as a result of which the electric field strengths can be significantly reduced or standardized. However, the insulation layer growth inhibitors can also be implanted obliquely to the surface of the semiconductor substrate, as a result of which only one side wall of the gate stack is exposed to strong side wall oxidation and the other side wall undergoes relatively little oxidation. In this way, a leakage current that occurs only on the source or drain side can be selectively reduced.

Furthermore, a weakly doped source and drain implantation before or after the implantation of the insulation layer -

Growth inhibitors are carried out, which results in an optimal adaptation to a particular process. In the same way, a gate insulation layer can only be partially removed and remain as a residual insulation layer on the semiconductor substrate surface, which in turn results in an optimal adaptation to existing manufacturing processes and in particular enables the implementation of a so-called embedded or embedded process.

Further advantageous refinements of the invention are characterized in the further subclaims.

The invention is described below using exemplary embodiments with reference to the drawing.

Show it:

Figure 1 is a simplified sectional view of a

Field effect transistor according to the prior art;

Figure 2 is a simplified sectional view of a

Field effect transistor with sidewall oxidation according to the prior art;

FIGS. 3A to 3G simplified sectional views to illustrate the individual process steps for producing the field effect transistor according to the invention with sidewall oxidation according to a first exemplary embodiment; and

FIGS. 4A and 4B show simplified sectional views to illustrate essential method steps for producing the field effect transistor according to the invention with sidewall oxidation according to a second exemplary embodiment.

FIGS. 3A to 3G show simplified sectional views to illustrate the respective manufacturing steps of the field effect transistor according to the invention with side wall oxidation according to a first exemplary embodiment, the same reference numerals representing the same or similar elements or layers as in FIGS. 1 and 2 and a detailed description being omitted below.

According to FIG. 3A, a semiconductor substrate 1 is first prepared, which can preferably consist of silicon, SiGe, SiC, SOI, GaAs or another III-V semiconductor.

According to FIG. 3B, in a subsequent method step, a gate insulation layer 2 is formed over the entire surface of the semiconductor substrate 1, thermal oxidation of the semiconductor substrate 1 or a chemical deposition method (CVD) preferably being used. The gate insulation layer 2 preferably consists of an SiO ₂ layer, which can also be used as a tunnel oxide layer, in particular when realizing FLASH memories.

According to FIG. 3C, an electrically conductive gate layer 3 is formed over the entire area on the gate insulation layer 2 in a subsequent method step and covered with a mask layer 4. The mask layer 4 preferably consists LO LO to t HH

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ten source and drain regions S and D in the semiconductor substrate 1 result.

What is essential for the present invention, however, is the selectively adjustable size of a necessary one

Scattering oxide SO, which is essentially determined by the vertical thickness d _{v of} the thermal insulation layer 5. Particularly in modern MOS transistor circuits with very small structure sizes, such thin and adjustable scattering oxides are of great importance even after a gate stack has been formed.

The thermal formation of the thermal insulation layer 5 is preferably carried out using a conventional thermal oxidation process, a polysilicon of the gate layer 3 preferably being converted into SiO _{2 of} the thermal insulation layer 5. Accordingly, in the preferred exemplary embodiment according to FIG. 3, the gate insulation layer 2, the mask layer 4 and the thermal insulation layer 5 consist of SiO ₂ .

FIGS. 4A and 4B show simplified sectional views to illustrate the essential production steps of the field effect transistor according to a second exemplary embodiment according to the invention, reference numerals again representing the same or similar elements or layers as in FIGS. 3A to 3G and a repeated description being omitted below.

According to FIGS. 4A and 4B, only the process steps essential for the invention of the implantation of insulation layer growth inhibitors x and the thermal formation of the thermal insulation layer 5 are shown, as they correspond to FIGS. 3D and 3F, but further process steps as in FIGS. 3A to 3C , 3E and 3D are to be used analogously. tt HH

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Claims

claims

1. A method for producing a field effect transistor with sidewall oxidation, comprising the steps of: a) forming a gate insulation layer (2) on a semiconductor substrate (1); b) forming a gate layer (3) on the gate insulation layer (2); c) structuring the gate layer (3) and the gate insulation layer (2) to form a gate stack (GS); d) implanting isolation layer growth inhibitors (x); e) Forming a thermal insulation layer (5) on the 0- surface of the semiconductor substrate (1) and the gate stack

(GS); and f) forming source and drain regions (S, D) in the semiconductor substrate (1).

2. The method as claimed in claim 1, that the insulation layer growth inhibitors (x) implanted in step d) have N, N2 or nitrides.

3. The method according to claim 1 or 2, which also means that the implantation of the insulating layer growth inhibitor (x) in

Step d) is carried out perpendicular to the surface of the semiconductor substrate (1).

4. The method according to claim 1 or 2, so that the insulation layer growth inhibitor (x) is implanted in step d) obliquely to the surface of the semiconductor substrate (1).

5. The method according to any one of claims 1 to 4, characterized in that the implantation of the insulation layer growth inhibitor (x) in Step d) takes place directly in the semiconductor substrate (1) and / or in a residual insulation layer (RI) of the gate insulation layer (2).

6. The method according to one of the claims 1 to 5, that the formation of the thermal insulation layer (5) in step e) represents a thermal sidewall oxidation.

7. The method according to any one of claims 1 to 6, characterized in that the formation of the source and drain regions (S, D) in step f) comprises a step for forming heavily and weakly doped source and drain regions, the formation of the weak doped source and drain regions (S, D) before or after the implantation of the insulation layer growth inhibitor (x) in step d).

8. The method according to any one of claims 1 to 7, that the structuring of the gate layer (3) in step c) takes place using a hard mask (4).

9. The method according to any one of claims 1 to 8 d a d u r c h g e k e n n z e i c h n e t that the semiconductor substrate (1) has Si.

10. The method according to any one of claims 1 to 9, d a d u r c h g e k e n n z e i c h n e t that the gate layer (3) has polysilicon.

11. The method according to any one of claims 1 to 10, that the gate, residual and thermal insulation layer (2, RI, 5) and the hard mask (4) have a silicon oxide layer.