WO2001078140A3 - Chip carrier, relative manufacturing process, and electronic component incorporating such a carrier - Google Patents

Chip carrier, relative manufacturing process, and electronic component incorporating such a carrier Download PDF

Info

Publication number
WO2001078140A3
WO2001078140A3 PCT/IT2001/000177 IT0100177W WO0178140A3 WO 2001078140 A3 WO2001078140 A3 WO 2001078140A3 IT 0100177 W IT0100177 W IT 0100177W WO 0178140 A3 WO0178140 A3 WO 0178140A3
Authority
WO
WIPO (PCT)
Prior art keywords
carrier
cells
mounting areas
electronic components
manufacturing process
Prior art date
Application number
PCT/IT2001/000177
Other languages
French (fr)
Other versions
WO2001078140A2 (en
Inventor
Giuseppe Pedretti
Carlo Arrigoni
Original Assignee
Viasystems S R L
Giuseppe Pedretti
Carlo Arrigoni
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Viasystems S R L, Giuseppe Pedretti, Carlo Arrigoni filed Critical Viasystems S R L
Publication of WO2001078140A2 publication Critical patent/WO2001078140A2/en
Publication of WO2001078140A3 publication Critical patent/WO2001078140A3/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/24—Reinforcing the conductive pattern
    • H05K3/241—Reinforcing the conductive pattern characterised by the electroplating method; means therefor, e.g. baths or apparatus
    • H05K3/242—Reinforcing the conductive pattern characterised by the electroplating method; means therefor, e.g. baths or apparatus characterised by using temporary conductors on the printed circuit for electrically connecting areas which are to be electroplated
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09009—Substrate related
    • H05K2201/09036—Recesses or grooves in insulating substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/0959—Plated through-holes or plated blind vias filled with insulating material
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/02—Details related to mechanical or acoustic processing, e.g. drilling, punching, cutting, using ultrasound
    • H05K2203/0228—Cutting, sawing, milling or shearing
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/05—Patterning and lithography; Masks; Details of resist
    • H05K2203/0562—Details of resist
    • H05K2203/0571—Dual purpose resist, e.g. etch resist used as solder resist, solder resist used as plating resist
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/16—Inspection; Monitoring; Aligning
    • H05K2203/162—Testing a finished product, e.g. heat cycle testing of solder joints
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0044—Mechanical working of the substrate, e.g. drilling or punching
    • H05K3/0052—Depaneling, i.e. dividing a panel into circuit boards; Working of the edges of circuit boards
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
    • H05K3/061—Etching masks
    • H05K3/064—Photoresists
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/28—Applying non-metallic protective coatings

Abstract

A support (10) of the printed circuit type, also called 'chip carrier', for use in the making of electronic components (50), which comprises a sheet (13) of electrically insulating material, and which has, on one side (10a), a first plurality of cells or small areas (27), each of which is provided with solder pads or mounting areas (26) for receiving and electrically connecting to a corresponding integrated electronic circuit (41), and, on the other side (10b), a second plurality of cells provided with solder pads or mounting areas (26) for the coupling of the carrier (10) with a common electronic board (48); wherein a protective layer (28) is deposited on both sides (10a, 10b) of the carrier (10) in such a way as to leave uncovered the relative mounting areas (26), and wherein the carrier (10) also has, along the outlines of the cells (27), a plurality of etchings (33) which pass through the protective layer (28) to leave uncovered the layer (13) of insulating material underneath, and which correspond to removed portions (25a) of an original conducting grid (25), used during the manufacturing process of the carrier (10) itself to deposit a thin layer of solderable material (32) on the various pads or mounting areas (26). The carrier (10), thanks to the removal of these portions (25a) of the original conducting grid (25), acquires a structure which electrically insulates the various cells (27) from one another, so that the carrier (10) may be tested advantageously together with the integrated electronic circuits (41) mounted thereon, before the stage in which the carrier (10) is divided into electronic components (50), thereby avoiding the much more costly testing of the single electronic components (50), piece by piece.
PCT/IT2001/000177 2000-04-10 2001-04-09 Chip carrier, relative manufacturing process, and electronic component incorporating such a carrier WO2001078140A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
IT2000TO000334A IT1320025B1 (en) 2000-04-10 2000-04-10 SUPPORT OF THE PRINTED CIRCUIT TYPE FOR INTEGRATED ELECTRONIC CIRCUITS, PROCEDURE FOR ITS MANUFACTURE, AND COMPONENT
ITTO2000A000334 2000-04-10

Publications (2)

Publication Number Publication Date
WO2001078140A2 WO2001078140A2 (en) 2001-10-18
WO2001078140A3 true WO2001078140A3 (en) 2002-02-07

Family

ID=11457657

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/IT2001/000177 WO2001078140A2 (en) 2000-04-10 2001-04-09 Chip carrier, relative manufacturing process, and electronic component incorporating such a carrier

Country Status (2)

Country Link
IT (1) IT1320025B1 (en)
WO (1) WO2001078140A2 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1381260A1 (en) * 2002-07-11 2004-01-14 Ultratera Corporation Method of plating connecting layers on a conductor pattern of a printed circuit board (PCB)
EP1381259A1 (en) * 2002-07-11 2004-01-14 Ultratera Corporation Structure of printed circuit board (PCB)
US7488620B2 (en) 2005-12-29 2009-02-10 Sandisk Corporation Method of fabricating leadframe based flash memory cards including singulation by straight line cuts

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4551788A (en) * 1984-10-04 1985-11-05 Daniel Robert P Multi-chip carrier array
US5126818A (en) * 1987-05-26 1992-06-30 Matsushita Electric Works, Ltd. Semiconductor device
US5652185A (en) * 1995-04-07 1997-07-29 National Semiconductor Corporation Maximized substrate design for grid array based assemblies
US5783866A (en) * 1996-05-17 1998-07-21 National Semiconductor Corporation Low cost ball grid array device and method of manufacture thereof
US6004833A (en) * 1998-04-21 1999-12-21 Atmel Corporation Method for constructing a leadless array package
US6140708A (en) * 1996-05-17 2000-10-31 National Semiconductor Corporation Chip scale package and method for manufacture thereof

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4551788A (en) * 1984-10-04 1985-11-05 Daniel Robert P Multi-chip carrier array
US5126818A (en) * 1987-05-26 1992-06-30 Matsushita Electric Works, Ltd. Semiconductor device
US5652185A (en) * 1995-04-07 1997-07-29 National Semiconductor Corporation Maximized substrate design for grid array based assemblies
US5783866A (en) * 1996-05-17 1998-07-21 National Semiconductor Corporation Low cost ball grid array device and method of manufacture thereof
US6140708A (en) * 1996-05-17 2000-10-31 National Semiconductor Corporation Chip scale package and method for manufacture thereof
US6004833A (en) * 1998-04-21 1999-12-21 Atmel Corporation Method for constructing a leadless array package

Also Published As

Publication number Publication date
IT1320025B1 (en) 2003-11-12
WO2001078140A2 (en) 2001-10-18
ITTO20000334A1 (en) 2001-10-10
ITTO20000334A0 (en) 2000-04-10

Similar Documents

Publication Publication Date Title
EP1041633A4 (en) Semiconductor device, method of manufacture thereof, circuit board, and electronic device
GB2341277A (en) An electronic component package with posts on the active surface
EP1156705A4 (en) Wiring board, semiconductor device and method of producing, testing and packaging the same, and circuit board and electronic equipment
WO2003017324A8 (en) Structure and method for fabrication of a leadless chip carrier with embedded inductor
EP1005082A4 (en) Semiconductor device, method for manufacturing the same, circuit board and electronic apparatus
EP0913866A4 (en) Electronic component and semiconductor device, method for manufacturing the same, circuit board have the same mounted thereon, and electronic equipment having the circuit board
EP1895586A3 (en) Semiconductor package substrate
JP2004523908A (en) Adapters for plastic leaded chip carriers (PLCC) and other surface mount technology (SMT) chip carriers
WO2002051217A3 (en) Packaged integrated circuits and methods of producing thereof
EP1035759A3 (en) Edge-mountable integrated circuit package and method of attaching the same to a printed wiring board
EP0394588A3 (en) Solder terminal
GB2137807B (en) A semiconductor component and method of manufacture
EP0892274A3 (en) A system and method for easily inspecting a bonded state of a BGA/CSP type electronic part to a board
EP0265629A3 (en) Printed circuit card fabrication process with nickel overplate
GB2341003A (en) Integrated passive components and package with posts
EP1102523A4 (en) Printed-circuit board and method of manufacture thereof
EP1041618A4 (en) Semiconductor device and manufacturing method thereof, circuit board and electronic equipment
EP0804056A3 (en) Improvements in or relating to connecting board
WO2001078140A3 (en) Chip carrier, relative manufacturing process, and electronic component incorporating such a carrier
JPH02301182A (en) Printed circuit board for flat mounting structure
KR920003823A (en) How to connect an integrated circuit to a circuit board and circuit board assembly
US5926379A (en) Electronic card assembly by means of solder connections
JPH05226803A (en) Mounting circuit board
TW422458U (en) Electrical connector
EP0962976A3 (en) Intergrated circuit having unique lead configuration

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A2

Designated state(s): CN JP US

AL Designated countries for regional patents

Kind code of ref document: A2

Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE TR

121 Ep: the epo has been informed by wipo that ep was designated in this application
AK Designated states

Kind code of ref document: A3

Designated state(s): CN JP US

AL Designated countries for regional patents

Kind code of ref document: A3

Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE TR

WWE Wipo information: entry into national phase

Ref document number: 2001925870

Country of ref document: EP

NENP Non-entry into the national phase

Ref country code: JP

WWW Wipo information: withdrawn in national office

Ref document number: 2001925870

Country of ref document: EP

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS (R.69(1)EPC)

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS (R.69(1)EPC)

122 Ep: pct application non-entry in european phase