WO2001078475A1

WO2001078475A1 - Method and device for fabricating electrical connecting elements, and connecting element

Info

Publication number: WO2001078475A1
Application number: PCT/CH2001/000200
Authority: WO
Inventors: Walter Schmidt; Kurt Grohmann
Original assignee: Dyconex Patente Ag
Priority date: 2000-03-31
Filing date: 2001-03-30
Publication date: 2001-10-18
Also published as: AU2001242204A1

Abstract

A method for manufacturing electrical connecting elements or semifinished products is disclosed. Starting from a plastically deformable dielectric substrate layer (1) being on its faces clad with a first and a second conducting layer (3, 5), microperforation combined with a welding or soldering process is carried out. To this end, the clad dielectric substrate layer (1) is placed between a perforation tool (11) having perforation tips (11a) and a support (13) and pressure is applied between the perforation tool (11) and the support (13), so that the perforation tips (11a) of the perforation tool (11) penetrate into the substrate material (1). The materials and the size and shape of the perforation tips (11a) are now chosen in a manner that the conducting material (5) is deformed and the dielectric substrate material (1) is thrust aside, conductor material of the first conducting layer (5) being displaced so that it gets into contact with conductor material of the second conducting layer (3) and is electrically and mechanically connected to conducting material of the second conducting layer.

Description

METHOD AND DEVICE FOR FABRICATING ELECTRICAL CONNECTING ELEMENTS, AND CONNECTING ELEMENT

The invention relates to methods for fabricating electrical connecting elements such as Printed Circuit Boards (PCBs), High-Density-Interconnects (HDIs), Ball-Grid- Array- (BGA-) substrates, Chip Scale Packages (CSP), Multi-Chip-Module- (MCM) substrates, etc. It also relates to a electrical connecting element and to an apparatus for fabricating electrical connecting elements.

In modern circuit board technology, due to increasing miniaturization, conventionally drilled through holes are more and more replaced by microvias. Methods for fabricating such microvias include laser drilling and plasma drilling as well as photochemical structuring. A new method for fabricating microvias has been disclosed in WO 00/13062. This new technology approach, the Micro-Perforation, is a method including mechanical embossing of micro-holes into deformable dielectric material. With Micro-Perforation, any shape of a microvia is feasible. By controlling the length and size of perforation-tips also the formation of very small blind microvias can be achieved.

However, the fabrication of blind microvias by Micro-Perforation and the other state of the art methods have in common that a via fabricating step has to be followed by a contacting step between the conducting layers or pads across the via. Depending on the microvia geometry, such a contacting step may be a chemical or physical deposition of some conductor material as a seed layer followed by an electroplating step. Plating of very small blind holes of lOOμm Diameter and less is very tricky and often results in non-plated holes and consequently scrapped boards. Also, incomplete plating of side walls of the holes affects the reliability of the boards. It therefore would be desirable to have a method which allows to omit this plating step. Omitting the plating step, apart from the elimination of the above shortcomings, would also lead to a considerable reduction of production cost and of environmental impact caused by wet chemical bathes .

It is therefore an objective of the invention to provide a method for the fabrication of microvias which overcomes drawbacks of existing methods and which especially allows the electroplating step for making an electrical contact between two conducting layers to be eliminated.

This objective is achieved by the method as defined in the claims.

The invention is essentially characterized in that a mechanical via forming step is combined with a metal connecting step such as a cold welding process or a soldering process.

The method according to the invention thus combines a perforation step with a contacting step and thus eliminates plating after perforation.

The connecting step may be a cold welding step which is performed at the appropriate temperature between conductor material of a first conducting layer and conductor material of a second conducting layer, the layers being separated by an insulating layer. To this end, the first conducting layer is locally pressed through the insulating layer by a perforation tip. By the pressure exerted on the conductor material, the conductor material from the first and from the second layer is fused. The connecting step may also be any other metal connecting and/or fusing step between conductor material of two layers, the only restriction being that the metals of two layers in some way coalesce. A further example is e.g. a soldering step. In this case, conductor material of a conductor layer to be connected to an other conductor layer is in a previous step provided with soldering material. Other examples of a connecting step according to the invention include welding with energy input such as hot welding or ultrasonic welding.

Perforation can according to the invention be combined with a connecting step if it results in a mechanical deformation of the materials involved, rather than in piercing of one or more layers.

According to one embodiment of the invention, during the combined perforation and metal connecting step, additional energy is supplied. This energy may be supplied in the form of heat. As an alternative, the energy may also be supplied as ultrasonic energy. This embodiment makes the fabrication of well fused and thus reliable connections particularly easy and straightforward. Supplying energy in the form of ultrasonic vibrations can ideally be combined with a piezo actuated perforation tool. This can be done by modulating the piezo voltage by a signal with ultrasonic frequency.

In the following, examples of embodiments of the invention are described with reference to drawings. In the drawings, Figs. la through Id schematically show a PCB HDI substrate (or a component of such a PCB HDI substrate, respectively) during different stages of the production,

Figures 2a and 2b also schematically show a PCB HDI substrate (or a component of such a PCB/HDI substrate, respectively) during different stages of the production if it is produced according to an other embodiment of the invention,

Figures 3a through 3c schematically represent a top cap or a bottom cap of a four layer build up PCB HDI during different stages of the production

Figures 4a and 4b schematically show the production of a component of a four layer build-up using components produced according to figures la through Id and 3a through 3c,

Figures 5a and 5b show examples of tip shapes,

Figures 6a and 6b show the principle of the piezo perforation technique and a voltage/time chart of the piezo actuator if the piezo perforation technique is used,

Figure 7 shows a photograph of a cut through a product produced according to the invention,

and Figures 8a-8g, 9a- 9e, and 10a- 10c show a process sequence for the production of a 4-layer foil-based PCB/HDI with micro-perforation and micro-punching technology. Figures la, lb, lc and Id show a process to manufacture PCB HDI substrates or semi-finished products for the production thereof by means of a combination of micro-perforation and a special connecting technology according to the invention. In the following, with reference to Figures la-Id (or 2a-2c), 3a-3c and 4a-4b a process for manufacturing a four layer build-up is described. It should be noted, however, that the described process can also be used to produce an electrical connecting element of 2 layers, 3 layers 5 layers, 6 layers or any other number of layers. A PCB/HDI substrate of two layers, for example, can be produced using the procedure of Fig. la-Id or Fig. 2a-2d. In order to produce a PCD HDI substrate of more layers, to such a substrate (as semifinished product) the appropriate number of semifinished products produced according to Fig. 3a-3c has to be added.

In Fig la, the core base material 1, which is already coated by a first conducting layer 3 and a second conducting layer 5, is shown. The base material (or substrate material) 1 is a dielectric, e.g. epoxy, polyimide, a liquid crystal polymer (LCP), polysulfone, polyester (PEEK), Polycarbonate etc. The conducting material may be copper or a copper alloy. It may also be an other conducting material such as silver or a silver alloy. In the following description of an example, it is assumed that the conducting layers are clad copper layers. As an example, the thickness of the base material by be around 25-100 μm, the thickness of each clad copper layer around 5- 35 μm. It however goes without saying that the invention also works for other material thicknesses.

In this clad material, by a first Micro-Perforation (MP) step microvias are formed: In Fig. lb, a perforation tool 11 is shown schematically. It is e.g. made of a coated, relatively hard metal such as a Nickel or Chromium or any other hard material. It may also be made of a combination of materials, e.g. may be a Tungsten Carbide coated metal. The perforation tool 11 comprises perforation tips 11a. Apart from the perforation tool, the perforation equipment also comprises a support plate 13 which is also made of a hard material, e.g. steel or any other relatively hard material.

The shape of the perforation tips is crucial for the cold welding process to take place. Two examples of usable tip shapes are schematically shown in Figures 5a and 5b, resprectively. The shape depends on other manufacturing parameters such as the polymer layer thickness, the copper layer thicknesses, the perforation speed, etc. It may, e.g. be formed as a cone with rounded tip (Fig. 5a). The opening angle α of the cone may then vary between 30° and 90°. The radius r of the tip curvature is then e.g. between 5 μm and 100 μm. Generally, a low curvature radius will be combined with a large opening angle. For high perforation speed and high polymer layer thickness, the opening angle will be larger than for lower perforation speed and polymer layer thicknesses. The tip may also be formed as truncated cone with a rounded edge 91 (Fig. 5b). The curvature radius of the edge rounding then is between 2 μm and 20 μm. It may also have other shapes, especially including not rotationally symmetric shapes. It is important, however, that it does not comprise, on a micrometer scale, any sharp tips or edges in order not to pierce through the copper layer but to deform the copper material during the MP-cold- welding-process.

The Micro-Perforation (MP) process may e.g. be carried out at room temperature. It may, depending on the type of the polymer layer, also be performed at a different temperature, e.g. at a temperature between room temperature and 300°C or 400°C. In the process, the perforation tool 11 is pressed against the support plate 13, the clad base material 1, 3, 5 being sandwiched between the perforation tool 11 and the support plate 13 (Fig. lb). By pressing the tips into the material, the dielectric material is deformed and thrust aside. At the same time, the copper is formed by the die, like in a metal-forming-process and is pressed against the opposite copper layer. Since the flat support plate 13 is relatively hard, the copper is crushed against the other copper layer and is permanently connected by a cold-welding process. The two conductor layers are thus electrically and mechanically connected to each other.

For illustrating this effect, in Figure 7 a photograph of a product produced according to the above method in section is shown. As can be seen, in a connection region, the two metal layers 101, 103 are fused together.

In the example shown in Figs. la-Id and 2a, 2b, the height of stroke of the perforation process is determined by the tip length, as can be seen from the drawings. In this case, the perforation tips are just about as long as the sum of the thicknesses of the base material 1 and the first conducting layer 3. More precisely, for the length of the tips, the following formula holds:

dβM+0.5* dcLl ≤ lτi_P ≤ d_BM+dcu+ dcL2,

where dβM is the thickness of the base material 1, d<χι the thickness of the conducting top layer, dc 2 the thickness of the conducting bottom layer, and lχi_P the length of the perforation tip. It should be noted, however, that in certain setups the perforation tip height of stroke is determined by other mechanisms. Then, lχi_p in the above formula should be replaced by a quantity representing the tip height of stroke in the material, i.e. the distance over which the tip is advanced after having touched the conductor material surf ce.

The perforation tool 11 (or die), as an example, may be configured so as to form all the required microvias in one perforation step. As an alternative, perforation and welding may also be carried out in more than one step and using one or more dies.

After the perforation step(s), the die and the support plate are removed (Fig. lc). Then, in a following photo-patterning process, the copper can be structured in accordance with the layout. (Fig. Id). The photo-patterning process may e.g. be carried out according to state-of-the-art photo-patterning processes and is not further described here. The semifinished product resulting is denoted by 21 in the figure.

In the example described here, the perforation die 11 is pressed against an essentially flat support plate 13 for forming the microvias. The method, however, may also be adapted to be performed using two perforation dies for both opposing faces of the layer. The support then is not a support plate but a further perforation tool having perforation tips, too. In this case, the perforation tools may or may not correspond to each other, i.e. they may or may not have perforation tips to be placed at corresponding spots of the opposing surfaces.

As an alternative to the above method, the photo-patterning process can also be carried out before the perforation steps, as shown schematically in Figures 2a and 2b. The perforation steps according to this embodiment of the method are performed analogously to the embodiment described with reference to Figures la through Id. It is, however, important that the pressure exerted on the material is reduced as soon as the distance between the perforation tool and the support plate reaches a minimum value corresponding to the thickness of the clad base material since otherwise the conductor tracks are crushed.

The semifinished product produced according to Fig. la-Id or Fig. 2a-2b, in the example described here may serve as core of a four layer build-up.

The top and the bottom cap layer are made in a way that is different from the forming of the core. The copper layer 33, which is clad on one side of an uncured dielectric material 31 only, as represented in Figure 3a, is perforated by the MP process analogously to the core. The copper clad side of the dielectric material in the following is called the top side, the opposing side will be named the back side. For the MP process, a perforation tool 41 analogous to the perforation tool 11 is used. In contrast to the perforation of the core, a softer support plate 43, such as e.g. a hard plastic (any plastic is usable, e.g. an epoxy resin) is used. In addition, as shown in Figure 3b, during the perforation process, a thin sheet (or foil) 45 of solder material is placed between the support and the unclad side of the dielectric material. As solder material e.g. PbSn or a different tin alloy or any solder material known in the field may be used.

Because of the softness of the support and the solder sheet, the copper 33 may penetrate the opposite surface, resulting in a small copper protrusion 3a. At the same time, at the locations where these protrusions result, the solder material is also subjected to some pressure. Therefore, solder material sticks to the protruding copper material even after the solder foil 45 is removed. This results in solder caps 45' and/or a partial intermixing of solder material with copper (Figure 3c). As an alternative to this tinning method, a sheet of solder material may also be placed on top of the structure, i.e. between the copper layer and the perforation die (not shown). Some solder material is then - due to its characteristic softness - pressed through the structure and remains protruding on the bottom side. The resulting semifinished product is denoted by 51 in the figure. After this procedure, a plasma cleaning step may be carried out on the back side of the product 51 in order to clean away possible pollutants and to remove some dielectric material around the copper protrusions.

Then, the top and bottom layers 51, 51' (both produced according to figs. 3a-3c) are laminated to the core as shown in Figures 4a and 4b. In this way, a 4-layer HDI build-up is formed. By doing so, the tinned copper protrusions are pressed towards correspondingly aligned copper pads of the semifinished product 21. This laminating step may be carried out at room temperature or, depending on the layer materials, at an elevated temperature, so that the pre-tinned copper tips are soldered to the core, this soldering process being a second fusing step. If the polymer material is e.g. a Liquid Crystal Polymer (LCP), the temperature may e.g. be between 200°C and 450°C. Fig. 4a shows the semifinished products 21, 51, 51' and Fig. 4b depicts the lamination/soldering process. The reference numeral 61 denotes two plates (which can be replaced by reels) between which the pressure for laminating is developed. Because of the elevated temperature, by which the soldering is made possible, the base material may, depending on its composition, may be cured simultaneously to the soldering process. Finally, the outer layers are structured in a conventional way by means of photochemical methods (Fig. 4b).

Whereas in the previously described embodiment of the method of the invention, the microvias are produced in a parallel process, also sequentially operating micro- perforation machines are realizable. Fig. 6a shows an example of a part of such a device, namely a perforation tip 73 driven by a piezo activator 75. Such piezo- activators 75 are built using piezo-ceramic materials, like lead- zirconium-titanium- oxides or other known piezoelectric materials. In Fig. 6a, a piezo perforation tool 71 comprising a piezo-activator 75, a perforation tip 73 and a mounting 77 for the piezo- activator 75 is shown very schematically. Piezo-activators allow a very fast actuation. The perforation frequency can be as high as 20kHz, because no mechanical parts have to be moved. In addition, wear-out is also eliminated.

In a device for carrying out the method of the invention, a multitude of piezo perforation tools 71 with a small diameter may be densely packed in an array resulting in a quasi-parallel process with a high throughput. As an alternative, a piezo perforation tool mounted on a piezo activator may comprise several perforation tips formed by one miniature perforation die mounted on the piezo activator. The perforation tips of this one perforation tool are arranged close to each other and may, during a perforation step, all be positioned so that they cover the same contacting area or the same conductor path. All microvias formed in one perforation stage then serve the same contacting purpose, the method thus resulting in enhanced reliability by redundancy.

Referring to Figs, la through 4b, the method according to the invention using such a perforation tool is carried out largely analogously to the procedure using a perforation tool formed as a perforation die 11, 41.

Depending on the tip shape and other parameters, additional energy for the metal fusing process according to the invention may optionally be fed in. A first example of such a feeding in of additional energy is a simple heating of the layered structure, as shown very schematically in Fig. lb by the dashed arrow 22.

A second example of a feeding of additional energy for the metal fusing process, namely for a cold welding process, is by means of ultrasonic energy. As an example, a piezo activated perforation tip of the kind of the perforation tip shown in Fig. 6a can be provided with a high frequency voltage superposed on the piezo activating DC signal as shown schematically in Fig. 6b. In Fig. 6b, the voltage/time curve 81 of a piezo process without feeding of additional ultrasonic energy is compared to a voltage/time curve 83 of a piezo process where ultrasonic energy is fed in. As can be seen from the schematic curve, an ultrasonic modulation is superposed on the piezo actuating voltage. This ultrasonic signal has a much higher frequency than the perforation frequency but a clearly lower amplidude than the difference (V_- No) required for the piezo height of stroke. The perforation tool and support schematically shown in the previously described figures are both supposed to be an essentially flat plate. It may, however, as well be that either or both of these items may be formed as a reel. In this case the substrate is e.g. a foil which is formed by a continuous perforation process and which is only then divided into individual interconnects. Of course, also essentially flat perforation tools and/or supports may be mounted on a reel, one reel may be combined with an essentially flat tool or support (e.g. formed as conveyor belt) etc.

A further modification of the above described method pertains to the (cold, hot or ultrasonic) welding process. It is equally well imaginable that instead of a pure welding process, welding may be combined with soldering or even be replaced by soldering. To this end, an appropriate solder material may be placed underneath the perforation tool of Figure 1. During the perforation step using a hard support plate, it intermixes with the copper material of the first conducting layer and also with the conducting material of the second conducting layer. As an alternative, solder material may directly be placed between the first conducting layer and the dielectric substrate layer before the perforation process, as a modification of the clad substrate of Figure la.

A device for carrying out the method described here can be arranged in various ways. It comprises means for holding a substrate. These may be formed as a plurality of reels between which the substrate is stretched and by which it is transported. They may also be configured to be some sort of a table , e.g. comprising suction means for creating a depression between a surface and the substrate. By these means the substrate may temporarily, during a perforation step, be attached to the table. The device further has means for heating the substrate to a certain desired temperature, which means may or may not be integrated in the means for holding the substrate. Crucial to the device is the perforation tool. This tool may e.g. comprise a perforation die (possibly mounted on a reel or formed as a reel) or be formed as a piezo perforation tool as previously shortly described. A perforation tool may be configured to be or mounted on a reel. The perforation tip or perforation tips are formed in the previously described manner, i.e., on a micrometer scale, they do not have any sharp points or edges. Before the perforation step can be carried out, the lateral position of the sample with respect to the perforation tool has to be determined. This can be done by some camera or may alternatively be provided by the means for holding the substrate.

As previously stated, it may be important that the perforation tip penetration depth is approximately equal to the sum of the thicknesses of the substrate material an of the first conducting layer, i.e. that dβM+0.5* dc ≤ (Penetration depth) < dβ +dcLi+ dc ₂- This can be achieved by choosing the tip length to be within this penetration depth range and by pressing the perforation die against the substrate. As an alternative, e.g. if the perforation tool is a piezo perforation tool, the moment when the perforation tip touches (or the perforation tips touch, respectively) the surface of the first conducting layer. This can be done by measuring the resistance between this first conducting layer and the perforation tiρ(s). A control electronics then be programmed to then advance the perforation tip by exactly a pre-defined penetration depth determined according to the above formula.

The embodiment described by Figures 8a- 10c goes even a step further than the above described embodiments: During the perforation/cold welding step, the layers are also imprinted (micro-punching). No wet chemicals are involved any more.

A dielectric foil material coated on both sides with a Cu foil, which is adhering to the material because the surface is tacky (Fig. 8a) is loaded into an embossing equipment (Fig. 8b). The dies shown above and below the foil in the Figure include not only the traces and other features but also the tips for the microvias. The stack is pressed together and the copper is formed, where rounded tips are pressing into the copper layer, and is punched through, where the die has sharp edges, which cut through the copper (Figs. 8c and 8d). During the embossing, the principle of cold welding is applied for the blind via. The resulting product is shown in Fig. 8d.

After separation, the copper which has not been pressed down into the dielectric can be taken off by an adhesive tape process (Fig 8e). After removal of the excess copper, the core is finished (Fig. 8g).

The manufacturing a top or bottom cap layer is shown in Figures 9a-9e. The top and bottom cap layers are formed analogue to the core, but with a soft support plate, which results in copper protrusions, like shown for the previous embodiments. At the same time, the embossing is done, to form the copper pattern (Figs. 9a-9c). The excess of copper is removed with a tacky tape and the outer layers are finished (Figs. 9d, 9e).

An example of fixing a top and a bottom cap to the core is shown in Figures lOa-lOc. In principle, the same tinning process as explained above can be applied to get a solderable surface. Another method, shown in the Figures, is to use a pre-coated Cu foil. The foil is coated on the outer side with a thin layer of lower melting metal, which remains on the surface, throughout the whole process. Core and pre-formed outer layers are then laminated together and the pre-coated copper surface on the core provides for the solder to get an inter-metallic connection between the copper protrusion and the corresponding pads on the core (Figures 10a- 10c). The copper surfaces may be plasma activated for the process to be (even better) bondable. The lamination process shown in Figures 10a and 10b can be combined with the embossing process for the outer layers shown in Figure 9b. This technology combines a variety of advantages:

- No plating necessary

- No photo-patterning necessary

- Low cost material

- Minimum number of processing steps

- Processes suitable for complete automation

Claims

WHAT IS CLAIMED IS:

1. A method for manufacturing electrical connecting elements or semifinished products wherein a plastically deformable dielectric substrate layer is provided, said plastically deformable dielectric substrate layer having two surfaces at least partially being covered by a first and a second conducting layer, wherein said at least partially covered dielectric substrate layer is placed between a perforation tool having perforation tips and a support, and wherein pressure is applied between the perforation tool and the support, so that the perforation tips of said perforation tool penetrate into the substrate material, the conducting material being deformed and the dielectric substrate material being thrust aside, in a manner that conductor material of the first conducting layer is displaced so that it gets into contact with conductor material of said second conducting layer and is electrically and mechanically connected to conducting material of said second conducting layer.

2. A method according to claim 1 wherein for the length lτ;_p of the perforation tips, dβM+0.5* dc i ≤ lτi_P ≤ βM+dcLi+ dcL2 holds, where dβM is the thickness of the plastically deformable substrate layer and dc and dc 2 are the thickness of the first and the second conducting layer, respectively.

3. A method according to claim 1 or 2, wherein the perforation tip shape is the shape of a cone comprising a rounded tip or a truncation with rounded edges, the cone opening angle (α) of the cone being between 30° and 90°.

4. A method according to any one of the preceding claims, wherein during the plastic deforming step, additional energy is supplied in the form of heat for fusing conducting material of said first and second conducting layers together.

5. A method according to any one of the preceding claims, wherein during the plastic deforming step, additional energy is supplied in the form of ultrasonic energy for fusing conducting material of said first and second conducting layers together.

6. A method according to any one of the preceding claims, wherein soldering material is provided for electrically and mechanically connecting conducting material of said first and of said second conducting layer.

7. A method according to any one of the preceding claims, wherein at least one of the perforation tool and the support is formed as a reel or mounted on a reel.

8. A method according to any one of the preceding claims, wherein tips of said perforation tool are driven by a piezo activator, the piezo activator having a height of stroke which is at least approximately equal the sum of the thicknesses of the insulating plastically deformable layer and of the top conducting layer, and wherein perforation steps are carried out using the piezo activator.

9. A method according to the claims 5 and 8 wherein the ultrasonic energy is supplied in the form of adding to the piezo voltage an alternating voltage signal with ultrasonic frequency.

10. A method according to any one of the preceding claims, wherein at least one conducting layer is structured after the perforation, e.g. using photochemical methods.

11. A method according to any one of the preceding claims, wherein further a second plastically deformable dielectric substrate layer is provided which is at least partially clad on one face by a third conducting layer, the other face not being clad, wherein said partially clad second dielectric substrate layer is placed between a perforation tool having perforation tips and a support, wherein further a sheet of solder material is placed between said second clad substrate layer and the perforation tool or between said second substrate layer and the support, and wherein pressure is applied between the perforation tool and the support, so that the perforation tips of said perforation tool penetrate into the substrate material, the conducting material being deformed and the dielectric substrate material being thrust aside, and conductor material and solder material protruding on the unclad face of said second clad substrate layer, and wherein the thus reshaped second substrate layer's unclad face is laminated to the first partially covered substrate layer.

12. A semifinished product or an electrical connecting element manufactured using the method according to any one of the preceding claims, comprising an insulating layer and two conducting layers, each adjacent to a face of said insulating layer and possibly being structured, the substrate layer comprising microvias, the walls of said microvias being covered by conductor material of one of said conductor layers being welded or soldered to conductor material of the other one of said conductor layers.

13. A device for carrying out the method according to any one of claims 1 to 11, comprising means for holding a substrate comprising a substrate layer covered by a first and a second conducting layer, means for heating the substrate to a certain desired temperature, a perforation tool having at least one perforation tip, the perforation tip, on a micrometer scale, not having any sharp points or edges, the device further comprising means for determining a lateral position of the substrate with respect to the perforation tool, means for moving the perforation tool with respect to the substrate in a way that the perforation tip penetrates the conductor material of the first conducting layer and of the substrate layer and means for causing a well-defined perforation tip penetration depth.

14. A device according to claim 13 wherein the means for causing a well-defined perforation tip penetration depth comprise electrical resistance measuring means for measuring an electrical resistance between the perforation tip and the first conducting layer in order to determine the moment when the perforation tip touches the surface and means for advancing the perforation tip by a pre-defined height of stroke after this moment.

15. A device according to claim 13 or 14, wherein the means for holding a substrate comprise support means with a surface and with means for causing a depression between this surface and a substrate.