WO2001079863A3 - Method and apparatus for testing signal paths between an integrated circuit wafer and a wafer tester - Google Patents

Method and apparatus for testing signal paths between an integrated circuit wafer and a wafer tester Download PDF

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Publication number
WO2001079863A3
WO2001079863A3 PCT/US2001/010030 US0110030W WO0179863A3 WO 2001079863 A3 WO2001079863 A3 WO 2001079863A3 US 0110030 W US0110030 W US 0110030W WO 0179863 A3 WO0179863 A3 WO 0179863A3
Authority
WO
WIPO (PCT)
Prior art keywords
signal paths
wafer
tester
interconnect structure
test
Prior art date
Application number
PCT/US2001/010030
Other languages
French (fr)
Other versions
WO2001079863A2 (en
Inventor
Ralph G Whitten
Benjamin N Eldridge
Original Assignee
Formfactor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US09/548,885 external-priority patent/US6724209B1/en
Application filed by Formfactor Inc filed Critical Formfactor Inc
Priority to KR1020027013785A priority Critical patent/KR100752448B1/en
Priority to EP01922817A priority patent/EP1275010A2/en
Priority to JP2001576477A priority patent/JP2003531481A/en
Priority to AU2001249578A priority patent/AU2001249578A1/en
Publication of WO2001079863A2 publication Critical patent/WO2001079863A2/en
Publication of WO2001079863A3 publication Critical patent/WO2001079863A3/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/3167—Testing of combined analog and digital circuits

Abstract

Signal paths within an interconnect structure linking input/output (I/O) ports of an integrated circuit (IC) tester and test points of an IC die on a wafer are tested for continuity, shorts and resistance by using the interconnect structure to access a similar arrangement of test points on a reference wafer. Conductors in the reference wafer interconnect groups of test points. The tester may then test the continuity of signal paths through the interconnect structure by sending test signals between pairs of its ports through those signal paths and the interconnecting conductors within the reference wafer. A parametric test unit within the tester can also determine impedances of the signal paths through the interconnect structure by comparing magnitudes of voltage drops across pairs of its I/O ports to magnitudes of currents it transmits between the I/O port pairs.
PCT/US2001/010030 2000-04-13 2001-03-27 Method and apparatus for testing signal paths between an integrated circuit wafer and a wafer tester WO2001079863A2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
KR1020027013785A KR100752448B1 (en) 2000-04-13 2001-03-27 Method and apparatus for testing signal paths between an integrated circuit wafer and a wafer tester
EP01922817A EP1275010A2 (en) 2000-04-13 2001-03-27 Method and apparatus for testing signal paths between an integrated circuit wafer and a wafer tester
JP2001576477A JP2003531481A (en) 2000-04-13 2001-03-27 Method and apparatus for testing a signal path between an integrated circuit wafer and a wafer tester
AU2001249578A AU2001249578A1 (en) 2000-04-13 2001-03-27 Method and apparatus for testing signal paths between an integrated circuit wafer and a wafer tester

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US09/548,885 US6724209B1 (en) 2000-04-13 2000-04-13 Method for testing signal paths between an integrated circuit wafer and a wafer tester
US09/548,885 2000-04-13
US09/568,460 US6476630B1 (en) 2000-04-13 2000-05-09 Method for testing signal paths between an integrated circuit wafer and a wafer tester
US09/568,460 2000-05-09

Publications (2)

Publication Number Publication Date
WO2001079863A2 WO2001079863A2 (en) 2001-10-25
WO2001079863A3 true WO2001079863A3 (en) 2002-05-16

Family

ID=27068958

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2001/010030 WO2001079863A2 (en) 2000-04-13 2001-03-27 Method and apparatus for testing signal paths between an integrated circuit wafer and a wafer tester

Country Status (8)

Country Link
US (1) US6476630B1 (en)
EP (1) EP1275010A2 (en)
JP (1) JP2003531481A (en)
KR (1) KR100752448B1 (en)
CN (1) CN1186643C (en)
AU (1) AU2001249578A1 (en)
TW (1) TW495897B (en)
WO (1) WO2001079863A2 (en)

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CN101770967A (en) * 2009-01-03 2010-07-07 上海芯豪微电子有限公司 Test method, device and system of common substrate integrated circuit
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CN107340466B (en) * 2016-04-28 2019-11-01 中芯国际集成电路制造(上海)有限公司 Analog signal detection system and analog signal detection method
US10295588B2 (en) * 2016-12-22 2019-05-21 Xcelsis Corporation Wafer testing without direct probing
WO2018163021A1 (en) * 2017-03-07 2018-09-13 Semiconductor Energy Laboratory Co., Ltd. Ic, driver ic, display system, and electronic device
CN107192940A (en) * 2017-04-27 2017-09-22 中国石油天然气股份有限公司 A kind of device for detecting circuit board working condition
DE102018217406B4 (en) * 2018-06-18 2020-07-23 ATEip GmbH Method and device for electrically testing an electrical assembly
WO2020048381A1 (en) * 2018-09-03 2020-03-12 Changxin Memory Technologies, Inc. Chip test device and method
CN110907796B (en) * 2018-09-14 2022-02-08 长鑫存储技术有限公司 Integrated circuit measurement result imaging analysis method and system
CN110954804B (en) * 2019-12-19 2021-11-02 上海御渡半导体科技有限公司 Device and method for accurately diagnosing cBit array faults in batch
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Also Published As

Publication number Publication date
CN1436307A (en) 2003-08-13
JP2003531481A (en) 2003-10-21
TW495897B (en) 2002-07-21
KR20030001420A (en) 2003-01-06
WO2001079863A2 (en) 2001-10-25
KR100752448B1 (en) 2007-08-27
CN1186643C (en) 2005-01-26
EP1275010A2 (en) 2003-01-15
AU2001249578A1 (en) 2001-10-30
US6476630B1 (en) 2002-11-05

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