WO2001080483A3 - Authentication engine architecture and method - Google Patents

Authentication engine architecture and method Download PDF

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Publication number
WO2001080483A3
WO2001080483A3 PCT/US2001/040507 US0140507W WO0180483A3 WO 2001080483 A3 WO2001080483 A3 WO 2001080483A3 US 0140507 W US0140507 W US 0140507W WO 0180483 A3 WO0180483 A3 WO 0180483A3
Authority
WO
WIPO (PCT)
Prior art keywords
sha1
authentication
hmac
algorithm
rounds
Prior art date
Application number
PCT/US2001/040507
Other languages
French (fr)
Other versions
WO2001080483A2 (en
Inventor
Mark Buer
Patrick Y Law
Zheng Qi
Original Assignee
Broadcom Corp
Mark Buer
Patrick Y Law
Zheng Qi
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Broadcom Corp, Mark Buer, Patrick Y Law, Zheng Qi filed Critical Broadcom Corp
Priority to AU2001253888A priority Critical patent/AU2001253888A1/en
Priority to DE60113395T priority patent/DE60113395T2/en
Priority to AT01927441T priority patent/ATE304759T1/en
Priority to EP01927441A priority patent/EP1273129B1/en
Publication of WO2001080483A2 publication Critical patent/WO2001080483A2/en
Publication of WO2001080483A3 publication Critical patent/WO2001080483A3/en

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/06—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols the encryption apparatus using shift registers or memories for block-wise or stream coding, e.g. DES systems or RC4; Hash functions; Pseudorandom sequence generators
    • H04L9/0643—Hash functions, e.g. MD5, SHA, HMAC or f9 MAC
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L2209/00—Additional information or applications relating to cryptographic mechanisms or cryptographic arrangements for secret or secure communication H04L9/00
    • H04L2209/12—Details relating to cryptographic hardware or logic circuitry
    • H04L2209/125—Parallelization or pipelining, e.g. for accelerating processing of cryptographic operations

Abstract

Provided is an architecture (hardware implementation) for an authentication engine to increase the speed at which multi-loop and/or multi-round authentication algorithms may be performed on data packets transmitted over a computer network. Authentication engines in accordance with the present invention apply a variety of techniques that may include, in various applications, collapsing two multi-round authentication algorithm (e.g., SHA1 or MD5 or variants) processing rounds into one; reducing operational overhead by scheduling the additions required by a multi-round authentication algorithm in such a manner as to reduce the overall critical timing path ('hiding the ads'); and, for a multi-loop (e.g., HMAC) variant of a multi-round authentication algorithm, pipelining the inner and outer loops. In one particular example of applying the invention in an authentication engine using the HMAC-SHA1 algorithm of the IPSec protocol, collapsing of the conventional 80 SHA1 rounds into 40 rounds, hiding the ads, and pipelining the inner and outer loops allows HMAC-SHA1 to be conducted in approximately the same time as conventional SHA1.
PCT/US2001/040507 2000-04-13 2001-04-11 Authentication engine architecture and method WO2001080483A2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
AU2001253888A AU2001253888A1 (en) 2000-04-13 2001-04-11 Authentication engine architecture and method
DE60113395T DE60113395T2 (en) 2000-04-13 2001-04-11 METHOD AND ARCHITECTURE FOR AUTHENTICATION
AT01927441T ATE304759T1 (en) 2000-04-13 2001-04-11 METHOD AND ARCHITECTURE FOR AUTHENTICATION
EP01927441A EP1273129B1 (en) 2000-04-13 2001-04-11 Authentication engine architecture and method

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
US19715200P 2000-04-13 2000-04-13
US60/197,152 2000-04-13
US26142501P 2001-01-12 2001-01-12
US60/261,425 2001-01-13
US09/827,882 2001-04-04
US09/827,882 US7177421B2 (en) 2000-04-13 2001-04-04 Authentication engine architecture and method

Publications (2)

Publication Number Publication Date
WO2001080483A2 WO2001080483A2 (en) 2001-10-25
WO2001080483A3 true WO2001080483A3 (en) 2002-04-04

Family

ID=27393706

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2001/040507 WO2001080483A2 (en) 2000-04-13 2001-04-11 Authentication engine architecture and method

Country Status (6)

Country Link
US (2) US7177421B2 (en)
EP (1) EP1273129B1 (en)
AT (1) ATE304759T1 (en)
AU (1) AU2001253888A1 (en)
DE (1) DE60113395T2 (en)
WO (1) WO2001080483A2 (en)

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Also Published As

Publication number Publication date
US8000469B2 (en) 2011-08-16
DE60113395D1 (en) 2005-10-20
EP1273129A2 (en) 2003-01-08
ATE304759T1 (en) 2005-09-15
EP1273129B1 (en) 2005-09-14
AU2001253888A1 (en) 2001-10-30
DE60113395T2 (en) 2006-06-14
US20020001384A1 (en) 2002-01-03
WO2001080483A2 (en) 2001-10-25
US7177421B2 (en) 2007-02-13
US20070110230A1 (en) 2007-05-17

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