WO2001082053A3 - A low latency fifo circuit for mixed clock systems - Google Patents

A low latency fifo circuit for mixed clock systems Download PDF

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Publication number
WO2001082053A3
WO2001082053A3 PCT/US2001/013777 US0113777W WO0182053A3 WO 2001082053 A3 WO2001082053 A3 WO 2001082053A3 US 0113777 W US0113777 W US 0113777W WO 0182053 A3 WO0182053 A3 WO 0182053A3
Authority
WO
WIPO (PCT)
Prior art keywords
sender
empty
clock
subsystem
receiver
Prior art date
Application number
PCT/US2001/013777
Other languages
French (fr)
Other versions
WO2001082053A2 (en
Inventor
Tiberiu Chelcea
Steven M Nowick
Original Assignee
Univ Columbia
Tiberiu Chelcea
Steven M Nowick
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Univ Columbia, Tiberiu Chelcea, Steven M Nowick filed Critical Univ Columbia
Priority to CA002407407A priority Critical patent/CA2407407A1/en
Priority to US10/258,221 priority patent/US7197582B2/en
Priority to AU2001257403A priority patent/AU2001257403A1/en
Publication of WO2001082053A2 publication Critical patent/WO2001082053A2/en
Publication of WO2001082053A3 publication Critical patent/WO2001082053A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G06F5/10—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor having a sequence of storage locations each being individually accessible for both enqueue and dequeue operations, e.g. using random access memory
    • G06F5/12—Means for monitoring the fill level; Means for resolving contention, i.e. conflicts between simultaneous enqueue and dequeue operations
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4027—Coupling between buses using bus bridges
    • G06F13/4031—Coupling between buses using bus bridges with arbitration
    • G06F13/4036—Coupling between buses using bus bridges with arbitration and deadlock prevention
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4027—Coupling between buses using bus bridges
    • G06F13/405—Coupling between buses using bus bridges where the bridge performs a synchronising function
    • G06F13/4059—Coupling between buses using bus bridges where the bridge performs a synchronising function where the synchronisation uses buffers, e.g. for speed matching between buses
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2205/00—Indexing scheme relating to group G06F5/00; Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F2205/12—Indexing scheme relating to groups G06F5/12 - G06F5/14
    • G06F2205/126—Monitoring of intermediate fill level, i.e. with additional means for monitoring the fill level, e.g. half full flag, almost empty flag
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0038—System on Chip

Abstract

A FIFO design interfaces a sender subsystem and a receiver subsystem working at different speeds. Global control signals relating to whether the FIFO is nearly full or nearly empty are synchronized to the sender subsystem clock and the receiver subsystem clock, respectively. A full global control signal synchronized to the sender clock signal is set when the array of cells is nearly full. A data item is enqueued when the full global control signal is not asserted and the sender requests the data be enqueued. A first empty global control signal is synchronized to the receiver clock is set when the array of cells is nearly empty. Data may be dequeued when requested by the receiver subsystem if the second empty signal is not asserted. A second empty control signal is also synchronized with the sender clock signal and is set when the FIFO is nearly empty and contains at least one valid data item. A dummy data item is enqueued when the full global control signal is not asserted and the second empty signal is asserted in order to prevent deadlock. A mixed-clock relay station design interfaces a sender subsystem and a receiver subsystem working at different speeds, and where the latency between sender and receiver is large.
PCT/US2001/013777 2000-04-26 2001-04-26 A low latency fifo circuit for mixed clock systems WO2001082053A2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
CA002407407A CA2407407A1 (en) 2000-04-26 2001-04-26 A low latency fifo circuit for mixed clock systems
US10/258,221 US7197582B2 (en) 2000-04-26 2001-04-26 Low latency FIFO circuit for mixed clock systems
AU2001257403A AU2001257403A1 (en) 2000-04-26 2001-04-26 A low latency fifo circuit for mixed clock systems

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US19985100P 2000-04-26 2000-04-26
US60/199,851 2000-04-26

Publications (2)

Publication Number Publication Date
WO2001082053A2 WO2001082053A2 (en) 2001-11-01
WO2001082053A3 true WO2001082053A3 (en) 2003-04-24

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2001/013777 WO2001082053A2 (en) 2000-04-26 2001-04-26 A low latency fifo circuit for mixed clock systems

Country Status (4)

Country Link
US (1) US7197582B2 (en)
AU (1) AU2001257403A1 (en)
CA (1) CA2407407A1 (en)
WO (1) WO2001082053A2 (en)

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US7269172B2 (en) 2003-01-07 2007-09-11 Sun Microsystems, Inc. Method and device for managing transmit buffers
CN100370415C (en) * 2003-04-26 2008-02-20 华为技术有限公司 Threading metod for processing data packets based on FIFO queue and device of
US20070186076A1 (en) * 2003-06-18 2007-08-09 Jones Anthony M Data pipeline transport system
EP1636725B1 (en) 2003-06-18 2018-05-16 Imagination Technologies Limited Circuit register and method therefor
US20080052687A1 (en) * 2003-11-03 2008-02-28 Agustin Gonzales-Tuchmann Development environment for data transformation applications
US7890684B2 (en) * 2006-08-31 2011-02-15 Standard Microsystems Corporation Two-cycle return path clocking
US7802032B2 (en) * 2006-11-13 2010-09-21 International Business Machines Corporation Concurrent, non-blocking, lock-free queue and method, apparatus, and computer program product for implementing same
JP4763629B2 (en) * 2007-02-20 2011-08-31 富士通セミコンダクター株式会社 Verification device, verification method, and program
US7913007B2 (en) 2007-09-27 2011-03-22 The University Of North Carolina Systems, methods, and computer readable media for preemption in asynchronous systems using anti-tokens
US8176280B2 (en) * 2008-02-25 2012-05-08 International Business Machines Corporation Use of test protection instruction in computing environments that support pageable guests
US8669779B2 (en) 2008-06-27 2014-03-11 The University Of North Carolina At Chapel Hill Systems, pipeline stages, and computer readable media for advanced asynchronous pipeline circuits
US8346784B1 (en) 2012-05-29 2013-01-01 Limelight Networks, Inc. Java script reductor
US8352774B2 (en) 2010-06-23 2013-01-08 King Fahd University Of Petroleum And Minerals Inter-clock domain data transfer FIFO circuit
US9721495B2 (en) 2013-02-27 2017-08-01 E Ink Corporation Methods for driving electro-optic displays
US9520180B1 (en) 2014-03-11 2016-12-13 Hypres, Inc. System and method for cryogenic hybrid technology computing and memory
WO2015192062A1 (en) 2014-06-12 2015-12-17 The University Of North Carolina At Chapel Hill Camera sensor with event token based image capture and reconstruction
US9703526B2 (en) * 2015-03-12 2017-07-11 Altera Corporation Self-stuffing multi-clock FIFO requiring no synchronizers
US10505704B1 (en) * 2015-08-02 2019-12-10 Wave Computing, Inc. Data uploading to asynchronous circuitry using circular buffer control

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US5956748A (en) * 1997-01-30 1999-09-21 Xilinx, Inc. Asynchronous, dual-port, RAM-based FIFO with bi-directional address synchronization

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Also Published As

Publication number Publication date
AU2001257403A1 (en) 2001-11-07
US7197582B2 (en) 2007-03-27
US20040125665A1 (en) 2004-07-01
CA2407407A1 (en) 2001-11-01
WO2001082053A2 (en) 2001-11-01

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