WO2001085884A3 - Predictive timing calibration for memory devices - Google Patents

Predictive timing calibration for memory devices Download PDF

Info

Publication number
WO2001085884A3
WO2001085884A3 PCT/US2001/014658 US0114658W WO0185884A3 WO 2001085884 A3 WO2001085884 A3 WO 2001085884A3 US 0114658 W US0114658 W US 0114658W WO 0185884 A3 WO0185884 A3 WO 0185884A3
Authority
WO
WIPO (PCT)
Prior art keywords
data
alignment
edge
pattern
bit
Prior art date
Application number
PCT/US2001/014658
Other languages
French (fr)
Other versions
WO2001085884A2 (en
Inventor
Brent Keeth
Brian Johnson
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Priority to AU2001259571A priority Critical patent/AU2001259571A1/en
Priority to EP01933122A priority patent/EP1282677B1/en
Priority to KR1020027015063A priority patent/KR100580740B1/en
Priority to JP2001582474A priority patent/JP4649629B2/en
Priority to DE60132445T priority patent/DE60132445T2/en
Publication of WO2001085884A2 publication Critical patent/WO2001085884A2/en
Publication of WO2001085884A3 publication Critical patent/WO2001085884A3/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/22—Control and timing of internal memory operations
    • G11C2207/2254—Calibration

Abstract

The present invention provides a unique way of using a 2N bit synchronization pattern to obtain a faster and more reliable calibration of multiple data paths in a memory system. If the 2N bit synchronization pattern is generated with a known clock phase relationship, then the data-to-clock phase alignment can be determined using simple decode logic to predict the next m-bits from a just-detected m-bits. If the succeeding m-bit pattern does not match the predicted pattern, then the current data-to-clock alignment fails for a particular delay value adjustment in the data path undergoing alignment, and the delay in that data path is adjusted to a new value. The invention also ensures that data alignment will occur to a desired edge of the clock signal, e.g., a positive going edge, by forcing a failure of all predicted m-bit patterns which are associated with an undesired edge, e.g., a negative going edge, of the clock signal.
PCT/US2001/014658 2000-05-10 2001-05-07 Predictive timing calibration for memory devices WO2001085884A2 (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
AU2001259571A AU2001259571A1 (en) 2000-05-10 2001-05-07 Predictive timing calibration for memory devices
EP01933122A EP1282677B1 (en) 2000-05-10 2001-05-07 Predictive timing calibration for memory devices
KR1020027015063A KR100580740B1 (en) 2000-05-10 2001-05-07 Predictive timing calibration for memory devices
JP2001582474A JP4649629B2 (en) 2000-05-10 2001-05-07 Predictive timing calibration for memory devices
DE60132445T DE60132445T2 (en) 2000-05-10 2001-05-07 CALIBRATION OF BUS SIGNALS FOR MEMORY ARRANGEMENTS

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/568,016 US6606041B1 (en) 2000-05-10 2000-05-10 Predictive timing calibration for memory devices
US09/568,016 2000-05-10

Publications (2)

Publication Number Publication Date
WO2001085884A2 WO2001085884A2 (en) 2001-11-15
WO2001085884A3 true WO2001085884A3 (en) 2002-05-23

Family

ID=24269573

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2001/014658 WO2001085884A2 (en) 2000-05-10 2001-05-07 Predictive timing calibration for memory devices

Country Status (10)

Country Link
US (2) US6606041B1 (en)
EP (3) EP1927988B1 (en)
JP (1) JP4649629B2 (en)
KR (1) KR100580740B1 (en)
CN (2) CN101320593A (en)
AT (3) ATE437438T1 (en)
AU (1) AU2001259571A1 (en)
DE (3) DE60143726D1 (en)
TW (1) TW588375B (en)
WO (1) WO2001085884A2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9099194B2 (en) 2001-10-22 2015-08-04 Rambus Inc. Memory component with pattern register circuitry to provide data patterns for calibration

Families Citing this family (34)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7137048B2 (en) * 2001-02-02 2006-11-14 Rambus Inc. Method and apparatus for evaluating and optimizing a signaling system
US6735709B1 (en) 2000-11-09 2004-05-11 Micron Technology, Inc. Method of timing calibration using slower data rate pattern
US6873939B1 (en) 2001-02-02 2005-03-29 Rambus Inc. Method and apparatus for evaluating and calibrating a signaling system
US7490275B2 (en) 2001-02-02 2009-02-10 Rambus Inc. Method and apparatus for evaluating and optimizing a signaling system
US7058799B2 (en) * 2001-06-19 2006-06-06 Micron Technology, Inc. Apparatus and method for clock domain crossing with integrated decode
EP1865648B1 (en) 2001-10-22 2012-12-05 Rambus Inc. Phase adjustment apparatus and method for a memory device signalling system
US7469328B1 (en) * 2003-02-06 2008-12-23 Cisco Technology, Inc. Synchronization technique for high speed memory subsystem
US7076377B2 (en) * 2003-02-11 2006-07-11 Rambus Inc. Circuit, apparatus and method for capturing a representation of a waveform from a clock-data recovery (CDR) unit
US7336749B2 (en) * 2004-05-18 2008-02-26 Rambus Inc. Statistical margin test methods and circuits
US7590175B2 (en) * 2003-05-20 2009-09-15 Rambus Inc. DFE margin test methods and circuits that decouple sample and feedback timing
US7627029B2 (en) 2003-05-20 2009-12-01 Rambus Inc. Margin test methods and circuits
US7646835B1 (en) * 2003-11-17 2010-01-12 Rozas Guillermo J Method and system for automatically calibrating intra-cycle timing relationships for sampling signals for an integrated circuit device
US7095789B2 (en) * 2004-01-28 2006-08-22 Rambus, Inc. Communication channel calibration for drift conditions
US8422568B2 (en) 2004-01-28 2013-04-16 Rambus Inc. Communication channel calibration for drift conditions
US7400670B2 (en) 2004-01-28 2008-07-15 Rambus, Inc. Periodic calibration for communication channels by drift tracking
US6961862B2 (en) * 2004-03-17 2005-11-01 Rambus, Inc. Drift tracking feedback for communication channels
US7079446B2 (en) 2004-05-21 2006-07-18 Integrated Device Technology, Inc. DRAM interface circuits having enhanced skew, slew rate and impedance control
US8099638B2 (en) * 2004-11-12 2012-01-17 Ati Technologies Ulc Apparatus and methods for tuning a memory interface
US7509515B2 (en) * 2005-09-19 2009-03-24 Ati Technologies, Inc. Method and system for communicated client phase information during an idle period of a data bus
US7571267B1 (en) 2006-03-27 2009-08-04 Integrated Device Technology, Inc. Core clock alignment circuits that utilize clock phase learning operations to achieve accurate clocking of data derived from serial data streams having different relative skews
US7706996B2 (en) * 2006-04-21 2010-04-27 Altera Corporation Write-side calibration for data interface
US8504865B2 (en) * 2007-04-20 2013-08-06 Easic Corporation Dynamic phase alignment
TWI421694B (en) * 2009-08-26 2014-01-01 Asustek Comp Inc Memory controlling method
US8943242B1 (en) 2012-03-30 2015-01-27 Integrated Device Technology Inc. Timing controllers having partitioned pipelined delay chains therein
US9846606B2 (en) * 2014-11-07 2017-12-19 Mediatek Inc. Storage device calibration methods and controlling device using the same
US9607672B2 (en) 2014-11-14 2017-03-28 Cavium, Inc. Managing skew in data signals with adjustable strobe
US9502099B2 (en) 2014-11-14 2016-11-22 Cavium, Inc. Managing skew in data signals with multiple modes
US9570128B2 (en) * 2014-11-14 2017-02-14 Cavium, Inc. Managing skew in data signals
CN108241586B (en) * 2016-12-27 2020-03-06 慧荣科技股份有限公司 Controller circuit and estimated delay compensation method
KR102378384B1 (en) * 2017-09-11 2022-03-24 삼성전자주식회사 Operation method of nonvolatile memory device and operation method of memory controller
CN109656846B (en) * 2018-12-20 2020-11-17 湖南国科微电子股份有限公司 Method and device for optimizing available delay parameter interval of electronic terminal and memory
US11210029B2 (en) * 2020-05-18 2021-12-28 Micron Technology, Inc. Generating memory array control signals
US11361815B1 (en) 2020-12-24 2022-06-14 Winbond Electronics Corp. Method and memory device including plurality of memory banks and having shared delay circuit
CN117478107B (en) * 2023-12-28 2024-02-27 芯光智网集成电路设计(无锡)有限公司 Delay calibration method, transmitting end and source synchronous communication system

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1999046687A1 (en) * 1998-03-12 1999-09-16 Hitachi, Ltd. Data transmitter
US6041419A (en) * 1998-05-27 2000-03-21 S3 Incorporated Programmable delay timing calibrator for high speed data interface

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4791404A (en) * 1986-03-03 1988-12-13 Tektronix, Inc. Predictive time base control circuit for a waveform system
US4755951A (en) * 1986-03-03 1988-07-05 Tektronix, Inc. Method and apparatus for digitizing a waveform
IL96808A (en) 1990-04-18 1996-03-31 Rambus Inc Integrated circuit i/o using a high performance bus interface
US5163162A (en) * 1990-11-14 1992-11-10 Ibm Corporation System and method for data recovery in multiple head assembly storage devices
US5266952A (en) * 1992-03-30 1993-11-30 Hughes Aircraft Company Feed forward predictive analog-to-digital converter
US5917760A (en) 1996-09-20 1999-06-29 Sldram, Inc. De-skewing data signals in a memory system
US5953263A (en) 1997-02-10 1999-09-14 Rambus Inc. Synchronous memory device having a programmable register and method of controlling same
US6016282A (en) 1998-05-28 2000-01-18 Micron Technology, Inc. Clock vernier adjustment
US6349399B1 (en) * 1998-09-03 2002-02-19 Micron Technology, Inc. Method and apparatus for generating expect data from a captured bit pattern, and memory device using same
US6430696B1 (en) * 1998-11-30 2002-08-06 Micron Technology, Inc. Method and apparatus for high speed data capture utilizing bit-to-bit timing correction, and memory device using same

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1999046687A1 (en) * 1998-03-12 1999-09-16 Hitachi, Ltd. Data transmitter
US6041419A (en) * 1998-05-27 2000-03-21 S3 Incorporated Programmable delay timing calibrator for high speed data interface

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9099194B2 (en) 2001-10-22 2015-08-04 Rambus Inc. Memory component with pattern register circuitry to provide data patterns for calibration

Also Published As

Publication number Publication date
JP4649629B2 (en) 2011-03-16
EP1927988A1 (en) 2008-06-04
EP2077558A1 (en) 2009-07-08
ATE492881T1 (en) 2011-01-15
ATE384327T1 (en) 2008-02-15
TW588375B (en) 2004-05-21
US6674378B2 (en) 2004-01-06
DE60139355D1 (en) 2009-09-03
EP1282677A2 (en) 2003-02-12
KR20030013407A (en) 2003-02-14
US20030122696A1 (en) 2003-07-03
EP2077558B1 (en) 2010-12-22
ATE437438T1 (en) 2009-08-15
JP2003532969A (en) 2003-11-05
AU2001259571A1 (en) 2001-11-20
US6606041B1 (en) 2003-08-12
DE60132445T2 (en) 2008-08-14
KR100580740B1 (en) 2006-05-15
EP1927988B1 (en) 2009-07-22
DE60143726D1 (en) 2011-02-03
DE60132445D1 (en) 2008-03-06
WO2001085884A2 (en) 2001-11-15
EP1282677B1 (en) 2008-01-16
CN1636248A (en) 2005-07-06
CN100407181C (en) 2008-07-30
CN101320593A (en) 2008-12-10

Similar Documents

Publication Publication Date Title
WO2001085884A3 (en) Predictive timing calibration for memory devices
JP4065234B2 (en) Data recovery device for synchronous chip-chip system
JP5153094B2 (en) DLL device and DLL clock generation method
KR20100078987A (en) Semiconductor device
KR20080001861A (en) Circuit for removing skew and method for removing skew by the same
US9257968B2 (en) Duty cycle correction circuit and operation method thereof
US8144531B2 (en) Latency control circuit, semiconductor memory device including the same, and method for controlling latency
KR20110060740A (en) Apparatus and method for controlling the operation timing of semiconductor memory
KR100845804B1 (en) Circuit and method for controlling clock in semiconductor memory apparatus
KR20020055910A (en) Delay Locked Loop in Semiconductor Device
WO2000031915A3 (en) A method and a circuit for retiming a digital data signal
JP2005339519A (en) Resynchronization circuit
JP2005339001A (en) Phase synchronization circuit
JPH0431211B2 (en)
CN209088923U (en) Delay locked loop circuit and semiconductor memory
CN208939923U (en) Delay locked loop circuit and semiconductor memory
CN209088924U (en) Delay locked loop circuit and semiconductor memory
WO2013038562A1 (en) Transmitting system, transmitting apparatus, receiving apparatus, and transmitting method
JP2008134926A (en) Synchronization circuit
KR100951669B1 (en) Circuit and method for generating output enable signal in semiconductor memory apparatus
JP2000251473A (en) Semiconductor integrated circuit
KR20060114234A (en) Circuit for generating delay locking clock and method for generating delay locking clock
JP2007123988A (en) Receiving circuit for start-stop synchronous communication
KR20030084499A (en) Synchrounous Memory device
JPWO2013038562A1 (en) Transmission system, transmission apparatus, reception apparatus, and transmission method

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A2

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EE ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NO NZ PL PT RO RU SD SE SG SI SK SL TJ TM TR TT TZ UA UG UZ VN YU ZA ZW

AL Designated countries for regional patents

Kind code of ref document: A2

Designated state(s): GH GM KE LS MW MZ SD SL SZ TZ UG ZW AM AZ BY KG KZ MD RU TJ TM AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE TR BF BJ CF CG CI CM GA GN GW ML MR NE SN TD TG

121 Ep: the epo has been informed by wipo that ep was designated in this application
DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
AK Designated states

Kind code of ref document: A3

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EE ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NO NZ PL PT RO RU SD SE SG SI SK SL TJ TM TR TT TZ UA UG UZ VN YU ZA ZW

AL Designated countries for regional patents

Kind code of ref document: A3

Designated state(s): GH GM KE LS MW MZ SD SL SZ TZ UG ZW AM AZ BY KG KZ MD RU TJ TM AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE TR BF BJ CF CG CI CM GA GN GW ML MR NE SN TD TG

WWE Wipo information: entry into national phase

Ref document number: 1020027015063

Country of ref document: KR

WWE Wipo information: entry into national phase

Ref document number: 2001933122

Country of ref document: EP

WWE Wipo information: entry into national phase

Ref document number: 018112277

Country of ref document: CN

WWP Wipo information: published in national office

Ref document number: 2001933122

Country of ref document: EP

WWP Wipo information: published in national office

Ref document number: 1020027015063

Country of ref document: KR

WWG Wipo information: grant in national office

Ref document number: 1020027015063

Country of ref document: KR

WWG Wipo information: grant in national office

Ref document number: 2001933122

Country of ref document: EP