WO2001088719A3 - Speed cache having separate arbitration for second-level tag and data cache rams - Google Patents

Speed cache having separate arbitration for second-level tag and data cache rams Download PDF

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Publication number
WO2001088719A3
WO2001088719A3 PCT/US2001/013269 US0113269W WO0188719A3 WO 2001088719 A3 WO2001088719 A3 WO 2001088719A3 US 0113269 W US0113269 W US 0113269W WO 0188719 A3 WO0188719 A3 WO 0188719A3
Authority
WO
WIPO (PCT)
Prior art keywords
cache
memory
data memory
tag
arbitration
Prior art date
Application number
PCT/US2001/013269
Other languages
French (fr)
Other versions
WO2001088719A2 (en
Inventor
Rajasekhar Cherabuddi
Original Assignee
Sun Microsystems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sun Microsystems Inc filed Critical Sun Microsystems Inc
Priority to AU2001257238A priority Critical patent/AU2001257238A1/en
Publication of WO2001088719A2 publication Critical patent/WO2001088719A2/en
Publication of WO2001088719A3 publication Critical patent/WO2001088719A3/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0855—Overlapped cache accessing, e.g. pipeline
    • G06F12/0857—Overlapped cache accessing, e.g. pipeline by multiple requestors
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893—Caches characterised by their organisation or structure
    • G06F12/0897—Caches characterised by their organisation or structure with two or more cache hierarchy levels
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0831—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means

Abstract

A cache system for use in computer systems has a tag memory (412), a data memory (416), and a cache control unit (401). The tag memory (412) and data memory (416) are provided with separate address lines. The cache control unit (401) has a first arbitration unit (405) for arbitrating access to the tag memory (412) and a second arbitration unit (406) for arbitrating access to the data memory (416). Providing separate arbitration units (405, 406) for the tag memory (412) and the data memory (416) allows access of the data memory (416) for a following cycle of a multicycle cache-line read while the tag memory (412) is accessed by a snoop controller (402).
PCT/US2001/013269 2000-05-17 2001-04-24 Speed cache having separate arbitration for second-level tag and data cache rams WO2001088719A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU2001257238A AU2001257238A1 (en) 2000-05-17 2001-04-24 Speed cache having separate arbitration for second-level tag and data cache rams

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US57261100A 2000-05-17 2000-05-17
US09/572,611 2000-05-17

Publications (2)

Publication Number Publication Date
WO2001088719A2 WO2001088719A2 (en) 2001-11-22
WO2001088719A3 true WO2001088719A3 (en) 2002-03-07

Family

ID=24288605

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2001/013269 WO2001088719A2 (en) 2000-05-17 2001-04-24 Speed cache having separate arbitration for second-level tag and data cache rams

Country Status (2)

Country Link
AU (1) AU2001257238A1 (en)
WO (1) WO2001088719A2 (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5692152A (en) * 1994-06-29 1997-11-25 Exponential Technology, Inc. Master-slave cache system with de-coupled data and tag pipelines and loop-back
US5809537A (en) * 1995-12-08 1998-09-15 International Business Machines Corp. Method and system for simultaneous processing of snoop and cache operations

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5692152A (en) * 1994-06-29 1997-11-25 Exponential Technology, Inc. Master-slave cache system with de-coupled data and tag pipelines and loop-back
US5809537A (en) * 1995-12-08 1998-09-15 International Business Machines Corp. Method and system for simultaneous processing of snoop and cache operations

Also Published As

Publication number Publication date
AU2001257238A1 (en) 2001-11-26
WO2001088719A2 (en) 2001-11-22

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