WO2002000004A2

WO2002000004A2 - Detrimental latch-up avoidans in digital circuits

Info

Publication number: WO2002000004A2
Application number: PCT/SE2001/001556
Authority: WO
Inventors: Erik Plesner; Morten Skov Hansen
Original assignee: Telefonaktiebolaget Lm Ericsson (Publ)
Priority date: 2001-07-05
Filing date: 2001-07-05
Publication date: 2002-01-03
Also published as: WO2002000004A3; AU2001271166A1

Abstract

The present invention relates to methods and arrangement to prevent detrimental latch-up in gates located in two independently powered supply domains. The gates are mutually connected via a bi-directional interface between the domains, and a voltage surveillance circuit is associated with the domains. The method comprises the following steps: detecting in the surveillance circuit, an improper supply of power to at least one domain of the two domains; generating an inhibit signal in the surveillance circuit; preventing logic high levels for signals on the bi-directional interface between gates located in the two domains.

Description

DETRIMENTAL LATCH-UP AVOIDANCE

TECHNICAL FIELD OF THE INVENTION

The present invention relates to a method and an arrangement to prevent detrimental latch-up in digital circuits located in domains with different power supplies.

DESCRIPTION OF RELATED ART

It is a well-known fact that latch-up is a detrimental parasitic effect in CMOS chips. Under certain conditions, a parasitic junction would be created in a CMOS integrated circuit, resulting in a latch-up and possibly destruction of the CMOS integrated circuit. In figure 1, a CMOS-inverter is disclosed as prior art. The CMOS-inverter comprises a PMOS- transistor Ql and an NMOS-transistor Q2. The latch-up effect is emphasised in figure 1 by an equivalent parasitic bipolar circuit. Latch-up causes a short between power supply V_cc and ground GND. The latch-up effect in the substrate is modelled in figure 1 by bipolar transistors Tl and T2 and by resistors Rs and Rw. When currents in the substrate cause voltage drops in excess of a threshold voltage V_th across any path in the substrate, modelled by the parasitic resistors Rs and Rw, latch-up is triggered. If the substrate ..current through Rs causes Tl to conduct, this will increase the current through Rw, and when the voltage across Rw exceeds the threshold voltage, T2 will start to conduct too. The current flowing through the latch-up path will further extend the area where the voltage drop is exceeding the threshold voltage. This lowers the resistance of Rs and Rw in the equivalent circuit, which again increases the current. Hence a self-perpetuating effect.

The inputs of most CMOS IC's contain protection diodes.. These diodes protect the logic circuits on a chip from voltages outside a range - V_Λ V_CC + V_A . If the input voltage V_m raises above V_cc + V_th the protection diode towards V_cc will start to conduct. If V_M raises high above V_cc + V_lh with high drive strength, the current through the protection diode may drive the substrate near the protection diode into latch-up. This can happen in circuits with several supply domains, if one supply domain has a power supply failure while another one, supplying V_m , is fully powered.

When the input of a CMOS transistor stage changes from logic high to logic low or vice versa, both the N- and the P- transistor will be open (conducting) for a short period of time during the transition. During this time V_cc is effectively shortened to ground, but because the duration is short this is not a problem. If the input of a CMOS transistor stage is held in the logic undefined range between logic high and logic low, the transistor stage may be caught at a point of its switching characteristics, where both the N- and the P-transistor are open at the same time. This will cause an excessive current due to the shorting of

V_cc and ground, and may cause latch-up due to the reasons explained above.

In the US patent US 5,392,186 an electrical protection circuit is disclosed. Under certain conditions a paras'itic junction would be created in a CMOS integrated circuit, resulting in the latch-up and possibly destruction of the CMOS integrated circuit. US 5,392,186 discloses an electrical protection circuit that detects and takes care of the problem. According to the US patent, when a latch-up condition exists, power from one source is deprived from the CMOS integrated circuits, whereby the circuits are preserved. The disadvantages with this solution are that devises used to switch off power to any supply take up PCB real estate, are expensive, dissipate heat/power, cause losses, may have poor reliability (mechanical relays) or may be difficult to implement (monolithic IC's).

SUMMARY OF THE INVENTION

The present invention solves the problem with efficient avoidance of self-perpetuating detrimental latch-up conditions caused by latch-up in mutually connected CMOS- gates located in different independently powered domains after improper power supply to at least one domain. The self-perpetuating detrimental latch-up may cause damage to CMOS-gates within the domains and has to be avoided.

The problem is solved by the invention by detecting the improper supply of power to the at least one domain and by preventing logic high levels on interfaces between gates located in the different domains.

More in detail, the invention in a first aspect discloses a method and an arrangement to prevent detrimental latch-up in CMOS-gates located in two independently powered supply domains . The gates are mutually connected via a bi- directional interface between the domains. A voltage surveillance circuit is associated with the domains.. The method according to this first aspect of the invention comprises steps like detecting in the surveillance circuit an improper supply of power to at least one domain, generate an inhibit signal in the surveillance circuit and prevent logic high levels for signals on the bi-directional interface in one or both directions between gates located in the two domains .

The invention in a second aspect discloses a method and an arrangement to prevent detrimental latch-up in CMOS-gates located in a plurality of power supply domains. The gates are mutually connected via bi-directional interfaces between the domains. A voltage surveillance circuit is associated with the domains . The method according to this second aspect of the invention comprises steps like detecting in the surveillance circuit an improper power supply to at least one domain of the plurality of domains, generate an inhibit signal ^■ in the surveillance circuit and prevent logic high levels for signals on all bi-directional interfaces between gates in the domains, in both directions.

In yet another aspect of the invention, preventing of detrimental latch-up in CMOS-gates located in dependently powered supply domains is disclosed.

The object of the invention is to prevent destruction of CMOS integrated circuits located in different power supply domains, i.e. to avoid detrimental latch-up before self- perpetuation.

An advantage with the invention is that detrimental latch-up is effectively prevented from occurring.

Another advantage with the invention is that it is not necessary to use any device to switch off the power to any supply domain.

Yet another advantage is the effective latch-up prevention in the design of circuits, where some parts of the circuit are intentionally switched-off in order to save power.

Yet another advantage is the small amount PCB real estate that has to be used.

Yet other advantages are that the solution is less expensive, does not dissipate heat/power, does not cause losses or have poor reliability.

Yet another advantage is that the solution is easy to implement. DESCRIPTION OF THE DRAWINGS

Figure 1 is a CMOS-gate displayed on a substrate level. The figure is disclosed as prior art.

Figure 2 is a block schematic illustration of two power supply domains . CMOS-gates in the two domains are connected via interfaces. A voltage surveillance circuit is monitoring power supply to the two domains . The figure shows a so- called generalised description for n supply domains.

Figure 3 is a flow chart disclosing the most important steps of a method according to the invention when two domains are connected via interface as disclosed in figure 2.

Figure 4 is a block schematic illustration of multiple power supply domains whereby CMOS-gates in the different domains are connected via interfaces. A voltage surveillance circuit monitors power supply to all domains. In this figure, a so- called simplified description for n supply domains can be seen.

Figure 5 is a block schematic illustration of dependent power supply domains . The figure shows a so-called simplified description for dependent supply domains.

Figure 6 is an arrangement built up by discrete components according to the invention.

DESCRIPTION OF PREFERRED EMBODIMENTS

Below, three embodiments will be explained and disclosed with figures. A first embodiment, the so-called generalised description for n supply domains can be seen in figure 2. A second . embodiment, the so-called simplified description for n supply domains can be seen in figure 4. A third embodiment, the so-called simplified description for dependent supply domains is disclosed in figure 5.

Figure 2 discloses in the first embodiment an arrangement for preventing detrimental latch-up according to the invention. The arrangement comprises CMOS-inverters INV1,

INV2, INV3 and INV4 of identical type, located in two different power supply domains iV_j and N₂ . It is to be observed that more than two mutually connected domains often exist, even though only two domains are discussed and displayed in figure 2. The first power supply domain N_t comprises the inverters INV1 and INV2. The inverter INV1 is the same CMOS-inverter that already has been explained in the description of related art. The first inverter INV1 comprises the already mentioned CMOS-gates Ql and Q2. The second inverter is identical and comprises two CMOS-gates Q3 and Q4. A second power domain N₂ comprises a third inverter INV3 existing of the CMOS-gates Q5 and Q6. A fourth inverter INV4 in N₂ comprises two CMOS-gates Q7 and Q8. The first power supply domain N_j is supplied with supply power VCC1 from a first power supply unit DC1. The second power supply domain N₂ is supplied with supply power VCC2 from a second power supply unit DC2. The two power supply domains have common ground GND. The output of the first inverter INV1 is connected to the input of the fourth inverter INV4 via an interface J₁₂. In the same way, the output of the third inverter INV3 is connected to the input of the second inverter INV2 via an interface 7₂₁. A surveillance circuit SURV is constantly monitoring the supply voltage delivered from the two supply units DC1 and DC2. An output of the surveillance circuit is connected to the bi-directional interface I_{l 2} , I_2Λ . By means of inhibit signals S,S_Ϊ or S₂ , the surveillance circuit SURV is able to put the interface out of action in one or both of the two directions, i.e. to prevent logic high levels on the bi-directional interface between inverters located in the two power domains N_j and N₂. A first inhibit signal S₁ affects a control buffer, in this example a tri-state buffers PI, in the interface in direction from the first inverter INV1 to the fourth inverter INV4, to be disabled. A second inhibit signal S₂ affects a tri-state buffers P2 in the interface in direction from the third inverter INV3 to the second inverter INV2, to be disabled. A common inhibit signal S affect both buffers simultaneously. It is to be noted that there are several ways of preventing logic high levels on the interfaces when the inhibit signal is low, e.g by using AND-gates instead of tri-state buffers or by using a reset-signal.

Two different latch-up conditions will now be further explained by means of figure 2. A first latch-up condition exists when an output of the powered first domain N_t drives a logical high into an input of a not powered second domain N₂ , i.e. VCC2=0V. This is the case earlier mentioned when V_m raises high above V_cc + V_ih with high drive strength. This can for example happen when power is intentionally or unintentionally switched-off. A second latch-up condition exists when unstable power supply to the first domain N_x causes an output of domain N_λ to drive an undefined logic level into an input of the second domain N₂. This is the case earlier mentioned when a transistor stage is caught at a point of its switching characteristics, where both the Island the P-transistor are open at the same time. The first latch-up condition exists, when the second power supply unit DC2 fails to deliver power to the second domain N₂ , while the first domain N_λ is fully powered. In this latch-up condition, an output from the first inverter INV1 of the powered first domain N, drives a logical high into an input of the fourth inverter INV4 of the not powered second domain N₂. This situation causes latch-up condition in the fourth inverter as earlier explained, i.e. when V_m raises high above V_cc + V_jh with high drive strength. The method according to the invention avoiding this first latch-up condition will now be further analysed. The method comprises the following steps:

- The surveillance circuit SURV detects a stable power supply value VCCl exceeding a pre-set limit value, received from the first power supply unit DC1.

The surveillance circuit SURV detects an improper power supply value VCC2 below the pre-set limit value, received from the second power supply unit DC2.

The first inhibit signal S_x is activated (active low) .

- The tri-state buffers PI in the interface in direction from the first inverter INV1 to the second inverter INV2, is affected to be activated and thereby prevent logic high level on the interface I_{1 2} between INV1 and INV4.

By preventing logic high levels on the interface I_{l 2} between INVl and INV4, the first latch-up condition will never occur in the fourth inverter INV4.

The second latch-up condition arises, when the first power supply unit DC1 fails to deliver stable power so that the first domain N_λ has unstable power supply while the second domain N₂ is fully powered. In this latch-up condition, an output from the first inverter INVl of the first domain N_t drives an undefined logic level into an input of the fourth inverter INV4 of the fully powered second domain N₂. This situation may cause latch-up condition in the fourth inverter, as earlier explained. Experience shows that CMOS inverters with unstable power supplies prefer to output VCC/2, which is the worst level for the CMOS inputs connected to improperly powered outputs. The method according to the invention avoiding the second latch-up condition will now be further analysed. The method comprises the following steps:

The surveillance circuit SURV detects a stable power supply value VCC2 exceeding a pre-set limit value, received from the second power supply unit DC2.

- The surveillance circuit SURV detects an unstable supply of power received from the first power supply unit DC1.

The first inhibit signal S_l is activated (active low) .

The tri-state buffers Pi in the interface in direction from the first inverter INVl to the fourth inverter INV4, is affected to be activated and thereby prevent logic high level on the interface I_{1 2} between INVl and INV4.

By preventing logic high levels on the interface J₁₂ between

INVl and INV4, the second latch-up condition will never occur in the fourth inverter INV4.

It is to be noted that detection of the two different latch- up conditions of course can be combined. In this case, the common inhibit signal S prevents logic high levels simultaneously in both directions of the interface, independent on whether latch-up condition 1 or latch-up condition 2 caused the problem. In figure 3 the most essential steps of the above two

^'methods are shown in a flow chart. The flow chart is to be read together with the earlier shown figure 2. The object of the flow chart is to make the behaviour of the surveillance circuit more clear. The most essential steps are as follows.

The surveillance circuit SURV detects an improper power supply value below a pre-set limit value (loss of power) in any supply domain. The blocks 101-103 disclose this step.

- The domain N2 is pointed out in the surveillance circuit as the domain having low power. A block 104 discloses this step.

The first inhibit signal S, is activated (active low) . A block 106 discloses this step.

- The tri-state buffers PI in the interface in direction from the first domain Nl to the second domain N2, is affected to be activated and thereby prevent logic high level for signals on the interface I_{l 2} between INVl and INV4. A block 107 discloses this step.

- In case the domain Nl is pointed out instead of N2 (block 104), as the domain having low power, the second innibit signal S₂ is activated (active low) . A block 105 discloses this step.

The tri-state buffers P2 in the interface in direction from the second domain N2 to the first domain Nl, is affected to be activated and thereby prevent logic high level for signals on the interface I₂₁ between INV3 and INV2. A block 108 discloses this step.

If the surveillance circuit SURV instead detects an unstable power supply and not a value below a pre-set limit value (block 101-103) , this step is disclosed in figure 3 by the blocks 101, 102 and 109.

The domain Nl is now pointed out as the one having unstable power. A block 110 discloses this step.

- The first inhibit signal S_x is activated (active low) . A block 112 discloses this step.

The tri-state buffers PI in the interface in direction from the first domain Nl to the second domain N2, is affected to be activated and thereby prevent logic high level on the interface I_{l 2} between INVl and INV4. A block 114 discloses this step.

In case the domain N2 is pointed out instead of Nl (block 110) , as the domain having unstable power, the second inhibit signal S₂ is activated (active low) . A block 111 discloses this step.

The tri-state buffers P2 in the interface in direction from the second domain N2 to the first domain Nl, is affected to be activated and thereby prevent logic high level on the interface I_{2 l} between INV3 and INV2. A block 113 discloses this step.

Figure 4 discloses a second embodiment of the invention. This is the so-called simplified description for n supply domains. In the figure, four powers supply domains n_i,n_j,n_k and n_t are shown. Each domain comprises CMOS-inverters of the same type as earlier discussed in the previous figures. Each domain is individually supplied with power from different power supply units DC_l,DC_j,DC_k and DC, . Domain «,- is fed with power V_i from unit DC_i , domain ti_j is fed with power V_j from unit DC₇ , domain n_k is fed with power V_k from unit DC_k and domain n, is fed with power V, from unit DC, . Bidirectional interfaces I, ,I_jj.,I_kj are located between the powers supply domains. Each interface comprises tri-state buffers in both directions . The interface I, , is located between the domains n, and ri_j , the interface I_jJc is located between the domains n . and n_k , and the interface I_k, between the domains n_k and n, . A surveillance circuit SU is constantly monitoring the supply voltage delivered from the four supply units DC,, C_j,DC_k and DC, . An output of the surveillance circuit is connected to all tri-states buffers in the bi-directional interfaces I. .,1^,1^ . By means of an inhibit signal E, the surveillance circuit SU is able to affect the tri-state buffers and put the interfaces out of action in both directions, i.e. to prevent logic high levels on the bi-directional interface between inverters located in the power domains . In many circumstances it does not make sense to operate one part of the circuit if there is a power supply failure in another part of the circuit. The method shows this somewhat simplified version of the invention. In principle, the surveillance circuit SU detects an improper supply of power to at least one of the power supply domains n,,n .,n_k and n, . After detection of the improper power supply which can be loss of power or unstable power or any other effect influencing the power negatively, the surveillance circuit prevents logic high levels on the bi-directional interfaces I, .,I^_k, I_{k l} between all gates in the four domains n_i,n_j,n_k,n, , in both directions. This simplified method comprises the following steps:

The surveillance circuit SU detects, in this example, an improper power supply value V_k (loss of power or unstable power) , received from the power supply unit DC_k . The inhibit signal E is activated (active low) .

- Tri-state buffers interfaces I _i,I _!<k,I_kJL in both directions are affected to be activated and thereby prevent logic high levels for signals on interfaces between the four domains .

The third embodiment, the so-called simplified description for dependent supply domains, can be seen in figure 5. A first voltage Ul is converted to a second voltage U2 in a first converter DC1/DC2. The second voltage U2 supply power to a first power supplies domain Dl. In figure 5a can be seen how the second voltage U2 is converted to a third voltage U3 in" a second converter DC2/DC3. The third voltage U3, supply power to a second power supplies domain D2. As an alternative which can be seen in figure 5b, the second voltage U2 is filtered into a filtered second voltage U2f by a filter F. The filtered second voltage U2f, supply power to the second power supplies domain D2. Figure 5a and 5b show two examples of dependent domains . A bi-directional interface J_{ι 2 > 21} is located between the two domains Dl and D2. In both cases, disclosed in figure 5a and figure 5b, the power to the second domain D2 depends on the power to the first domain Dl, therefore the earlier mentioned first latch-up condition can not occur on the interface I_{2 l} . The second latch-up condition can only occur on the interface I_{l 2}. The method according to the invention comprises the following steps;

detecting in the surveillance circuit, an unstable supply of power to the first domain Dl;

generating an inhibit signal in the surveillance circuit (not shown in figure 5) ; - preventing logic high levels for signals on the bidirectional interface I ₂ between the two domains Dl, D2, in direction off the first domain Dl .

Three different embodiments have been explained above, namely • the first embodiment, the so-called generalised description for n supply domains, the second embodiment, the so-called simplified description for n supply domains and the third embodiment, the so-called simplified description for dependent supply domains. In the first embodiment, each bi-directional interface between two domains is autonomous controlled, while in the second embodiment all interfaces between the domains are simultaneously controlled. In the first embodiment, a separate surveillance circuit is used for each interface between the domains and shuts down only connections across this interface. The solutions in the second and third embodiments are somewhat simpler compared to the first embodiment.

In figure 6, yet another example of an arrangement according to the invention can be seen. A first converter CONVl converts an electric voltage VI to an electric voltage V2. A second converter C0NV2 converts the electric voltage VI to an electric voltage V3. In this example V1=48V, V2=2,7V and V3=3,3V. The voltages V2 and V3 are detected by a combined voltage supervision chip SC. The chip SC has two reset outputs, one for each supply unit U2 and U3. In figure 6, only RST3 is shown. Both reset outputs are active at the same time, and both reset outputs are active low. U2 is in this example a 3,3V micro-controller. The address-bus (A19:l) is held low, when "negative reset" nRS is low. The bi-directional data bus D(15:0) is Hi-Z when nRS is low. "negative chip select" nCSO, "negative read" nRD and "negative write" nWR are active low signals which are held high when nRS is low. Therefore these signals are passed through a tristate driver TD which enters the Hi-Z mode, when nRS is low. Pull-up resistors R1-R3 on the three control inputs of U3, which is a flash PROM, ensures that the levels on these signals remain high when tri-state drivers are in HI-Z mode. U3 is a 2,7V flash PROM. The bi- directional data bus D(15:0) is Hi-Z when nRS is low.

Different variations are possible within the scope of the invention. There are for example several ways of preventing logic high levels on the interfaces when the inhibit signal is low, e.g. by using AND-gates instead of tri-state buffers or by using a reset-signal. Only two power supply domains are shown in figure 2 and 5, but these two domains can of course be an integral part of a plurality of domains. This is also the case for the embodiment displayed in figure 4 where four domains are displayed. The invention is thus not restricted to the above described and illustrated exemplifying embodiments, and modifications can be made within the scope of the claims .

Claims

1. Method to prevent detrimental latch-up in gates (INV1- INV4) located in two independently powered supply domains ( N₁₃N₂ ) , whereby the gates are mutually connected via a bi-directional interface ( I_{i 2},I_{2 ι} ) between the domains, and whereby a voltage surveillance circuit (SURV) is associated with the domains, which method comprises the following steps:

detecting in the surveillance circuit (SURV) , an improper supply of power to at least one domain ( N₂ ) of the two domains ( N₁₃N₂ ) ;

generating an inhibit signal ( S,S₁,S₂ ) in the surveillance circuit (SURV);

- preventing logic high levels for signals on the bi- directional interface { I _>2^_2,\ between gates (INV1-INV4) located in the two domains ( N_λ,N₂ ) .

2. Method according to claim 1 whereby the improper supply of power represents power supply below a predetermined value, which method comprises the following further step:

- preventing logic high levels for signals on the bidirectional interface (7_ι>2) between the two domains

( N_X,N₂ ) , in direction towards the at least one domain ( N₂ ) .

3. Method according to claim 1 whereby the improper power supply represents unstable power, which method comprises the following further steps : preventing logic high levels for signals on the bidirectional interface ( I_2, ) between the two domains ( N_{l 5}N₂ ) , in direction off the at least one domain ( N₂ ) .

4. Method to prevent detrimental latch-up in gates located in ^' a plurality of independently powered power supply domains ( n_i,n_j,n_k,n, ) , whereby the gates are mutually connected via bi-directional interfaces ( I_{i j},I_{j k},I_{k l} ) between the domains, and whereby a voltage surveillance circuit (SU) is associated with the domains, which method comprises the following steps:

detecting in the surveillance circuit (SU) , an improper power supply to at least one domain of the plurality of domains ( n, , ri_j ,n_k,n, ) ;

generating an inhibit signal (E) in the surveillance circuit (SU) ;

preventing logic high levels for signals on all bidirectional interfaces ( I _j,I _{j k},I_{k l} ) between gates in the domains ( n_i,n_j,n_k,n, ) , in both directions.

5. Method according to claim 4 whereby the improper power supply represents loss of power supply.

6. Method according to claim 4 whereby the improper power supply represents unstable power supply.

7. Method to prevent detrimental latch-up in gates located in two power supply domains (Dl, D2) , whereby power (U3,U2f) supplied to a second domain (D2) is dependent upon power (U2) supplied to a first domain (Dl) and whereby the gates are mutually connected via a bidirectional interface ( J_{ι>2> 21} ) between the domains, and whereby a voltage surveillance circuit is associated with the first domain (Dl) , which method comprises the following steps :

detecting in the surveillance circuit, an unstable supply of power to the first domain (Dl) ;

- generating an inhibit signal in the surveillance circuit;

- preventing logic high levels for signals on the bidirectional interface (i,_>2) between the two domains (Dl, D2), in direction off the first domain (Dl) .

8. Method to prevent detrimental latch-up in gates located in two power supply domains (Dl, D2) , whereby power

(U3,U2f) supplied to a second domain (D2) is dependent upon power (U2) supplied to a first domain (Dl) and whereby the gates are mutually connected via a bidirectional interface ( J_{ι 2}, ₂₁ ) between the domains, and whereby a voltage surveillance circuit is associated with the domains, which method comprises the following steps :

detecting in the surveillance circuit (SURV) , an improper supply of power to the second domain ( D₂ ) ;

- generating an inhibit signal in the surveillance circuit;

preventing logic high levels for signals on the bidirectional interface ( ₁₂, _2>ι) between the two domains

{ D_X ,D₂ ) .

9. Method according to claim 8 whereby the improper supply of power supply represents power supply below a predetermined value, which method comprises the following further step: - preventing logic high levels for signals on the bidirectional interface ( ₁₂) between the two domains

( D ,D₂ ) , in direction towards the second domain (D₂).

10. Method according to claim 8 whereby the improper power supply represents unstable power supply, which method comprises the following further steps:

- preventing logic high levels for signals on the bidirectional interface ( _2>ι) between the two domains

( D_l,D₂ ) , in direction off the second domain ( D₂ ) .

11. Arrangement to prevent detrimental latch-up in gates (INV1-INV4) located in two independently powered supply domains ( N_λ,N₂ ) , whereby the gates are mutually connected via a bi-directional interface ( ₁₂,/₂₁ ) between the domains, and whereby a voltage surveillance circuit (SURV) is associated with the domains, which arrangement comprises :

- means to detect in the surveillance circuit (SURV), an improper supply of power to at least one domain ( N₂ ) of the two domains ( N_X,N₂ ) ;

- means for generating an inhibit signal ( S,S₁,S₂ ) in the surveillance circuit (SURV) ;

- means for preventing logic high levels for signals on the bi-directional interface ( ) between gates (INVl-

INV4) located in the two domains { N_λ,N₂ ) .

12. Arrangement according to claim 11 whereby the improper supply of power represents power supply below a predetermined value, which arrangement comprises: - means for preventing logic high levels for signals on the bi-directional interface ( J_1>2 ) between the two domains

( N₁,N₂ ) , in direction towards the at least one domain

( N₂ ) .

13. Arrangement according to claim 11 whereby the improper power supply represents unstable power supply, which arrangement comprises :

- means for preventing logic high levels for signals on the bi-directional interface (7_2>1) between the two domains ( N_{1 }}N₂ ) , in direction off the at least one domain ( N₂ ) .

14. Arrangement to prevent detrimental latch-up in gates located in a plurality of independently powered power supply domains ( n_i,ri_j,n_k,n, ) , whereby the gates are mutually connected via bi-directional interfaces { I, .,1._tk,I_kj ) between the domains, and whereby a voltage surveillance circuit (SU) is associated with the domains, which arrangement comprises:

- means for detecting in the surveillance circuit (SU) , an improper power supply to at least one domain of the plurality of domains ( n_i,n_j,n_k,n, ) ;

- means for generating an inhibit signal (E) in the surveillance circuit (SU) ;

- means to prevent logic high levels for signals on all bidirectional interfaces ( I, ,I_jιk,I_k ) between gates in the domains ( n_i,n_J,n_k,n, ) , in both directions.

15. Arrangement to prevent detrimental latch-up in gates located in two power supply domains (Dl, D2) , whereby power (U3,U2f) supplied to a second domain (D2) is dependent upon power (U2) supplied to a first domain (Dl) and whereby the gates are mutually connected via a bi-directional interface ( /₁₂»-^_2,ι ) between the domains, and whereby a voltage surveillance circuit is associated with the first domains, which arrangement comprises:

- means to detect in the surveillance circuit, an unstable supply of power to the first domain (Dl) ;

- means for generating an inhibit signal in the surveillance circuit;

- means to prevent logic high levels for signals on the bidirectional interface ( Jι_>2 ) between the two domains (Dl, D2), in direction off the first domain (Dl) .

16. Arrangement to prevent detrimental latch-up in gates located in two power supply domains (Dl, D2) , whereby power (U3,U2f) supplied to a second domain (D2) is dependent upon power (U2) supplied to a first domain

(Dl) and whereby the gates are mutually connected via a bi-directional interface ( I ₂,I_{2 l} ) between the domains, and whereby a voltage surveillance circuit is associated with the domains, which arrangement comprises:

- means to detect in the surveillance circuit (SURV) , an improper supply of power to the second domain ( D₂ ) ;

means for generating an inhibit signal in the surveillance circuit;

- means to prevent logic high levels for signals on the bi^¬ directional interface ( _lj2,/_2,ι) between the two domains i D ,D₂ ) .

17. Arrangement according to claim 16 whereby the improper supply of power supply represents power supply below a predetermined value, which arrangement comprises:

- means to prevent logic high levels for signals on the bi- directional interface ( J_ι>2 ) between the two domains

( D_X,D₂ ) , in direction towards the at least one domain ( D₂ ) .

18. Arrangement according to claim 16 whereby the improper power supply represents unstable power supply, which arrangement comprises:

- means to prevent logic high levels for signals on the bidirectional interface (7_2>1) between the two domains

( D₁,D₂ ) , in direction off the at least one domain (D₂).