WO2002000004A3 - Detrimental latch-up avoidans in digital circuits - Google Patents

Detrimental latch-up avoidans in digital circuits Download PDF

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Publication number
WO2002000004A3
WO2002000004A3 PCT/SE2001/001556 SE0101556W WO0200004A3 WO 2002000004 A3 WO2002000004 A3 WO 2002000004A3 SE 0101556 W SE0101556 W SE 0101556W WO 0200004 A3 WO0200004 A3 WO 0200004A3
Authority
WO
WIPO (PCT)
Prior art keywords
domains
latch
detrimental
avoidans
digital circuits
Prior art date
Application number
PCT/SE2001/001556
Other languages
French (fr)
Other versions
WO2002000004A2 (en
Inventor
Erik Plesner
Morten Skov Hansen
Original Assignee
Ericsson Telefon Ab L M
Erik Plesner
Morten Skov Hansen
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ericsson Telefon Ab L M, Erik Plesner, Morten Skov Hansen filed Critical Ericsson Telefon Ab L M
Priority to AU2001271166A priority Critical patent/AU2001271166A1/en
Priority to PCT/SE2001/001556 priority patent/WO2002000004A2/en
Publication of WO2002000004A2 publication Critical patent/WO2002000004A2/en
Publication of WO2002000004A3 publication Critical patent/WO2002000004A3/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0921—Means for preventing a bipolar, e.g. thyristor, action between the different transistor regions, e.g. Latchup prevention

Abstract

The present invention relates to methods and arrangement to prevent detrimental latch-up in gates located in two independently powered supply domains. The gates are mutually connected via a bi-directional interface between the domains, and a voltage surveillance circuit is associated with the domains. The method comprises the following steps: detecting in the surveillance circuit, an improper supply of power to at least one domain of the two domains; generating an inhibit signal in the surveillance circuit; preventing logic high levels for signals on the bi-directional interface between gates located in the two domains.
PCT/SE2001/001556 2001-07-05 2001-07-05 Detrimental latch-up avoidans in digital circuits WO2002000004A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
AU2001271166A AU2001271166A1 (en) 2001-07-05 2001-07-05 Detrimental latch-up avoidance
PCT/SE2001/001556 WO2002000004A2 (en) 2001-07-05 2001-07-05 Detrimental latch-up avoidans in digital circuits

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/SE2001/001556 WO2002000004A2 (en) 2001-07-05 2001-07-05 Detrimental latch-up avoidans in digital circuits

Publications (2)

Publication Number Publication Date
WO2002000004A2 WO2002000004A2 (en) 2002-01-03
WO2002000004A3 true WO2002000004A3 (en) 2002-05-16

Family

ID=20283974

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/SE2001/001556 WO2002000004A2 (en) 2001-07-05 2001-07-05 Detrimental latch-up avoidans in digital circuits

Country Status (2)

Country Link
AU (1) AU2001271166A1 (en)
WO (1) WO2002000004A2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JO2787B1 (en) 2005-04-27 2014-03-15 امجين إنك, Substituted Amid derivatives & methods of use
DE602007005289D1 (en) 2006-01-24 2010-04-29 St Microelectronics Sa Protection circuit for an integrated circuit against parasitic latch-up phenomena

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4353105A (en) * 1980-12-08 1982-10-05 National Semiconductor Corporation CMOS Latch-up protection circuit
JPS60257620A (en) * 1984-06-04 1985-12-19 Hitachi Ltd Cmos integrated circuit device
JPS61269417A (en) * 1985-05-23 1986-11-28 Nec Corp Complementary mos semiconductor integrated circuit
JPS61270917A (en) * 1985-05-27 1986-12-01 Toshiba Corp Semiconductor integrated circuit device
US4733105A (en) * 1985-09-04 1988-03-22 Oki Electric Industry Co., Ltd. CMOS output circuit
EP0720295A2 (en) * 1994-12-27 1996-07-03 Oki Electric Industry Company, Limited Semiconductor device
US5942932A (en) * 1997-08-26 1999-08-24 Nanoamp Solutions, Inc. Circuit and method for preventing latch-up in a CMOS semiconductor device

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4353105A (en) * 1980-12-08 1982-10-05 National Semiconductor Corporation CMOS Latch-up protection circuit
JPS60257620A (en) * 1984-06-04 1985-12-19 Hitachi Ltd Cmos integrated circuit device
JPS61269417A (en) * 1985-05-23 1986-11-28 Nec Corp Complementary mos semiconductor integrated circuit
JPS61270917A (en) * 1985-05-27 1986-12-01 Toshiba Corp Semiconductor integrated circuit device
US4733105A (en) * 1985-09-04 1988-03-22 Oki Electric Industry Co., Ltd. CMOS output circuit
EP0720295A2 (en) * 1994-12-27 1996-07-03 Oki Electric Industry Company, Limited Semiconductor device
US5942932A (en) * 1997-08-26 1999-08-24 Nanoamp Solutions, Inc. Circuit and method for preventing latch-up in a CMOS semiconductor device

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN *

Also Published As

Publication number Publication date
WO2002000004A2 (en) 2002-01-03
AU2001271166A1 (en) 2002-01-08

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