WO2002001643A2 - Soft recovery power diode and related method - Google Patents

Soft recovery power diode and related method Download PDF

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Publication number
WO2002001643A2
WO2002001643A2 PCT/US2001/019990 US0119990W WO0201643A2 WO 2002001643 A2 WO2002001643 A2 WO 2002001643A2 US 0119990 W US0119990 W US 0119990W WO 0201643 A2 WO0201643 A2 WO 0201643A2
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Prior art keywords
semiconductor layer
semiconductor
dopant concentration
diode
range
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PCT/US2001/019990
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French (fr)
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WO2002001643A3 (en
Inventor
Praveen Muraleedharan Shenoy
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Fairchild Semiconductor Corporation
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Priority to AU2001270086A priority Critical patent/AU2001270086A1/en
Priority to DE10196362T priority patent/DE10196362B4/en
Priority to JP2002505688A priority patent/JP4608181B2/en
Publication of WO2002001643A2 publication Critical patent/WO2002001643A2/en
Publication of WO2002001643A3 publication Critical patent/WO2002001643A3/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/36—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the concentration or distribution of impurities in the bulk material
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/548—Amorphous silicon PV cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/927—Different doping levels in different parts of PN junction to produce shaped depletion layer

Definitions

  • the present invention relates to the field of electronic devices , and, more particularly, to power diodes .
  • Diodes are used in a variety of circuits to either restrict or permit the flow of current within the circuit depending upon the voltage which is applied across the diode. That is, the voltage will either cause the diode to become forward-biased, at which point the current will flow through the diode, or reverse-biased, at which point current is restricted from flowing through the diode.
  • Diodes such as the P-i-N (positive-intrinsic- negative) diodes are widely used in high voltage applications, such as power factor correction circuits, for example.
  • the diode transitions suddenly from a forward-biased state to a reversed-biased state caused by a large voltage swing, the diode must undergo a period of reverse recovery.
  • the i region of the diode contains a large concentration of minority carriers. This concentration must be removed from the i region before the current flow can be limited to substantially zero.
  • a reverse recovery current (Irr) will increase in magnitude until the excess carrier concentration at the P-N junction has dropped below the background concentration at a time t (i.e., the time when the current reaches a negative peak) , at which point reverse recovery can begin.
  • the Irr may increase to the point at which the circuit is damaged.
  • the Irr results in an increase in the forward voltage drop (Vf) of the diode as well a decrease in the softness of the recovery waveform, both of which are undesirable.
  • the softness of the recovery waveform corresponds to the slope of the Irr (i.e., dlrr/dt) as it tends toward zero after the time t. The steeper the slope, the less “soft" the recovery waveform and the greater the chance that ringing will result. Ringing is caused when the current overshoots or oscillates back and forth about zero during the reverse recovery period because the current increases and decreases too guickly due to circuit parasitics.
  • a semiconductor diode including a more highly doped base layer between the intrinsic layer and the base.
  • the diode may comprise a first semiconductor layer that includes a dopant having a first conductivity type and a second semiconductor layer adjacent the first semiconductor layer that includes a dopant having the first conductivity type and having a dopant concentration less than a dopant concentration of the first semiconductor layer.
  • a third semiconductor layer maybe adjacent the second semiconductor layer and includes a dopant having the first conductivity type and having a dopant concentration greater than the dopant concentration of the second semiconductor ayer. This third layer may be considered as providing the more highly doped base layer or region.
  • a fourth semiconductor layer maybe adjacent the third semiconductor layer and include a dopant of a second conductivity type. Respective contacts are connected to the first and fourth semiconductor layers.
  • the diode has a reduced Irr compared to prior art diodes yet still provides a low Vf and soft recovery characteristics .
  • the semiconductor diode may further include an intermediate semiconductor layer between the first semiconductor layer and the second semiconductor layer.
  • the intermediate semiconductor layer has a dopant concentration between the dopant concentrations of the first and second semiconductor layers.
  • the fourth semiconductor layer may be surrounded by the third semiconductor layer.
  • the dopant concentrations and thicknesses of the semiconductor layers may be as follows: for the first semiconductor layer, a dopant concentration in a range of about 1 X 10 18 to 1 X 10 19 cm -3 and a thickness in a range of about 100 to 400 ⁇ m; for the intermediate semiconductor layer, a dopant concentration in a range of about 2.5 x 10 14 to 1.3 x 10 15 cm -3 and a thickness in a range of about 8 to 35 ⁇ m; for the second semiconductor layer, a dopant concentration in a range of about 6 x 10 13 to 6 x 14 14 cm -3 and a thickness in a range of about 7 to 70 ⁇ m; for the third semiconductor layer, a dopant concentration in a range of about 1 X 10 14 to 1 X 10 16 cm "3 and a thickness in a range of about 4 to 6 ⁇ m; and for the fourth semiconductor layer, a dopant concentration in a range of less than about 1 X 10 17 cm -3 and a thickness in a range of
  • the first conductivity type is preferably N type and the second conductivity type is preferably P type.
  • Another aspect of the invention relates to doping the fourth semiconductor region with relatively low concentrations compared to those found in prior art devices. Accordingly, the excess carrier concentration at the P-N junction between the third and fourth semiconductor layers is held to a lower level, thus resulting in a reduced Irr at the time t (hereafter "Irrm") . Increasing the doping concentration of the third semiconductor layer further reduces the carrier concentration at the P-N junction, providing for further reduction in the Irrm.
  • the dopant concentration of the fourth semiconductor layer preferably has a dopant concentration greater than the dopant concentration of the third semiconductor layer.
  • a method according to the invention is for making a semiconductor diode.
  • the method preferably includes providing a semiconductor substrate including a dopant having a first conductivity type.
  • a first epitaxial layer of the first conductivity type is grown adjacent the semiconductor substrate and may have a dopant concentration less than a dopant concentration of the first semiconductor layer.
  • the method may further include doping a first region of the first conductivity type in the first epitaxial layer to a dopant concentration less than the dopant concentration of the first epitaxial layer, and doping a second region of a second conductivity type in the first region. Additionally, respective contacts maybe formed on the semiconductor substrate and the second region.
  • FIG. 1 is a schematic cross-sectional view of a semiconductor diode according to the present invention.
  • FIG. 2 is a graph illustrating a doping profile of the semiconductor diode of FIG. 1.
  • FIG. 3 is a graph illustrating simulated test results of the recovery waveforms of a prior art diode and several embodiments of diodes according to the present invention.
  • FIG. 4 is a graph illustrating actual test results of the recovery waveforms of a prior art diode and a diode according to the present invention.
  • the diode 10 includes a first semiconductor layer or substrate 11 that illustratively includes an N-type dopant.
  • An intermediate semiconductor layer 13 (N-type) is formed between the first semiconductor layer 11 and a second semiconductor layer 14, which is also N-type.
  • the dopant concentration of the intermediate semiconductor layer 13 is less than that of first semiconductor layer 11, and the dopant concentration of the second semiconductor layer 14 is less than that of the intermediate semiconductor layer.
  • the intermediate and second semiconductor layers 13, 14 may be epitaxially grown on the substrate, for example, as will be readily appreciated by those skilled in the art.
  • a third semiconductor layer 15 is adjacent the second semiconductor layer 14 and includes an N- type dopant of a concentration greater than the second semiconductor layer. Adjacent the third semiconductor layer is a fourth semiconductor layer 16 which includes a P-type dopant. Both the third and fourth semiconductor layers 15, 16 may be doped by conventional diffusion or implantation techniques, for example, as will be readily appreciated by those of skill in the art. As shown in FIG. 1, the fourth semiconductor layer 16 may be surrounded by the third semiconductor layer 15.
  • a metal contact layer (or cathode) 17 is formed on the first semiconductor layer 11 and a metal contact layer (or anode) 18 is formed on the fourth semiconductor layer 16.
  • a shallow, lightly activated P+ surface implant may be included to provide better contact between the fourth semiconductor layer 16 and the anode 18. The implant layer is only lightly activated to keep the injection efficiency at the P-N junction low.
  • the dopant concentrations are chosen to cause an excess carrier concentration region to be formed away from the P-N junction during operation, which serves to maintain Vf at low values and produce a soft recovery waveform. That is, even though the maximum recovery value (i.e., the point at which dlrr/dt equals zero) is reduced because a lower carrier concentration is present at the P-N junction, the overall carrier concentration of the semiconductor diode 10 may be maintained due to the higher excess carrier concentration region away from the P-N junction, which allows Vf to remain low.
  • the maximum recovery value is lower, the time it takes the reverse recovery current to reach this point will decrease. Yet, since the carrier concentration across the entire semiconductor diode 10 remains substantially the same as in prior art diodes, the total time required for recovery will basically remain unchanged. Thus, the slope of the recovery curve after the maximum recovery value (i.e., after time t) will be less steep, resulting in increased softness.
  • the efficacy of the present invention has been demonstrated in both simulations and actual tests .
  • the first waveform 20 corresponds to a prior art Hyperfast diode made by the assignee of the present invention.
  • the second waveform 21 corresponds to a diode made according to the present invention having a third semiconductor layer 15 with an increased dopant concentration (as described in Table 2, above) and a conventionally doped fourth semiconductor layer 16.
  • the third waveform 22 corresponds to a diode made according to the present invention having a fourth semiconductor layer 16 with a decreased dopant concentration (again described in Table 2) and a conventionally doped third semiconductor layer 15.
  • the fourth waveform 23 corresponds to a diode made according to the present invention having both a third semiconductor layer 15 with an increased dopant concentration and a fourth semiconductor layer 16 with a decreased dopant concentration.
  • Each of the simulated diodes according to the present invention (i.e., waveforms 21, 22, 23) provide lower Irr values and increased softness.
  • the Irr of the diodes corresponding to waveforms 21, 22 were approximately 9 and 14% lower, respectively, than the Irr of the prior art diode corresponding to waveform 20.
  • the diode corresponding to waveform 23 provided an approximate 27% drop in Irr as well as an approximate 75% increase in softness with respect to the prior art diode. These values were obtained while maintaining Vf at about 1.8 ⁇ 0.05 volts for each of the diodes. Referring now to FIG.
  • the third layer or first region 15 is formed by doping an upper portion of the epitaxial layer 14, and the second region 16 may be formed by doping an upper portion of the first region.
  • the contacts 17, 18 are also preferably formed on the semiconductor substrate 11 and the second region 16, respectively, as will be readily appreciated by those skilled in the art.
  • the above layers are preferably formed having the dopant types and concentrations, thickness, etc. as set, forth above. It will also be appreciated by those skilled in the art that the present invention is not limited to any one type of diode. Rather, it may advantageously be used in all diodes including a P-N junction where a soft Irr waveform is desired, such as MOSFET body diodes, for example.

Abstract

A semiconductor diode includes a first semiconductor layer including a dopant having a first conductivity type. A second semiconductor layer is adjacent the first semiconductor layer and includes a dopant having the first conductivity type and having a dopant concentration less than a dopant concentration of the first semiconductor layer. Adjacent the second semiconductor layer is a third semiconductor layer including a dopant having the first conductivity type and having a dopant concentration greater than the dopant concentration of the second semiconductor layer. A fourth semiconductor layer is adjacent the third semiconductor layer and includes a dopant of a second conductivity type. Respective contacts are connected to the first and fourth semiconductor layers.

Description

SOFT RECOVERY POWER DIODE AND RELATED METHOD
Field of the Invention
The present invention relates to the field of electronic devices , and, more particularly, to power diodes . Background of the Invention
Diodes are used in a variety of circuits to either restrict or permit the flow of current within the circuit depending upon the voltage which is applied across the diode. That is, the voltage will either cause the diode to become forward-biased, at which point the current will flow through the diode, or reverse-biased, at which point current is restricted from flowing through the diode.
Diodes such as the P-i-N (positive-intrinsic- negative) diodes are widely used in high voltage applications, such as power factor correction circuits, for example. When such a diode transitions suddenly from a forward-biased state to a reversed-biased state caused by a large voltage swing, the diode must undergo a period of reverse recovery. During the forward- biased state the i region of the diode contains a large concentration of minority carriers. This concentration must be removed from the i region before the current flow can be limited to substantially zero. Accordingly, after being switched to a reverse-biased state a reverse recovery current (Irr) will increase in magnitude until the excess carrier concentration at the P-N junction has dropped below the background concentration at a time t (i.e., the time when the current reaches a negative peak) , at which point reverse recovery can begin.
If the minority carrier concentration becomes too large, it is possible that the Irr may increase to the point at which the circuit is damaged.
Accordingly, it is desirable to have a low Irr to avoid this disadvantage. Yet, reducing the Irr results in an increase in the forward voltage drop (Vf) of the diode as well a decrease in the softness of the recovery waveform, both of which are undesirable. The softness of the recovery waveform corresponds to the slope of the Irr (i.e., dlrr/dt) as it tends toward zero after the time t. The steeper the slope, the less "soft" the recovery waveform and the greater the chance that ringing will result. Ringing is caused when the current overshoots or oscillates back and forth about zero during the reverse recovery period because the current increases and decreases too guickly due to circuit parasitics. Accordingly, there is a need for a power diode that provides for a relatively low Irr value while maintaining a low Vf and soft recovery characteristics. Various attempts have been made in the prior art to create such diodes. One example is U.S. Patent No. 4,594,602 to Iimura et al. entitled "High Speed Diode." The diode has a PNN<+> structure which is intended to provide high speed switching characteristics along with a soft reverse recovery and low forward voltage drop. However, the structure of this diode may not provide an adequate balance of reduced Irr and increased softness in certain applications .
Summary of the Invention
In view of the foregoing background, it is therefore an object of the invention to provide a semiconductor diode having relatively low Irr and Vf values and further exhibiting soft recovery characteristics .
This and other objects, features, and advantages in accordance with the present invention are provided by a semiconductor diode including a more highly doped base layer between the intrinsic layer and the base. More particularly, the diode may comprise a first semiconductor layer that includes a dopant having a first conductivity type and a second semiconductor layer adjacent the first semiconductor layer that includes a dopant having the first conductivity type and having a dopant concentration less than a dopant concentration of the first semiconductor layer. Additionally, a third semiconductor layer maybe adjacent the second semiconductor layer and includes a dopant having the first conductivity type and having a dopant concentration greater than the dopant concentration of the second semiconductor ayer. This third layer may be considered as providing the more highly doped base layer or region. A fourth semiconductor layer maybe adjacent the third semiconductor layer and include a dopant of a second conductivity type. Respective contacts are connected to the first and fourth semiconductor layers. The diode has a reduced Irr compared to prior art diodes yet still provides a low Vf and soft recovery characteristics .
The semiconductor diode may further include an intermediate semiconductor layer between the first semiconductor layer and the second semiconductor layer. The intermediate semiconductor layer has a dopant concentration between the dopant concentrations of the first and second semiconductor layers. Additionally, the fourth semiconductor layer may be surrounded by the third semiconductor layer.
By way of example, the dopant concentrations and thicknesses of the semiconductor layers may be as follows: for the first semiconductor layer, a dopant concentration in a range of about 1 X 1018 to 1 X 1019 cm-3 and a thickness in a range of about 100 to 400 μm; for the intermediate semiconductor layer, a dopant concentration in a range of about 2.5 x 1014 to 1.3 x 1015 cm-3 and a thickness in a range of about 8 to 35 μm; for the second semiconductor layer, a dopant concentration in a range of about 6 x 1013 to 6 x 1414 cm-3 and a thickness in a range of about 7 to 70 μm; for the third semiconductor layer, a dopant concentration in a range of about 1 X 1014 to 1 X 1016 cm"3 and a thickness in a range of about 4 to 6 μm; and for the fourth semiconductor layer, a dopant concentration in a range of less than about 1 X 1017 cm-3 and a thickness in a range of about 2 to 4 μm.
In addition, the first conductivity type is preferably N type and the second conductivity type is preferably P type. Another aspect of the invention relates to doping the fourth semiconductor region with relatively low concentrations compared to those found in prior art devices. Accordingly, the excess carrier concentration at the P-N junction between the third and fourth semiconductor layers is held to a lower level, thus resulting in a reduced Irr at the time t (hereafter "Irrm") . Increasing the doping concentration of the third semiconductor layer further reduces the carrier concentration at the P-N junction, providing for further reduction in the Irrm. The dopant concentration of the fourth semiconductor layer preferably has a dopant concentration greater than the dopant concentration of the third semiconductor layer. Furthermore, the dopant concentration may be chosen to cause an excess carrier concentration region away from the P-N junction during operation to be higher than in prior art devices, which serves to maintain Vf at low values and produce a soft recovery waveform. A method according to the invention is for making a semiconductor diode. The method preferably includes providing a semiconductor substrate including a dopant having a first conductivity type. A first epitaxial layer of the first conductivity type is grown adjacent the semiconductor substrate and may have a dopant concentration less than a dopant concentration of the first semiconductor layer. The method may further include doping a first region of the first conductivity type in the first epitaxial layer to a dopant concentration less than the dopant concentration of the first epitaxial layer, and doping a second region of a second conductivity type in the first region. Additionally, respective contacts maybe formed on the semiconductor substrate and the second region. Brief Description of the Drawings
FIG. 1 is a schematic cross-sectional view of a semiconductor diode according to the present invention.
FIG. 2 is a graph illustrating a doping profile of the semiconductor diode of FIG. 1.
FIG. 3 is a graph illustrating simulated test results of the recovery waveforms of a prior art diode and several embodiments of diodes according to the present invention. FIG. 4 is a graph illustrating actual test results of the recovery waveforms of a prior art diode and a diode according to the present invention.
Detailed Description of the Preferred Embodiments The present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Like numbers refer to like elements throughout.
Referring now to FIG. 1, a diode 10 according to the invention is first described. The diode 10 includes a first semiconductor layer or substrate 11 that illustratively includes an N-type dopant. An intermediate semiconductor layer 13 (N-type) is formed between the first semiconductor layer 11 and a second semiconductor layer 14, which is also N-type. The dopant concentration of the intermediate semiconductor layer 13 is less than that of first semiconductor layer 11, and the dopant concentration of the second semiconductor layer 14 is less than that of the intermediate semiconductor layer. The intermediate and second semiconductor layers 13, 14 may be epitaxially grown on the substrate, for example, as will be readily appreciated by those skilled in the art.
A third semiconductor layer 15 is adjacent the second semiconductor layer 14 and includes an N- type dopant of a concentration greater than the second semiconductor layer. Adjacent the third semiconductor layer is a fourth semiconductor layer 16 which includes a P-type dopant. Both the third and fourth semiconductor layers 15, 16 may be doped by conventional diffusion or implantation techniques, for example, as will be readily appreciated by those of skill in the art. As shown in FIG. 1, the fourth semiconductor layer 16 may be surrounded by the third semiconductor layer 15. A metal contact layer (or cathode) 17 is formed on the first semiconductor layer 11 and a metal contact layer (or anode) 18 is formed on the fourth semiconductor layer 16. A shallow, lightly activated P+ surface implant may be included to provide better contact between the fourth semiconductor layer 16 and the anode 18. The implant layer is only lightly activated to keep the injection efficiency at the P-N junction low.
According to the present invention, the dopant concentrations of the above layers are chosen to minimize carrier concentration around the P-N junction between the third and fourth semiconductor layers 15, 16 to thereby lower Irrm. This can be achieved in two ways. First, the doping concentration of the third semiconductor layer 15 may be higher than the doping concentration of the second layer 14. Secondly, the doping concentration of the fourth semiconductor layer 16 may be decreased relative to prior art devices, providing the same effect. That is, by reducing the injection efficiency of the P type injector the excess carrier concentration at the P-N junction may be lowered. By doing both, an even greater reduction in Irrm levels may be obtained, as will be discussed further below.
As noted above, reducing Irrm normally leads to an increase in Vf and a loss of softness in the recovery waveform. To alleviate such results, the dopant concentrations are chosen to cause an excess carrier concentration region to be formed away from the P-N junction during operation, which serves to maintain Vf at low values and produce a soft recovery waveform. That is, even though the maximum recovery value (i.e., the point at which dlrr/dt equals zero) is reduced because a lower carrier concentration is present at the P-N junction, the overall carrier concentration of the semiconductor diode 10 may be maintained due to the higher excess carrier concentration region away from the P-N junction, which allows Vf to remain low. Also, since the maximum recovery value is lower, the time it takes the reverse recovery current to reach this point will decrease. Yet, since the carrier concentration across the entire semiconductor diode 10 remains substantially the same as in prior art diodes, the total time required for recovery will basically remain unchanged. Thus, the slope of the recovery curve after the maximum recovery value (i.e., after time t) will be less steep, resulting in increased softness.
Exemplary expected ranges for the thicknesses (in μm) and doping concentrations (in cm"3) of the above described layers for representative diodes of 300, 600, and 1200 volts are provided in Table 1 and Table 2, respectively, below. Those of skill in the art will appreciate that the above advantages may be implemented in a variety of diodes having a variety of operating voltages other than those provided in these tables. Layer numbers refer to the reference numeral given above for the respective layer. Table 1 - Thicknesses
Figure imgf000011_0001
Table 2 - Doping Concentrations
Figure imgf000011_0002
An exemplary dopant profile of the semiconductor diode 10 of FIG. 1 is shown in FIG. 2. The reference numbers again correspond to the above described layers. One noteworthy point illustrated by the profile is that the dopant concentration of the fourth semiconductor layer 16 is chosen to be greater than the dopant concentration of the third semiconductor layer 15. Additionally, the depth of the fourth semiconductor layer 16 is less than corresponding P-layers of prior art P-N diodes, which are typically about 8μm. Furthermore, the dopant concentration of the fourth semiconductor layer 16 is also less than that of prior art diodes, as will be appreciated by those of skill in the art. Accordingly, the total charge of the semiconductor layer 16 is reduced to thereby provide a lower injection efficiency at the P-N junction than in prior art diodes.
The efficacy of the present invention has been demonstrated in both simulations and actual tests . Turning now to FIG. 3, the simulated recovery waveforms of four different 600V diodes are illustrated. The first waveform 20 corresponds to a prior art Hyperfast diode made by the assignee of the present invention. The second waveform 21 corresponds to a diode made according to the present invention having a third semiconductor layer 15 with an increased dopant concentration (as described in Table 2, above) and a conventionally doped fourth semiconductor layer 16. The third waveform 22 corresponds to a diode made according to the present invention having a fourth semiconductor layer 16 with a decreased dopant concentration (again described in Table 2) and a conventionally doped third semiconductor layer 15. Finally, the fourth waveform 23 corresponds to a diode made according to the present invention having both a third semiconductor layer 15 with an increased dopant concentration and a fourth semiconductor layer 16 with a decreased dopant concentration.
Each of the simulated diodes according to the present invention (i.e., waveforms 21, 22, 23) provide lower Irr values and increased softness. Specifically, the Irr of the diodes corresponding to waveforms 21, 22 were approximately 9 and 14% lower, respectively, than the Irr of the prior art diode corresponding to waveform 20. Furthermore, the diode corresponding to waveform 23 provided an approximate 27% drop in Irr as well as an approximate 75% increase in softness with respect to the prior art diode. These values were obtained while maintaining Vf at about 1.8 ± 0.05 volts for each of the diodes. Referring now to FIG. 4, actual test results comparing the above prior art Hyperfast diode to a diode according to the invention having both a third semiconductor layer 15 with an increased dopant concentration and a fourth semiconductor layer 16 with a decreased dopant concentration are shown. The waveform 24 corresponds to the prior art diode and the waveform 25 corresponds to the diode of the present invention. Again, it can be seen that the Irr for the diode of the present invention is lower than that of the prior art diode (by approximately 26%) . Most notably, an increase in softness of approximately 130% was realized, resulting in substantially no ringing. Again, by selecting dopant concentrations sufficient to cause an excess carrier concentration region as described above, the Vf value of the diode according to the present invention was maintained substantially the same as that of the prior art diode.
As will be appreciated by those skilled in the art, the third and fourth semiconductor layer 15, 16 of the diode 10, can be formed as doped regions in the upper portion of the second semiconductor layer 14. This can be done by conventional implantation or other doping techniques as will be appreciated by those skilled in the art. Accordingly, the power semiconductor diode 10 with its advantageous features can be readily made using an additional selective doping step to form the third semiconductor layer 15 (first doped region) as will be readily appreciated by those skilled in the art. A method according to the invention is for making the semiconductor diode 10 and may include providing a doped semiconductor substrate 11 and growing epitaxial layers 13, 14 on the semiconductor substrate. The third layer or first region 15 is formed by doping an upper portion of the epitaxial layer 14, and the second region 16 may be formed by doping an upper portion of the first region. The contacts 17, 18 are also preferably formed on the semiconductor substrate 11 and the second region 16, respectively, as will be readily appreciated by those skilled in the art. The above layers are preferably formed having the dopant types and concentrations, thickness, etc. as set, forth above. It will also be appreciated by those skilled in the art that the present invention is not limited to any one type of diode. Rather, it may advantageously be used in all diodes including a P-N junction where a soft Irr waveform is desired, such as MOSFET body diodes, for example.
Many modifications and other embodiments of the invention will come to the mind of one skilled in the art having the benefit of the teachings presented in the foregoing descriptions and the associated drawings. Therefore, it is to be understood that the invention is not to be limited to the specific embodiments disclosed, and that other modifications and embodiments are intended to be included within the scope of the appended claims.

Claims

THAT WHICH IS CLAIMED IS:
1. A semiconductor diode comprising: a first semiconductor layer including a dopant having a first conductivity type; a second semiconductor layer adjacent said first semiconductor layer and including a dopant having the first conductivity type and having a dopant concentration less than a dopant concentration of said first semiconductor layer; a third semiconductor layer adjacent said second semiconductor layer and including a dopant having the first conductivity type and having a dopant concentration greater than the dopant concentration of said second semiconductor layer; a fourth semiconductor layer adjacent said third semiconductor layer and including a dopant of a second conductivity type; and respective contacts connected to said first and fourth semiconductor layers.
2. The semiconductor diode of Claim 1 wherein said fourth semiconductor layer has a dopant concentration greater than the dopant concentration of said third semiconductor layer.
3. The semiconductor diode of Claim 1 wherein said third semiconductor layer has a thickness in a range of about 4 to 6 μm.
4. The semiconductor diode of Claim 1 wherein the dopant concentration of said third semiconductor layer is in a range of about 1 x 10" to 1 x 1016 cm"3.
5. The semiconductor diode of Claim 1 wherein said fourth semiconductor layer has a thickness of about 2 to 4 μm.
6. The semiconductor diode of Claim 1 wherein said fourth semiconductor layer has a dopant concentration in a range of less than about 1 x 1017 cm"3.
7. The semiconductor diode of Claim 1 wherein said fourth semiconductor layer is surrounded by said third semiconductor layer.
8. The semiconductor diode of Claim 1 wherein said first semiconductor layer has a thickness in a range of about 100 to 400 μm.
9. The semiconductor diode of Claim 1 wherein the dopant concentration of said first semiconductor layer is in a range of about 1 x 1018 to 1 x 1019 cm"3.
10. The semiconductor diode of Claim 1 wherein said second semiconductor layer has a thickness in a range of about 7 to 70 μm.
11. The semiconductor diode of Claim 1 wherein the dopant concentration of said second semiconductor layer is in a range of about 6 x 1013 to 6 x 10" cm"3.
12. The semiconductor diode of Claim 1 further comprising an intermediate semiconductor layer between said first semiconductor layer and said second semiconductor layer including a dopant having the first conductivity type and having a dopant concentration between the dopant concentration of said first semiconductor layer and the dopant concentration of said second semiconductor layer.
13. The semiconductor diode of Claim 12 wherein said intermediate semiconductor layer has a thickness in a range of about 8 to 35 μm.
14. The semiconductor diode of Claim 12 wherein the dopant concentration of said intermediate semiconductor layer is in a range of about 2.5 x 10" to 1.3 x 1015 cm"3.
15. The semiconductor diode of Claim 1 wherein the first conductivity type is N type and the second conductivity type is P type.
16. A semiconductor diode comprising: a first semiconductor layer including a dopant having a first conductivity type; a second semiconductor layer adjacent said first semiconductor layer and including a dopant having the first conductivity type and having a dopant concentration less than a dopant concentration of said first semiconductor layer; a first doped region in said second semiconductor layer having the first conductivity type and having a dopant concentration greater than the dopant concentration of said second semiconductor layer; a second doped region in said first doped region having a second conductivity type; and respective contacts connected to said first semiconductor layer and said second doped region.
17. The semiconductor diode of Claim 16 wherein said second doped region has a dopant concentration greater than the dopant concentration of said first doped region.
18. The semiconductor diode of Claim 16 wherein said first doped region has a thickness in a range of about 4 to 6 μm.
19. The semiconductor diode of Claim 16 wherein the dopant concentration of said first doped region is in a range of about 1 x 10" to 1 x 1016 cm"3.
20. The semiconductor diode of Claim 16 wherein said second doped region has a thickness of about 2 to 4 μm.
21. The semiconductor diode of Claim 16 wherein said second doped region has a dopant concentration in a range of less than about 1 x 1017 cm"3.
22. The semiconductor diode of Claim 16 wherein said second doped region is surrounded by said first doped region.
23. The semiconductor diode of Claim 16 wherein said first semiconductor layer has a thickness in a range of about 100 to 400 μm.
24. The semiconductor diode of Claim 16 wherein the dopant concentration of said first semiconductor layer is in a range of about 1 x 1018 to 1 x 1019 cm"3.
25. The semiconductor diode of Claim 16 wherein said second semiconductor layer has a thickness in a range of about 7 to 70 μm.
26. The semiconductor diode of Claim 16 wherein the dopant concentration of said second semiconductor layer is in a range of about 6 x 1013 to 6 x 10" cm"3.
27. The semiconductor diode of Claim 16 further comprising an intermediate semiconductor layer between said first semiconductor layer and said second semiconductor layer including a dopant having the first conductivity type and having a dopant concentration between the dopant concentration of said first semiconductor layer and the dopant concentration of said second semiconductor layer.
28. The semiconductor diode of Claim 27 wherein said intermediate semiconductor layer has a thickness in a range of about 8 to 35 μm.
29. The semiconductor diode of Claim 27 wherein the dopant concentration of said intermediate semiconductor layer is in a range of about 2.5 x 10" to 1.3 x 1015 cm"3.
30. The semiconductor diode of Claim 16 wherein the first conductivity type is N type and the second conductivity type is P type.
31. A semiconductor diode comprising: a first semiconductor layer including a dopant having a first conductivity type; a second semiconductor layer adjacent said first semiconductor layer and including a dopant having the first conductivity type and having a dopant concentration less than a dopant concentration of said first semiconductor layer; a first doped region in said second semiconductor layer having the first conductivity type and having a dopant concentration greater than the dopant concentration of said second semiconductor layer; a second doped region in said first doped region having a second conductivity type and having a dopant concentration greater than the dopant concentration of said first doped region; and respective contacts connected to said first semiconductor layer and said second doped region.
32. The semiconductor diode of Claim 31 wherein said first doped region has a thickness in a range of about 4 to 6 μm.
33. The semiconductor diode of Claim 31 wherein the dopant concentration of said first doped region is in a range of about 1 x 10" to 1 x 1016 cm"3.
34. The semiconductor diode of Claim 31 wherein said second doped region has a thickness of about 2 to 4 μm.
35. The semiconductor diode of Claim 31 wherein said second doped region has a dopant concentration in a range of about to 1 x 1017 cm"3.
36. The semiconductor diode of Claim 31 wherein said second doped region is surrounded by said first doped region.
37. The semiconductor diode of Claim 31 wherein said first semiconductor layer has a thickness in a range of about 100 to 400 μm.
38. The semiconductor diode of Claim 31 wherein the dopant concentration of said first semiconductor layer is in a range of about 1 X 1018 to 1 x 1019 cm"3.
39. The semiconductor diode of Claim 31 wherein said second semiconductor layer has a thickness in a range of about 7 to 70 μm.
40. The semiconductor diode of Claim 31 wherein the dopant concentration of said second semiconductor layer is in a range of about 6 x 1013 to 6 x 10" cm"3.
41. The semiconductor diode of Claim 31 further comprising an intermediate semiconductor layer between said first semiconductor layer and said second semiconductor layer including a dopant having the first conductivity type and having a dopant concentration between the dopant concentration of said first semiconductor layer and the dopant concentration of said second semiconductor layer.
42. The semiconductor diode of Claim 41 wherein said intermediate semiconductor layer has a thickness in a range of about 8 to 35 μm.
43. The semiconductor diode of Claim 41 wherein the dopant concentration of said intermediate semiconductor layer is in a range of about 2.5 x 10" to 1.3 x 10" cm"3.
44. The semiconductor diode of Claim 31 wherein the first conductivity type is N type and the second conductivity type is P type.
45. A method for making a semiconductor diode comprising: providing a semiconductor substrate including a dopant having a first conductivity type; growing a first epitaxial layer of the first conductivity type adjacent the semiconductor substrate and having a dopant concentration less than a dopant concentration of the semiconductor substrate; doping a first region of the first conductivity type in the first epitaxial layer to a dopant concentration greater than the dopant concentration of the first epitaxial layer; doping a second region of a second conductivity type in the first region; and forming respective contacts on the semiconductor substrate and the second region.
46. The method of Claim 45 wherein doping the second region comprises doping the second region to a greater dopant concentration than the dopant concentration of the first region.
47. The method of Claim 45 wherein doping the first region comprises doping the first region to a depth in a range of about 4 to 6 μm.
48. The method of Claim 45 doping the first region comprises doping the first region to a dopant concentration in a range of about 1 x 10" to 1 x 1016 cm"3.
49. The method of Claim 45 wherein doping the second region comprises doping the second region to a depth in a range of about 2 to 4 μm.
50. The method of Claim 45 wherein doping the second region comprises doping the second region to a dopant concentration in a range of less than about 1 x 1017 cm"3.
51. The method of Claim 45 further comprising growing a second epitaxial layer of the first conductivity type between the semiconductor substrate and the first epitaxial layer and having a dopant concentration between the dopant concentration of the semiconductor substrate and the dopant concentration of the first epitaxial layer.
52. The method of Claim 45 wherein the first conductivity type is N type and the second conductivity type is P type.
PCT/US2001/019990 2000-06-26 2001-06-22 Soft recovery power diode and related method WO2002001643A2 (en)

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DE10196362T1 (en) 2003-05-22
WO2002001643A3 (en) 2002-04-18
CN1441968A (en) 2003-09-10
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DE10196362B4 (en) 2007-04-05
US6737731B1 (en) 2004-05-18
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JP4608181B2 (en) 2011-01-05
TW507384B (en) 2002-10-21

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