WO2002013276A1

WO2002013276A1 - A memory device and a memory array

Info

Publication number: WO2002013276A1
Application number: PCT/GB2000/003416
Authority: WO
Inventors: Daniel Loss
Original assignee: Gentech Investment Group Ag
Priority date: 2000-08-09
Filing date: 2000-09-06
Publication date: 2002-02-14
Also published as: JP2004523097A; AU2000270219A1; EP1328979A1; GB0019618D0

Abstract

A memory has at least one memory device (1) having an input region (3) for carrying a current, an output region (4) for carrying a current, and a three-dimensionally confined quantum region (2a) arranged to operate in the coulomb blockade regime and separating the input and output regions (3 and 4) whereby charge carriers can only pass from the input region to the output region by tunnelling through the quantum region (4). A magnetic field (Bdc) is used to control Zeeman splitting in the memory device such that the input and output regions (3 and 4) are spin polarised whereby conduction through the input and output regions is by charge carriers of one spin polarity. In one arrangement, a pulsed AC magnetic field (Bac) is used to control the spin polarisation of an uppermost charge carrier in the quantum region to control the tunnelling current through the memory device. In another arrangement the polarisation of the magnetic field applied to the output region is used to switch the memory device between a conducting and a non-conducting state so that the memory device acts as a current switch.

Description

A MEMORY DEVICE AND A MEMORY ARRAY

This invention relates to a memory device and a memory array.

The demands of the computer industry and information technology in general require larger and larger memories operating at ever higher speeds. However, conventional memory such as dynamic random access memory (DRAM) that uses conventional semiconductor FET structures and capacitors for storing information as charge is reaching its operational size limit. Thus, although current x-ray, electronic beam and like lithography techniques would enable further shrinkage of memory size dimensions, this is not permitted because of restrictions on the capacitor and FET size.

There is increasing interest in the use of electron spin rather than charge for data manipulation and storage. An increasing number of experiments have shown that electron spin provides new ways of information processing and storage as discussed in, for example, the review article entitled "Magnetoelectronics" by Gary Prinz in Science Volume 282 pages 1660 to 1663 on 27 November 1998 and in the article entitled "Electron spin and Optical coherence in Semiconductors" by David Awschalom and James Kikkawa in the June 1999 edition of Physics Today at pages 33 to 38 and, for example, the letter to Nature by the same authors published in volume 397 of Nature at pages 139 to 141. There is also considerable interest in spin-related phenomena for conventional as well as quantum computing as described in the article published in Physical Review A Volume 57 No. 1 at pages 120 to 126 by Daniel Loss and David DiVincenzo. Interest in spin-based information processing has also been considerably increased by recent experimental results in which spin coherence over macroscopic distances (typically one hundred micrometers) and spin dephasing times of 100' s of nanoseconds have been observed.

Various proposals have been made for spin-memory devices that offer advances in packing density, speed and/or other properties over conventional charge-based memory devices. For example, US-A-6021065 describes a memory device that consists of anisotropic ferromagnetic thin film memory structures providing a spin-dependent tunnelling memory. In addition US-A-5801984 proposes the use of a magnetic tunnel junction device as a memory cell and US-A-5654566 describes spin-based logic devices. All of these devices are multi-electron devices. Single electron devices including quantum dot devices and single electron transistors have, however, been proposed and EP- A-0697737 describes quantum dot computing elements that operate using the spin states of two single electrons on neighbouring quantum dots coupled by an anti- ferromagnetic material . It is an aim of the present invention to provide a memory device that operates at the single spin level and enables, for example, effective read-in and read-out data from the memory device .

An aspect of the present invention provides a spin detector comprising a three-dimensionally quantum confined region arranged to operate in the Coulomb blockage regime coupled by tunnel barriers to input and output Fermi leads having g-factors considerably larger than the quantum confined region whereby application of a magnetic field causes Zeeman splitting in the quantum confined region and the Fermi leads with the Zeeman splitting in the leads being considerably greater than that in the quantum confined region, whereby a current applied to the input lead is spin-polarised and conduction through the quantum confined region occurs primarily by sequential tunnelling of an electron having the same spin polarisation as the leads. The spin polarisation of an electron in the quantum confined region may be controlled by electron spin resonance techniques using AC magnetic field pulses so as to induce a Rabi spin-flop which spin-flop exists for sufficiently long time to enable the spin state to be used to store data so that one of spin up and spin down represents "0" and the other represents "1". The spin state of the memory device may be determined by detecting the current through the quantum confined region which will be considerably higher when the spin state of the quantum confined region coincides with that of the spin polarised Fermi leads .

A two-dimensional or even three-dimensional array of such memory devices may be produced to provide a dynamic random access memory device. A non-volatile memory device may be provided by arranging a hard magnetic layer, magnetic nano-particle, magnetic impurity or layer of nuclear spins providing an Overhauser field in close proximity to the quantum confined region.

In another aspect, the present invention provides a switch having a three-dimensionally quantum confined region coupled by tunnel barriers to input and output Fermi leads such that the quantum confined region is arranged to operate in the Coulomb blockage regime and the g-factors of the Fermi leads are considerably higher than that of the quantum confined region such that when, in use, Zeeman splitting is induced, the Zeeman splitting in the Fermi leads is considerably greater than in the quantum confined region and spin polarisation occurs in the input and output leads , and having means for controlling the direction of spin polarisation of the input and output leads whereby, when the polarisations of the input and output leads are the same, conduction can occur by sequential tunnelling of an electron through the quantum confined region whereas when the spin polarisations of the input and output leads are opposite, conduction is inhibited. Embodiments of the present invention will now be described, by way of example, with reference to the accompanying drawings in which:-

Figure 1 shows a very diagrammatic functional diagram of a memory embodying the invention;

Figure 2 shows a side view of the memory shown in Figure 1 ;

Figure 3 shows a very diagrammatic cross-sectional view through one example of a memory device suitable for use in the memory shown in Figure 1 and Figure 2.

Figure 4 shows a representational diagram for illustrating the operation of a memory device embodying the invention;

Figures 5 to 8 show conduction band energy level diagrams for explaining the principle of operation of a memory device embodying the present invention;

Figures 9a and 9b show respective conduction band energy level diagrams for illustrating the effect on a memory device embodying the invention of an AC magnetic field inducing electron spin resonance;

Figure 10 shows a graph of current (I) against time (t) for illustrating the change in current resulting from the application of an alternating magnetic field inducing electron spin resonance to a memory device embodying the present invention.

Figure 11 shows a functional block diagram illustrating one example of a two-dimensional memory array embodying the present invention;

Figure 12 shows a simplified top plan view of part of the memory array shown in Figure 11 to illustrate a possible layout;

Figure 13 shows cross-sectional view similar to Figure 3 illustrating another example of a memory device embodying the invention;

Figure 14 shows a functional diagram of a two-dimensional memory array using the memory device shown in Figure 13;

Figure 15 shows a cross-sectional view similar to Figure 13 for illustrating a modification of the memory device shown in Figure 13;

Figure 16 shows a functional diagram of another example of a two-dimensional memory array embodying the invention; and Figures 17 and 18 show conduction band energy level diagrams for illustrating operation of a current switch embodying the present invention.

Referring now to Figures 1 and 2, there is shown a simplified diagram for illustrating functional elements of a memory device 1 embodying the invention.

The memory device 1 comprises a three-dimensionally quantum confined region in the form of a quantum dot in a quantum dot region 2 coupled by tunnel barriers TBl and TB2 to respective input and output Fermi leads 3 and 4 formed by highly doped semiconductor regions.

The quantum dot is configured to operate in the Coulomb blockade regime which is discussed in detail in, for example, section 2.1 at pages 114 to 118 of the chapter entitled "Electron transport in quantum dots" by Kouwenhoven et al in the review text book entitled "Mesoscopic Electron Transport" edited by Sohn, Kouwenhoven, and Schόn (ISBN No. 0-7923-4737-4).

The quantum dot region 2 and Fermi leads 3 and 4 are formed of materials such that the Fermi leads 3 and 4 have a g-factor considerably greater than that of the quantum dot region 2.

A DC magnetic field generator (Figure 2 ) 5 is provided for inducing Zeeman splitting in the quantum dot and Fermi leads 3 and 4 and an AC magnetic field generator 6 is provided for generating an AC magnetic field perpendicular to the DC magnetic field.

The input and output Fermi leads 3 and 4 are coupled to respective contacts Ll and L2 between which a voltage source VS is coupled. An annular gate G contacts the quantum dot region 2 and is coupled to a gate voltage source GV.

A current sensor CS is coupled to contact L2 to sense the current through the device 1.

The device 1 may be manufactured using conventional quantum dot manufacturing techniques such as, for example MBE (molecular beam epitaxy) or MOCVD (metal organic chemical vapour deposition) and lithographic techniques such as x-ray or electron beam lithography. The DC magnetic field generator 5 is required to generate a homogenous DC magnetic field of the order of at most a few Tesla. The DC magnetic field generator 5 may, therefore, consist of a commercially available nanomagnet. As other possibilities, the DC magnetic field generator 5 may be provided in a manner similar to that used for IBM magnetic storage discs or dysprosium dots may be used. Where nanomagnets or dysprosium dots are used, then these may be integrated with the device 1. As another possibility, a superconducting magnet may be used as the DC magnetic field generator 5. The AC magnetic field generator 6 is a standard AC magnetic field generator used for electron spin resonance techniques that is capable of generating an AC magnetic field pulse. Dependent upon the g-factor of the Fermi leads 3 and 4 , the magnetic fields required may be provided by, for example, permanent magnets or even electrically driven solenoids.

As mentioned above, the device 1 may be manufactured using standard quantum dot fabrication techniques.

Figure 3 shows a very diagrammatic cross-sectional view through part of a semiconductor body 10 to illustrate one example of a structure that may be used for the device.

In this example, the semiconductor body 10 comprises a substrate 11 generally an intrinsic (that is not intentionally doped) Gallium Arsenide (GaAs) substrate 11 on to which may be grown, as is well known in the MBE and

MOCVD art, a Gallium Arsenide | Aluminium Gallium Arsenide

Superlattice structure SL to provide a clean relatively defect free surface S.

Alternate layers of a magnetic II-VI, a non-magnetic III-V and a magnetic II-VI material are then grown on the surface S using standard MOCVD or MBE techniques. These layers are then patterned using standard vertical quantum dot defining lithographic techniques to define a column C providing first and second n conductivity type II-VI regions defining the Fermi leads 3 and 4 separated by a III-V region defining the quantum dot region 2. As can be seen from Figure 3, the etching process does not continue all the way through the bottom II-VI layer, rather a portion 3a of the bottom II-VI layer remains.

A chromium layer 12 is deposited to enable ohmic contact to the Fermi lead 3 followed by an insulating material (generally silicon dioxide) layer 13 followed by a further metallic (generally chromium) layer 14 and a further insulating layer 15. Vias VI and V2 are etched through these layers in known manner and metallisation (again generally chromium) deposited to define the first contact Ll contacting the chromium layer 12, the gate G contacting the chromium layer 14 and the contact L2 contacting the Fermi lead 4.

In this example, the II-VI material is an n conductivity type Beryllium Manganese Zinc Selenide alloy (Be_xMn_yZni-._x._ySe) having a composition such that the II-VI material is lattice-matched to the III-V material forming the quantum dot region 2 which is, in this example, n conductivity type Gallium Arsenide (GaAs). Typically the II-VI alloy may have the composition Be₀.₀₇Mn_o._o3Zn₀.₉Se.

A Beryllium Manganese Zinc Selenide alloy is selected to form the Fermi leads or regions 3 and 4 because, as described in a Letter to Nature published in Nature Volume 402, 16 December 1999 at pages 787 to 789 by Fiederling et al , this material has been shown to provide efficient transport of a spin polarised current and, moreover, efficient injection of that spin polarised current into a non-magnetic semiconductor material such as Gallium Arsenide.

Using standard lithographic techniques, the column C may have a circular cross section with a diameter of about 0.5 micrometers which, as will be understood by the person skilled in the art, is not sufficiently small to define a quantum dot within the quantum dot region 2. However, as well known by person skilled in the art, confinement in the lateral direction in Figure 3 may be achieved by applying a voltage to the gate G to define within the quantum dot region 2 a quantum dot having a diameter of about 50 nanometers.

The quantum dot is required to operate in the quantum Coulomb blockade regime which requires that:

K_BT « ΔE, e²/C (1) where K_B is Boltzmann's constant,

T is temperature,

ΔE is the difference between energy levels in a quantum dot, e is the electron charge, C is the capacitance of the quantum dot, and the " , " means that the inequality is satisfied for both components on the right hand side, that is:

K_BT « ΔE and K_BT « e²/C so that tunnelling of an electron onto the quantum dot is only possible when the additional energy e²/C is applied by, for example, means of a voltage applied to the gate G. For the materials and quantum dot dimensions given above, then the quantised level spacing and Coulomb charging energy will be of the order of 1 meV (milli electron volt) so that, in this example, the device should be operated at liquid Helium temperatures (a few Kelvin) using conventional low temperature generation techniques. It will, however, be appreciated by those skilled in the art that scaling down the size of the quantum dot by a factor of 10 will raise the necessary temperature by a factor of 100 thus allowing operation at room temperature.

The principle of operation of the device 1 shown in Figures 1 to 3 will now be described with reference to Figures 4 to 8 in which Figure 4 shows a schematic representation of the device 1 when a voltage has been applied to the annular gate G to provide the necessary further confinement to define a quantum dot 2a within the quantum dot region. Figure 4 also shows the relative orientation of the DC magnetic field B_dc (into the plane of the paper in Figure 4 ) and AC magnetic field B_ac when applied by the DC magnetic field generator 5 and AC magnetic field generator 6, respectively.

Figure 5 shows a conduction band energy level diagram for the device 1 when B_dc=0 and B_ac=0. In Figure 5, u_λ and μ₂ represent the chemical potentials of the Fermi leads 3 and 4 which, in the Coulomb blockade regime with one electron in the uppermost ground state of the quantum dot 2a, is related to the voltage V₁₂ applied between the contacts Ll and L2 as follows:

Vι,₂ = ( μι-μ₂ ) /e (2)

Figure 5 shows for the purpose of illustration the one electron 20 in the uppermost ground state of the quantum dot 2a as having spin state up.

The effect of applying a DC magnetic field B_dc to the device 1 will now be explained with reference to the conduction band diagrams shown in Figures 6a and 6b.

Applying a DC magnetic field B_dc>0 in the direction shown in Figure 4 causes, as is well known in the art, lifting of the spin degeneracy of the energy levels and Zeeman splitting between the spin state up and spin state down levels where the Zeeman splitting Δ_z is given by:

Δ_z=μ_B I gB I ( 3 )

where g is the g-factor of the material, μ_B is the Bohr magneton and B is the applied DC magnetic field.

Figure 6a shows the case where the uppermost electron 20 in the quantum dot has a spin state up whilst Figure 6b shows the case where the uppermost electron 20a has a spin state down. As can be seen from these figures the direction of the DC magnetic field B_dc is such that the electron 20 in spin state up has a lower energy than the electron 20a in spin state down. It will, of course, be appreciated that both the singlet E_s and triplet energy levels are split. However, for the sake of convenience, only the lower level E_τ+ triplet state is shown in Figures 6a and 6b. In addition, the energy of the ground state lower energy level is arbitrarily set to zero for convenience .

As mentioned above, the Fermi leads 3 and 4 have a much higher g-factor than the quantum dot region 2. In the example given above, the Gallium Arsenide quantum dot has a g-factor of -0.44 while the Beryllium Manganese Zinc Selenide alloy Fermi leads 3 and 4 have a g-factor in the region of 100. Accordingly, the Zeeman splitting in the Fermi leads 3 and 4 resulting from the application of the magnetic field B_dc is very much greater than that in the quantum dot 2 to the extent that any electron current in the Fermi leads 3 and 4 is spin polarised with, for the orientation of the magnetic fields B_dc shown in Figure 4, spin state up.

Figures 7a and 7b show conduction band energy level diagrams corresponding to Figures 6a and 6b when B_dc>0 and a spin polarised current having electron spin state up is flowing in the Fermi lead 3 as illustrated by the electron 21 in Figures 7a and 7b.

In order for a current to flow through the device 1, an electron must tunnel from the Fermi leads 3 onto the quantum dot 2a and an electron must tunnel off the quantum dot 2a onto the Fermi lead 4. Because the quantum dot 2 is in the Coulomb blockade regime, the charge on the dot is, as illustrated by Figures 5 to 8, quantised in units of electron charge. Also, because the tunnelling coupling is weak, tunnelling between the Fermi leads 3 and 4 and the quantum dot 2a can be described as a perturbation enabling the standard master equation approach to be used to calculate the current in the stationery limit.

Evaluation of tunnelling rates shows that two regimes of transport can naturally be distinguished, namely a sequential tunnelling regime where the number of electrons N on the quantum dot 2a fluctuates between N and N±l and is a first order transition which must obey energy conservation and a cotunnelling regime which is of higher order and thus provides a much smaller contribution to the current and in which an electron effectively tunnels directly from one Fermi lead 3 to the other Fermi lead 4 via a virtual state on the quantum dot 2a with the only allowed processes being second order transitions with the initial and final electron number on the quantum dot 2a being the same, namely N. In order for the device to be in the sequential tunnelling regime, the chemical potential μ_λ of the input Fermi lead 3 must be comparable to or greater than the energy of the next unoccupied level of the quantum dot 2a while the chemical potential μ₂ of the output Fermi lead 4 should be less than or comparable to the energy of that level namely:

μ_x > Es ≥ μ₂ (4)

Figures 7a and 7b show conduction band level diagrams when B_dc>0 and where the chemical potential μ_x of the input Fermi lead 3 is comparable to the energy E_s of the first unoccupied singlet state on the quantum dot 2a and the chemical potential μ₂ of the output Fermi lead 4 is comparable to or slightly less than the energy level E_s. However, Figure 7a shows the quantum dot as having as its uppermost electron an electron 20 having spin state up while Figure 7b shows the quantum dot 2a as having as its uppermost electron an electron 20a having spin state down which, by virtue of the Zeeman splitting, is at an energy Δ_z higher than the energy of the electron 20 shown in Figure 7a.

As mentioned above, the very large Zeeman splitting in the Fermi leads 3 and 4 resulting from the applied DC magnetic field B_dc results in a spin polarised current in the input Fermi lead 3 with, in this case, an electron 21 carried by the Fermi lead 3 having spin state up. Where the uppermost electron on the quantum dot is a spin state up electron 20 as shown in Figure 7a, then where:

E_τ+ - E_s, Δ_z > Δμ, K_BT where Δμ = | μ_x _ μ₂1 (5)

where the " , " again means that the inequality is satisfied for both components on each side of the inequality, that is:

E_τ+-E_s > Δμ , E_τ+-E_s > K_BT, Δ_z > Δμ and Δ_z > K_BT

as in the present case, then only . ground state transitions are allowed by energy conservation. Therefore, in the situation shown in Figure 7a, because the ground state of the quantum dot 2a already contains an electron 20 with spin state up, the electron 21 cannot tunnel into the ground state and accordingly the only possibility is for that electron to tunnel into an excited triplet state. This is, however, forbidden by energy conservation.

In contrast, where the uppermost ground state electron is, as shown in Figure 7b, an electron 20a with spin state down, then a spin state up electron 21 with an energy equal to the additional Coulomb charging energy e²/C can, as shown in Figure 7b, tunnel onto the dot 2a, thus obeying Fermi's Golden rule. As shown in Figure 7b, this tunnelling of the electron 21 onto the dot ensures that the energy level of the two electrons 21 and 21a is raised to the energy level E_s .

Thus, the only possible process for tunnelling of an electron in a spin-up state onto the dots in the sequential tunnelling regime is if the uppermost electron on the dot is in the spin down state. Therefore, in the Coulomb blockade regime the quantum dot 2a blocks tunnelling of spin-up state electrons 21 from the Fermi lead 3 when the uppermost electron on the quantum dot is a spin up state electron. This process is fundamentally different to previously introduced spin blockade effects such as described by the Wiedmann et al in Physics review letters volume 74, 1995 at page 984 because they occur for non-spin polarised currents and vanish with increasing magnetic fields, in contrast to the effect being discussed here.

Once a spin up state electron 21 has tunnelled onto the quantum dot 2a as shown in Figure 7b, then, as shown in Figure 8, the spin up state electron 21 can tunnel from the quantum dot 2a onto the lower chemical potential μ₂ output Fermi lead 4 with the spin down electron 20a returning to its previous energy level. Tunnelling of the spin down electron 20a from the quantum dot 20 onto the output Fermi lead 4 is prohibited because of the large Zeeman splitting in the output lead 4. Above or below a sequential tunnelling resonance, that is when E_s is greater than the chemical potentials of the input and output Fermi leads 3 and 4 or is less than the chemical potentials of the input and output Fermi leads 3 and 4, the device 1 is in the cotunnelling regime where, as explained above, tunnelling can only occur directly from one lead to the other via a virtual state on the quantum dot. Where Δμ and K_BTT are smaller than the energy level spacing on the quantum dot 2a (which is readily achieveable in the Coulomb blockade regime), then elastic cotunnelling may occur. In this regime, the main contribution to transport through a quantum dot 2a is where the relative energy of the virtual state is minimal. Thus, for example, if the quantum dot 2a is initially in its down state with the uppermost electron in a spin up state (as shown in Figure 7a), then an incoming spin up electron 21 can only form a virtual triplet state with virtual energy E_τ+-μ (where μ = (μ₁+μ₂)/2) before it leaves the dot 2a and tunnels into the output Fermi lead 4. As this is a higher order transition, the magnitude of the co-tunnelling current is much smaller than that of the sequential tunnelling current .

Figures 9a and 9b are conduction band diagrams for the device 1 showing the effect of applying an electron spin resonance AC pulse B_ac to the device 1 in the presence of and perpendicular to the DC magnetic field B_dc. Figure 9a shows the quantum dot 2a as having an odd number of electrons N with the uppermost electron 20 being a spin state up electron. In this case, sequential tunnelling of a spin state up electron 21 onto the quantum dot 2a is prohibited because tunnelling into the excited triplet state level E_τ+ at higher levels is prevented by energy conservation and tunnelling into the singlet state energy level E_s is blocked by spin conservation because the Fermi leads 3 and 4 can only provide and accept electrons with spin up. As explained above, there may, however, be a cotunnelling current I_c but because this is of higher order, the cotunnelling current I_c is much smaller than the sequential tunnelling current would be if the uppermost electron on the quantum dot was in the spin down state. As is well known in the art and as explained in the text book "Mesoscopic Electron Transport" mentioned above, the ratio between sequential and co-tunnelling currents can be as much as 20 to 100:1.

Application of an AC pulse B_ac perpendicular to the DC field B_dc at a frequency ω with an energy equal to dhe Zeeman splitting ΔZ within the quantum dot 2a in accordance with electron spin resonance technique results in a Rabi spin flop whereby the spin state of the ground state electron 20 changes from the spin up state shown in Figure 9a to the higher energy spin down state 20' shown in Figure 9b. Once the ground state electron is in the spin down state shown in Figure 9b, then as will be understood from the above description with reference to Figures 7a, 7b and 8, sequential tunnelling of a spin up state electron 21 from the input Fermi lead 3 onto the quantum dot 2a can occur, enabling a sequential tunnelling current I_s (which may be orders of magnitude higher than the leakage or cotunnelling current Is) to flow through the quantum dot 2a. A discussion of such spin flipping can be found in a paper by Burkard et al in Physics Review B, volume 59 at page 2070, 1999.

Figure 10 shows a graph of current I (measured by the current sensor CS shown in Figures 1 and 2) against time (t) for the case where the AC pulse B_ac is applied prior to time t₀ and at t_Bac. As can be seen from Figure 10, a sequential tunnelling current I_s is detected for a period (τ_s) equal to the spin relaxation time that is the time taken for the spin flipped electron 20" to return to its original spin state. When, at time τ_s the electron returns to its original spin up state, then as shown in Figure 10, the only current I_c through the device is a small leakage current resulting from a cotunnelling process. When a subsequent AC pulse B_ac is applied at time t_Bac, then the current returns to the magnitude of the sequential tunnelling current I_Ξ. As reported by Awschalom et al in Nature, volume 397 at page 139 (1999), the spin relaxation time should exceed 100s of nanoseconds. The time scale for read in and read out of data can be estimated to be in the GigaHertz (GHz) range. Although typical refresh rates for conventional dynamic random access memory are somewhat longer, namely of the order of 10 microseconds, than this spin coherence time, a memory device embodying the present invention should have the advantage of a faster response time and lower power consumption in operation.

As will be appreciated by those skilled in the art, a number of memory devices 1 embodying the invention and having, for exmaple, the structure shown in Figure 3 may be integrated on the same substrate 11 and their input and output contacts Ll and L2 and gates G coupled so as to provide a two-dimensional memory.

Figures 11 and 12 illustrate diagrammatically one example of such a memory 30. Figure 11 showing a block diagram of the memory and Figure 12 part of a layout diagram for the array. In the interest of simplicity, Figure 11 shows a 3 by 3 array MA of memory devices 1. It will, however, be appreciated that, in practice, the memory array MA would generally be much larger.

As shown in Figure 11, the input contact Ll of each memory device 1 in a row is coupled to a respective row conductor Rl , R2 and R3 while the output contact L2 of each memory device 1 in a column is coupled to a corresponding column conductor CI, C2, C3. As is well known in the 2D array art, the row conductors Rl, R2 and R3 are coupled to an input drive or shift register 100 to enable the rows to be addressed in turn by an input signal provided via an input line 101 while each of the column conductors ci, C2 and C3 is coupled via a respective sense amplifier SA1 , SA2 and SA3 to output circuitry in the form of an output shift register 102 having an output 103 from which the content of the memory can be read. The gate G of each memory device 1 is separately connected by a gate conductor GC to a gate drive circuit 104 that enables the gate of each memory device 1 to be individually addressed in known manner.

As described above, the memory array MA is placed, in use, in a homogeneous DC magnetic field B_dc and data is stored in the memory using a pulsed AC magnetic field B_ac. In this memory, two different gate voltages may be applied with one voltage being applied when a memory device 1 is to store a "0" and the other gate voltage being applied when the memory device is to store a "1". When applied, one of these gate voltages pushes the wave function of the electrons on the quantum dot 2a of that memory device into a region of higher effective g-factor so changing the Zeeman splitting for that dot. The frequency ω of the AC magnetic field pulses B_ac is selected so as to match the Zeeman splitting for only those dots to which that gate voltage has been applied. Accordingly, a Rabi spin flip will occur only for the memory devices to which that gate voltage has been applied.

Individual memory devices within the array are addressed by addressing the row Rl, R2, R3 containing that memory device 1 and reading the current on the column CI, C2 , C3 containing that memory device. Thus, for example, memory device 1' is selected by addressing row Rl and reading column C2. If this memory device is a memory device to which the additional gate voltage has been applied, then a sequential tunnelling current I_s (Figure 10) will be detected whereas if this memory device is not a memory device to which the additional gate voltage has been applied, then only the very small cotunnelling current I_c will be detected. Accordingly, an output signal representing either a "0" or "1" can be obtained for that memory device.

To facilitate pushing of the wave function of the electrons into the region of higher effective g-factor by application of a different gate voltage, the quantum dots may be formed of a III-V alloy whose composition varies from top to bottom of the dot in Figure 3. Thus, for example, the quantum dot may be formed of a Gallium Indium Arsenide composition Ga^In^s where x varies from 0 to 1 throughout the depth of the quantum dot thereby causing the g-factor to vary from -0.44 when x is 0 and the material is Gallium Arsenide to +0.14 where x is 1 and the material is Indium Arsenide. As will be understood by those skilled in the art, this graded composition can readily be achieved using MBE or MOCVD techniques.

Figure 12 shows the arrangement of the row and column conductors Rl and C2 for the memory device 1 ' and also the gate conductor GC connected to that memory device to illustrate one possible layout for the memory array MA shown in Figure 11.

Another example of a memory 31 embodying the present invention will now be described with reference to Figures 13 and 14 where Figure 13 shows a cross sectional view through part of a semiconductor body 10 in which the memory devices 1 are formed and illustrates one memory device and Figure 14 shows a block diagram similar to Figure 11 for illustrating how the individual memory devices 1 are addressed.

As can be seen from Figure 13 , each memory device 1 has the same structure as shown in Figure 3. However, between the memory devices 1 and the substrate 11 is sandwiched a current grid arrangement consisting of a parallel spaced-apart first conductors 200 extending in the y direction in Figure 13 and, separated by an insulating layer 201 from the first conductors, parallel spaced- apart of second conductors 202 extending in the x direction in Figure 13 (that is into the plane of the paper) so that the first and second conductors 200^' and 202 are mutually perpendicular.

The second conductors 200 are separated from the memory devices 1 by an insulating layer 203. The insulating layer may, as is known in the art, comprise silicon dioxide or intrinsic Gallium Arsenide. The mutually perpendicular first and second conductors 200 and 202 are arranged such that each memory device is situated over a crossing point CP between a pair of first and second conductors 201 and 202.

Figure 14 shows a functional block diagram of a memory embodying the invention to illustrate a driving arrangement for the memory. Again in the interest of simplicity, a three by three memory array MA' is shown. It will, however, be appreciated that the memory array will generally consist of many more memory devices 1.

As in the embodiment shown in Figure 11, the input contacts Ll of rows of memory devices 1 are coupled via respective row conductors Rl to R3 to an input shift register 100 having an input 101 for enabling addressing of the row conductors in turn. Similarly, each of the output contacts L2 in a column is coupled via a corresponding column conductor CI to C3 and a corresponding sense amplifier SA1 to SA3 to an output shift register 102 having an output 103. In this example, all of the gates G are driven at the same voltage and are coupled via a common electrode CE to the gate drive circuit (GD) 104a as is well known in the art. Each of the first current conductors 201 is coupled to a first drive circuit 204 while each of the second conductors 202 is coupled to a second drive circuit 205. As can be seen in Figure 14, the pitch of the first and second current conductors 201 and 202 is smaller than that of the row and column conductors such that each memory device 1 is uniquely associated with a pair of first and second conductors 201 and 202. Thus, for example, the memory device 1₂₂ (where the ₂₂ indicates that the memory device is in the second row and the second column) is coupled to the fifth first conductor 201₅ and the fifth second conductor 202₅.

As in the above described embodiments, a DC magnetic signal generator is (although not shown in Figure 14) provided to generate the DC magnetic field B_dc and an AC magnetic field generator is provided to generate the AC magnetic field pulses B_ac perpendicular to the DC magnetic field B_dc.

In the embodiment shown in Figures 13 and 14, the current grid first and second drive circuits 204 and 205 are used in the same manner as the gate drive circuit 104 in Figure 11, that is to adjust locally the Zeeman splitting of a particular memory device. This is achieved in the embodiment shown in Figures 13 and 14 by supplying to the first and second conductors 201 and 202 uniquely associated with the selected memory device (for example, first conductor 20 l_s and second conductor 202_s for the memory device 1₂₂) currents which individually are insufficient but which together provide a magnetic field sufficient to cause the Zeeman splitting at the memory device 1₂₂ to match the AC resonance frequency of the AC magnetic field of B_ac. As in the example shown in Figure 11, only the memory devices (such as the memory device 1₂₂) directly addressed by the first and second drive circuits 204 and 205 will have a Zeeman splitting matching the AC resonance frequency of the AC magnetic field pulses B_ac and accordingly a Rabi spin flop will only occur for those devices. This enables individual memory devices to represent either a "0" or "1", depending on whether or not a spin flop has been introduced. The spin relaxation and refresh times will be similar to those discussed above with reference to Figure 11.

Figure 15 shows a cross sectional view similar to Figure 13 of a modification of the memory device shown in Figure 13. As shown very diagrammatically in Figure 15, an additional element in the form of a magnetic impurity 50 such as manganese is incorporated into the quantum dot region 2 such that there is no stray magnetic field leaking into the Fermi input and output leads 3 and 4 to affect the spin polarisation of the leads. As other possibilities, the additional magnetic element may be a hard magnetic layer or magnetic nanoparticles . The magnetic field from the additional magnetic element controls the Zeeman splitting at the quantum dot and the magnetic coercivity is such that the underlying current grid 201, 202 can be used to switch the magnetisation direction of the additional magnetic elements so as to reverse the Zeeman split energy levels (that is changing the spin down ground state into a spin up ground state or vice versa) and therefore allowing for a fully nonvolatile memory system. As another possibility, the additional magnetic element may be replaced by a layer of nuclear spin providing an Overhauser field which may be switched using standard nuclear magnetic resonance (NMR) techniques .

In the embodiments described above with reference to Figures 11 and 14, each individual memory device 1 is uniquely addressed by the gate drive circuitry 104 in Figure 11 and by the first and second drive circuits 204 and 205 of Figure 14. However, a multiplexing drive scheme may be used so that a memory embodying the invention may have the layout shown in Figures 11 and 14 may be modified as shown in Figures 16 which shows a memory 32 having again a 3 by 3 array MA" of memory devices 1 connected in rows by row conductors Rl to R3 connected to input drive circuitry 100 and connected in columns CI to C3 connected via respective sense amplifiers SA1 to SA3 to output circuitry 102.

In Figure 16 further drive circuits A, B and C are provided. The rows of memory devices 1 are associated with conductors Bl to B3 coupled to the drive circuit B while the columns of memory devices are associated with conductors Al to A3 coupled to the drive circuit A and a common electrode CC is coupled to the drive circuit C. Where the memory array uses gate control to control the Zeeman splitting as illustrated in Figure 11, then the conductors Al to A3 and Bl to B3 are connected to the gates G of the memory devices so that the voltage is provided on a conductor Al, A2 or A3 and the voltage provided on a conductor Bl, B2 and B3 is insufficient to cause the necessary Zeeman splitting while the combined voltage provided by the two conductors associated with a given memory device (for example, the conductors A2 and B2 associated with the memory device l_{2 2} in Figure 16) is sufficient for the Zeeman splitting at that quantum dot 2 to allow resonance with the AC magnetic field pulses B_AC to cause a Rabi spin flop. In this case, the drive C and the common electrode CC provide the DC magnetic field B_d0 common to all of the memory devices .

Where the memory 32 shown in Figure 16 operates by controlling the magnetic field to control the Zeeman splitting then drives A and B will be equivalent to the first and second drive circuits 204 and 205 in Figure 14 and drive C will be the gate drive circuit. In this case, the current supplied to individual conductors Al, A2 or A3 and Bl, B2 or B3 will be insufficient to cause the necessary magnetic field to achieve the Zeeman splitting required to achieved resonance with the AC magnetic field pulses B_ac and a magnetic field sufficient to cause the necessary Zeeman splitting will only be experienced by the memory device 1 at the crossover between selected conductors Al , A2 or A3 and Bl, B2 or B3, for example, the memory device 1_2,2 at the intersection of conductors A2 and B2.

In the embodiments described with reference to Figure 16, a multiplexing drive arrangement is used to both address and read the memory devices so that only one memory device is addressed or read at a time, that is only one conductor Al, A2 or A3 and only one conductor Bl, B2 or B3 is active at any one time to avoid cross talk problems between adjacent memory devices.

The memory devices described above may also be used as current switches by controlling the polarity of the magnetic field in the quantum dot region 2 and the Fermi output lead 4 by, for example, incorporating an additional magnetic element into the quantum dot region 2 and the Fermi output lead 4 where, as described above, the quantum dot region 2 is formed of a material such as Gallium Arsenide that has a negative g-factor (g = -0.44 for Gallium Arsenide) and the Fermi input and output leads 3 and 4 are formed of a II-VI magnetic material having a g-factor which is positive and considerably greater than the magnitude of the g-factor of the quantum dot region, as is the case for the n conductivity type Beryllium Manganese Zinc Selenide alloy discussed above.

The operation of this current switch will now be described with reference to Figures 17 and 18 each of which shows a conduction band energy level diagram for the switch.

The DC magnetic field B_dcl applied to the Fermi input lead 3 is such that the Fermi input lead 3 is in a spin polarised state with the spin polarisation state spin state up. In contrast, the DC magnetic field B_dcr applied to the quantum dot region 2 and the Fermi output lead 4 is of the opposite polarity so that the Fermi output lead 4 is spin polarised with the spin state being down. Figure 17. shows schematically, a spin state up electron 23 on the Fermi input lead 3 and a spin state down electron 24 on the Fermi output lead 4 . As shown in Figure 17, the uppermost ground state electron 25 in the quantum dot 2 is a spin state up electron.

As explained above with reference to Figures 4 to 8, spin conservation blocks tunnelling of the spin up state electron 23 into the singlet state E_s of the quantum dot 2a because the uppermost electron 25 already on the quantum dot 2 is also in the- spin up state. In the arrangement described above with reference to Figure 8, a cotunnelling current via a virtual triplet state was possible. However, in contrast, in the arrangement shown in Figure 17, the Fermi output lead 4 is spin-polarised in the spin-down state and so cannot accept a spin-up state electron. Accordingly, a cotunnelling current via the virtual triplet state is prohibited in the situation shown in Figure 17 and therefore no current can flow through the quantum dot 2a.

Figure 18 shows the same conduction band energy level diagram to illustrate the effect of reversing the polarity of the DC magnetic field B_dcr applied to the quantum dot 2a and the Fermi output lead 4. As shown, reversal of the DC magnetic field B_dcr causes the uppermost electron 25a on the quantum dot 2 to adopt a spin-down state enabling a spin-up state electron 23 from the Fermi input lead 3 to tunnel onto the singlet energy level E_s as shown in Figure 18. In addition, because the Fermi outpu . lead 4 is now spin polarised with the spin state up, the electron 23 can then tunnel off the quantum dot onto the Fermi output lead 4. Thus, sequential tunnelling via the singlet energy level E_s is now allowed and there is a finite sequential tunnelling current I_Ξ.

It will be appreciated from the above description that switching of the current switch described with reference to Figure 17 and 18 between the on and off state simply requires reversing of the polarity of the DC magnetic field applied to the quantum dot 2 and the Fermi output lead 4 and that there is no need for the AC magnetic field pulses B_ac described above. This current switch has the advantage that there is no leakage or cotunnelling in the off-state and, moreover, there is only one interface between the different directions of applied magnetic field which should considerably simplify the demands on the geometry of the magnetic field configuration.

Such current switches may also be used as memory devices and may be incorporated in a memory array similar to those described above with reference to Figures 14 and 16 wherein the state of each memory device is controlled by the magnetic field. In this case, the first and second drive circuits 204 and 205 shown in Figure 14 and the drive circuits A and B shown in Figure 16 will be used to control the polarisation of the magnetic field applied to the quantum dots 2a and output leads 4 and, as mentioned above, the AC magnetic field pulses B_aα will not be required. By controlling the magnetic field applied to individual current switches using the first and second drive circuits 204 and 205 (Figure 14) or the drive circuits A and B (Figure 16) each individual current switch will either be capable of or not capable of passing current and one of these two states can be used to represent "0" and the other to represent "1", thereby providing a dynamic random access memory as described above. The memory may be made non-volatile by, as described above, incorporating an additional magnetic element into the quantum dot regions 2a and the Fermi output leads 4. It will, of course, be appreciated that the current switch described above with reference to Figures 17 and 18 may also be implemented by applying a fixed DC magnetic field to the Fermi input lead 3 and the quantum dot region 2 and switching only the field applied to the Fermi output lead 4. However, such a switch may be less effective because its operation depends now on how fast the spin state on the quantum dot 2 relaxes to its ground state.

In the above described embodiments, the quantum dot region 2 is formed of Gallium Arsenide while the Fermi input and output leads are formed of an n conductivity type Beryllium Manganese Zinc Selenide alloy. However, the memory devices described with reference to Figures 1 to 16 above may be implemented using other materials provided that the magnitude of the g-factor of the material forming the quantum dot region 2 is very much less than the magnitude of the g-factor of the material forming the Fermi input and output leads 3 and 4 and, in case of the current switch described above with reference to Figures 17 and 18, provided that the g-factor of the material forming the quantum dot region 2 is negative, the g-factor of the material forming the Fermi input and output leads 3 and 4 is positive and is very much greater than the magnitude of the g-factor of the quantum dot region.

As described above, the memory device or current switch may be fabricated so that the dimensions of the quantum dot are about 50 nanometres which requires operation at very low temperature (typically liquid Helium temperature, that is a few Kelvin). However, the operating temperature increases dramatically with reduction in the quantum dot size so that, for example, a scaling down of the dot size by a factor of 10 would increase the temperature required by a factor of 100 allowing room temperature operation. As will be appreciated by those skilled in the art, Cadmium Selenide (CdSe) nanocrystals have been fabricated with a dot diameter of 6 nanometres and a Coulomb charging energy of 30 millielectron volts. Couloumb blockade behaviour has also been seen at high temperature in C_εo molecules and in carbon nanotubes (see for example the aforementioned text book entitled "Mesoscopic Electron Transport" by Sohn et al ) . Indeed, there is no fundamental physical discontinuity between a quantum dot and a large molecule or even atom and thus the present invention may also be applied to such quantum-confined nanostructure or regions .

Where size constraints make contact difficult then in the embodiments described above, scanning tunnelling electron microscope (STM) techniques may be used to address and read the state of a quantum dot .

In the above described embodiments, a large difference in g-factor between the Fermi input and output leads 3 and 4 and the quantum dot 2a is used to ensure that the Zeeman splitting within the Fermi input and output leads 3 and 4 is considerably greater than that in the quantum dot and that the input and output leads are therefore spin polarised, in the above embodiments this is achieved by using Gallium Arsenide to form the quantum dot region 2 and an n conductivity type Beryllium Manganese Zinc Selenide alloy to form the Fermi input and output leads . Other magnetic semiconductor materials may be used for the Fermi input and output leads and other non-magnetic semiconductor materials may be used for forming the quantum dot region. For example, following the proposals by Ohno et al in a letter to Nature published in Nature volume 402 on 16 December 1999 at page 790 to 792, the Fermi input and output leads may be formed of n conductivity type Gallium Arsenide doped with manganese while the quantum dot region may be formed of Indium Gallium Arsenide. Another possibility would be to work in the Quantum Hall regime as proposed by Ciorga et al in a paper entitled "The Addition Spectrum of a Lateral Dot from Coulomb and Spin Blockade Spectroscopy" (ar Xiv: cond-mat/9912446v2 , 19 April 2000) where the components may be fabricated from the same material, for example, a Gallium Arsenide two dimensional electron gas (2DEG).

The present invention provides a device where the spin state of a quantum dot can be read out or determined by sensing the current flowing through the quantum dot, which current is blocked or nearly blocked for one spin state and unblocked for the opposite spin state. Quantum dot having length scales of 10 to 50 nanometres can presently be fabricated using well known techniques as described in the aforementioned text book by Sohn et al . Production of a memory element having a total surface area of 50 nanometres by 50 nanometres should allow an array with memory densities of 260 Gigabits/inch².

Although the above described embodiments show vertical memory devices, the device may be produced in lateral configuration and on semiconducting or insulating substrates. As explained above, where necessary, addressing and read out of a memory array may be achieved using microscopic arrays of scanning tunnelling tips that are atomically sharp so that operation at a molecular or even atomic level may be possible.

Memories embodying the present invention may be used in, for example, quantum computation and communication where manipulation of electron spin is required or may be used in conventional computing environments to, for example, replace conventional hard drives. Also, very fast switching arrays of such devices may allow very fast switching with potentially large resistance ratios of low and high power industrial machinery.

Memory devices and switches embodying the present invention may also have applications in the area of opto- electronics enabling production of, for example, hybrid spin and optical electronic devices. Memory devices and switches embodying the present invention may also have applications in the area of tagging and tracking applications.

Claims

CLAIMS :

1. A memory comprising: a memory device having an input region for carrying a current, an output region for carrying a current, and a three-dimensionally confined quantum region arranged to operate in the Coulomb blockade regime and separating the input and output regions whereby charge carriers can only pass from the input region to the output region by tunnelling through the quantum region;

Zeeman splitting means for controlling Zeeman splitting in the memory device such that the input and output regions are spin polarised whereby conduction through the input and output regions is by charge carriers of one spin polarity; and control means for controlling the spin polarisation of an uppermost charge carrier in the quantum region to control the tunnelling current through the memory device.

2. A memory comprising: a memory device having an input region for carrying an electron current, an output region for carrying an electron current, and a three-dimensionally confined quantum region arranged to operate in the Coulomb blockade regime and separating the input and output regions whereby electrons can only pass from the input region to the output region by tunnelling through the quantum region;

Zeeman splitting means for controlling Zeeman splitting in the memory device such that the input and output regions are spin polarised whereby conduction through the input and output regions is by electrons of one spin polarity; and control means for controlling the spin polarisation of an uppermost electron in the quantum region to control the tunnelling electron current through the memory device.

3. A memory according to claim 1 or 2 , wherein the Zeeman splitting means comprises means for applying a DC magnetic field.

4. A memory according to claim 1, 2 or 3, wherein the control means comprises means for applying an AC magnetic field pulse for causing a Rabi spin flop in the quantum region when the Zeeman splitting in the quantum region is such that a resonance with the AC magnetic field pulse occurs.

5. A memory according to any one of the preceding claims, further comprising adjustment means for adjusting the Zeeman splitting within the quantum region.

6. A memory according to claim 5 , wherein the adjustment means comprises means for applying a gate voltage to the quantum region to adjust the energy levels within the quantum region.

7. A memory according to claim 5 or 6, wherein the adjustment means comprises means for locally controlling a DC magnetic field applied to the quantum region.

8. A memory according to claim 1 , 2 or 3 , wherein the control means comprises means for switching the direction of Zeeman splitting and thus the spin polarization of one of the input and output regions relative to the other of the input and output regions .

9. A memory according to claim 8, wherein the switching means is arranged to switch the direction of Zeeman splitting in the one of the input and output regions and also in the quantum region.

10. A memory according to any one of the preceding claims, wherein the quantum region is associated with a magnetic element and the control means is arranged to control the polarisation of the magnetic element and thus the spin state of the uppermost charge carrier in the quantum region.

11. A memory according to claim 10, wherein the magnetic element comprises a magnetic impurity within the quantum region.

12. A memory according to any one of the preceding claims, wherein the quantum region comprises a III-V semiconductor material.

13. A memory device according to claim 11, wherein the quantum region comprises a III-V semiconductor material and the magnetic impurity comprises manganese.

14. A memory according to claim 12 or 13, wherein the III-V semiconductor material comprises Gallium Arsenide.

15. A memory according to any one of the preceding claims, wherein the input and output regions comprise a heavily doped II-VI semiconductor material.

16. A memory according to any one of Claims 1 to 14, wherein the input and output regions comprise an n- conductivity type Beryllium Manganese Zinc Selenide alloy having the composition : Be_xMn_yZnx._x._ySe.

17. A memory according to Claim 16, wherein x=0.07 and y=0.03.

18. A memory according to any one of the preceding claims, wherein the quantum region comprises a quantum dot.

19. A memory according to any one of the preceding clams comprising a plurality of memory devices having the features set out in any one of the preceding claims.

20. A memory comprising: a two-dimensional array of memory devices each having an input region for carrying an electron current, an output region for carrying an electron current, and a three-dimensionally confined quantum region arranged to operate in the Coulomb blockade regime and separating the input and output regions whereby electrons can only pass from the input lead to the output lead by tunnelling through the quantum region; Zeeman splitting means for causing Zeeman splitting in the memory devices such that the input and output regions are spin polarised whereby conduction through the input and output regions of a memory device is by electrons of one spin polarity; adjustment means for adjusting the Zeeman splitting within an individual memory device or devices; spin-state changing means for changing . the spin state of the uppermost electron in the quantum region of only the adjusted Zeeman splitting memory device or devices to change the tunnelling current through that memory device or devices; addressing means for individually addressing each memory device; and read-out means for reading the current supplied by an addressed memory device to determine from the read current the spin state of the uppermost electron in the quantum region of the addressed memory device.

21. A memory according to Claim 20, wherein the Zeeman splitting means comprises means for applying a DC magnetic field to the array.

22. A memory according to claim 20 or 21, wherein the spin-state changing means comprises means for applying an AC magnetic field pulse for causing a Rabi spin flop in the quantum region of a memory device when the Zeeman splitting in the quantum region of that memory device is such that a resonance with the AC magnetic field pulse occurs.

23. A memory according to Claim 22, wherein the spin- state changing means is arranged to apply an AC magnetic field pulse to cause a Rabi spin flop in the quantum region of a memory device whose Zeeman splitting has been adjusted by the adjustment means.

24. A memory according to any one of claims 20 to 24, wherein the adjustment means comprises gate drive means for applying a gate voltage to the quantum region of a memory device to adjust the energy levels within the quantum region.

25. A memory according to claim 24, wherein the gate drive means comprises means for applying a gate voltage individually to each memory device.

26. A memory according to any one of claims 20 to 25, wherein the adjustment means comprises means for controlling a DC magnetic field applied to the quantum region of an individual memory device.

27. A memory according to claim 26, wherein the adjustment means comprises a first set of conductors arranged parallel to one another in a first direction and a second set of conductors arranged parallel to one another in a second direction perpendicular to the first direction with the first and second sets of conductors being arranged such that each memory device lies at a unique crossover point between a first and a second conductor, first drive means for supplying a current to a selected one of the first conductors and second drive means for supplying a current to a selected one of the second conductors whereby a memory device is selected in use by supplying currents to the first and second conductors associated with that memory device such that the combined current is sufficient to change the Zeeman splitting of the quantum region of the selected memory device at the crossover point between the selected first and second conductors .

28. A memory according to any one of claims 20 to 27, wherein the quantum region of a memory device is associated with a magnetic element thereby forming a non- volatile memory device and the adjustment means is arranged to control the polarisation of the magnetic element and thus the direction of Zeeman splitting.

29. A memory according to claim 27, wherein the quantum region of each memory device is associated with a magnetic element and the adjustment means is arranged to control the polarisation of the magnetic element and thus the direction of Zeeman splitting such that the polarisation of the magnetic element of a selected memory device is opposite to the polarisation of the magnetic element of a a non-selected memory device.

30. A memory according to claim 28 or 29, wherein the magnetic element comprises a magnetic impurity within the quantum region.

31. A memory comprising: a two-dimensional array of memory devices each having an input region for carrying an electron current, an output region for carrying an electron current, and a three-dimensionally confined quantum region arranged to operate in the Coulomb blockade regime and separating the input and output regions whereby electrons can only pass from the input lead to the output lead by tunnelling through the quantum region;

Zeeman splitting means for causing Zeeman splitting in the memory devices such that the input and output regions are spin polarised whereby conduction through the input and output regions of a memory device is by electrons of one spin polarity; switching means for enabling switching of each memory device between a first state in which the direction of Zeeman splitting and thus the spin polarization of the input and output regions is the same and a second state in which the spin polarisation of one of the input and output regions is switched relative to the other of the input and output regions, the arrangement being such that a current can only flow through a memory device when the input and output regions have the same spin polarisation; addressing means for individually addressing each memory device; and read-out means for reading the current supplied by an addressed memory device to determine from the read current whether the memory device is in the first or second state.

32. A memory according to claim 31, wherein the switching means is arranged to switch the direction of Zeeman splitting in the one of the input and output regions and also in the quantum region of a memory device.

33. A memory device according to claim 3 lor 32, wherein the quantum region of each memory device is associated with a magnetic element thereby forming a non-volatile memory device and the switching means is arranged to control the polarisation of the magnetic element and thus the direction of Zeeman splitting in the quantum region.

34. A memory according to claim 33, wherein the magnetic element comprises a magnetic impurity within the quantum region.

35. A memory according to any one of claims 20 to 34, wherein the quantum region comprises a III-V semiconductor material.

36. A memory according to claim 34, wherein the quantum region comprises a III-V semiconductor material and the magnetic impurity comprises manganese.

37. A memory according to claim 35 or 36, wherein the III-V semiconductor material comprises Gallium Arsenide.

38. A memory according to any one of Claims 20 to 37, wherein the input and output regions comprise a heavily doped II-VI semiconductor material.

39. A memory according to any one of Claims 20 to 37, wherein the input and output regions comprise an n- conductivity type Beryllium Manganese Zinc Selenide alloy having the composition : Be_xMn_yZn_!_χ__ySe.

40. A memory according to Claim 39, wherein x==0.07 and y=0.03.

41. A memory according to any one of claims 20 to 41, wherein the quantum region comprises a quantum dot.

42. A memory device having an input region for carrying a current, an output region for carrying a current, and a three-dimensionally confined quantum region arranged to operate in the Coulomb blockade regime and separating the input and output regions whereby charge carriers can only pass from the input lead to the output lead by tunnelling through the quantum region, the magnitude of the g- factor of the input and output regions being significantly larger than the magnitude of the g-factor of the quantum region such that when Zeeman splitting is induced in use by a magnetic field, the input and output regions are spin-polarised whereby conduction through the input and output regions is by charge carriers of one spin polarity.

43. A memory device having an input region for carrying a current, an output region for carrying a current, and a three-dimensionally confined quantum region arranged to operate in the Coulomb blockade regime and separating the input and output regions whereby charge carriers can only pass from the input lead to the output lead by tunnelling through the quantum region, the quantum region being formed of III-V semiconductor material and the input and output regions being formed of an n conductivity type II- VI alloy such that, when Zeeman splitting is induced in use by a magnetic field, the input and output regions are spin-polarised whereby conduction through the input and output regions is by charge carriers of one spin polarity.

44. A switching device comprising: a switching element having an input region for carrying a current, an output region for carrying a current, and a three-dimensionally confined quantum region arranged to operate in the Coulomb blockade regime and separating the input and output regions whereby charge carriers can only pass from the input lead to the output lead by tunnelling through the quantum region, the magnitude of the g-factor of the input and output regions being significantly larger than the magnitude of the g-factor of the quantum region such that when Zeeman splitting is induced in use by a magnetic field, the input and output regions are spin- polarised whereby conduction through the input and output regions is by charge carriers of one spin polarity; and switching means for enabling switching of the switching element between a first Zeeman split state in which the direction of Zeeman splitting and thus the spin polarization of the input and output regions is the same and a second Zeeman split state in which the spin polarisation of one of the input and output regions is switched relative to the other of the input and output regions, the arrangement being such that a current can only flow through the switching element when the input and output regions have the same spin polarisation.

45. A device according to claim 42, 43 or 44 wherein the quantum region comprises Gallium Arsenide.

46. A device according to claim 42, 43, 44 or 45, wherein the quantum region comprises Gallium Arsenide and the input and output regions comprise an n-conductivity type Beryllium Manganese Zinc Selenide alloy having the composition : Be_xMn_yZn^_x._ySe.

47. A device according to Claim 46, wherein x=0.07 and y=0.03.

48. A device according to any one of claims 42 to 46, wherein the quantum region is associated with a magnetic element.

49. A device according to claim 48, wherein the magnetic element comprises a magnetic impurity within the quantum region.

50. A device according to claim 49, wherein the magnetic impurity comprises manganese.

51. A device according to any one of claims 42 to 50, wherein the quantum region comprises a quantum dot.