WO2002013389A3 - An interconnection network for a field programmable gate array - Google Patents

An interconnection network for a field programmable gate array Download PDF

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Publication number
WO2002013389A3
WO2002013389A3 PCT/US2001/024445 US0124445W WO0213389A3 WO 2002013389 A3 WO2002013389 A3 WO 2002013389A3 US 0124445 W US0124445 W US 0124445W WO 0213389 A3 WO0213389 A3 WO 0213389A3
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WO
WIPO (PCT)
Prior art keywords
interconnection network
programmable gate
gate array
field programmable
network
Prior art date
Application number
PCT/US2001/024445
Other languages
French (fr)
Other versions
WO2002013389A2 (en
Inventor
Dale Wong
Original Assignee
Leopard Logic Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Leopard Logic Inc filed Critical Leopard Logic Inc
Priority to EP01959505A priority Critical patent/EP1305881A2/en
Priority to AU2001281054A priority patent/AU2001281054A1/en
Publication of WO2002013389A2 publication Critical patent/WO2002013389A2/en
Publication of WO2002013389A3 publication Critical patent/WO2002013389A3/en

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17736—Structural details of routing resources

Abstract

An interconnection network architecture which provides an interconnection network which is especially useful for FPGAs is described. Based upon Benes networks, the resulting network interconnect is rearrangeable so that routing between logic cell terminals is guaranteed. Upper limits on time delays for the network interconnect are defined and pipelining for high speed operation is easily implemented. The described network interconnect offers flexibility so that many design options are presented to best suit the desired application.
PCT/US2001/024445 2000-08-04 2001-08-03 An interconnection network for a field programmable gate array WO2002013389A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP01959505A EP1305881A2 (en) 2000-08-04 2001-08-03 An interconnection network for a field programmable gate array
AU2001281054A AU2001281054A1 (en) 2000-08-04 2001-08-03 An interconnection network for a field programmable gate array

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US22304700P 2000-08-04 2000-08-04
US60/223,047 2000-08-04

Publications (2)

Publication Number Publication Date
WO2002013389A2 WO2002013389A2 (en) 2002-02-14
WO2002013389A3 true WO2002013389A3 (en) 2002-08-01

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2001/024445 WO2002013389A2 (en) 2000-08-04 2001-08-03 An interconnection network for a field programmable gate array

Country Status (4)

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US (2) US6693456B2 (en)
EP (1) EP1305881A2 (en)
AU (1) AU2001281054A1 (en)
WO (1) WO2002013389A2 (en)

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Also Published As

Publication number Publication date
US6693456B2 (en) 2004-02-17
US20020113619A1 (en) 2002-08-22
EP1305881A2 (en) 2003-05-02
AU2001281054A1 (en) 2002-02-18
US6940308B2 (en) 2005-09-06
WO2002013389A2 (en) 2002-02-14
US20040150422A1 (en) 2004-08-05

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