WO2002015186A1 - Method and arrangement for concealing errors - Google Patents

Method and arrangement for concealing errors Download PDF

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Publication number
WO2002015186A1
WO2002015186A1 PCT/EP2001/008814 EP0108814W WO0215186A1 WO 2002015186 A1 WO2002015186 A1 WO 2002015186A1 EP 0108814 W EP0108814 W EP 0108814W WO 0215186 A1 WO0215186 A1 WO 0215186A1
Authority
WO
WIPO (PCT)
Prior art keywords
bitstream
modulator
single bit
error
signal
Prior art date
Application number
PCT/EP2001/008814
Other languages
French (fr)
Inventor
Derk Reefman
Alphons A. M. L. Bruekers
Original Assignee
Koninklijke Philips Electronics N.V.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninklijke Philips Electronics N.V. filed Critical Koninklijke Philips Electronics N.V.
Priority to EP01969552A priority Critical patent/EP1309972A1/en
Priority to JP2002520228A priority patent/JP2004507019A/en
Publication of WO2002015186A1 publication Critical patent/WO2002015186A1/en

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/10009—Improvement or modification of read or write signals
    • G11B20/10046—Improvement or modification of read or write signals filtering or equalising, e.g. setting the tap weights of an FIR filter
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/18—Error detection or correction; Testing, e.g. of drop-outs
    • G11B20/1876—Interpolating methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/10009—Improvement or modification of read or write signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/10009—Improvement or modification of read or write signals
    • G11B20/10222—Improvement or modification of read or write signals clock-related aspects, e.g. phase or frequency adjustment or bit synchronisation
    • G11B20/10231—Improvement or modification of read or write signals clock-related aspects, e.g. phase or frequency adjustment or bit synchronisation wherein an asynchronous, free-running clock is used; Interpolation of sampled signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/14—Digital recording or reproducing using self-clocking codes
    • G11B20/1403—Digital recording or reproducing using self-clocking codes characterised by the use of two levels
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/00007—Time or data compression or expansion
    • G11B2020/00014—Time or data compression or expansion the compressed signal being an audio signal
    • G11B2020/00065—Sigma-delta audio encoding
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/14—Digital recording or reproducing using self-clocking codes
    • G11B20/1403—Digital recording or reproducing using self-clocking codes characterised by the use of two levels
    • G11B2020/1476—Synchronisation patterns; Coping with defects thereof
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/18—Error detection or correction; Testing, e.g. of drop-outs
    • G11B20/1816—Testing
    • G11B2020/1823—Testing wherein a flag is set when errors are detected or qualified

Definitions

  • This invention relates to a method for concealing errors in a digital information signal. Such method is e.g. known from US-patent 5.715.312.
  • the storage medium when a digital information signal is stored on a storage medium, the storage medium also comprises an error correction code, which makes the retrieval from the medium more robust against possible errors in the information signal.
  • the error correction fails and then the remaining failures may extend for at least one frame or a number of frames. Such failure will, because of its duration of e.g. 1/75 sec. or more, be very troublesome.
  • the technique of error concealment seeks to replace the damaged area of the signal by a signal from a neighbouring undamaged frame.
  • the present invention has for its object to provide a method for concealing errors in a single bit bitstream signal.
  • Such signal format is e.g. adopted for the Super Audio Compact Disc (S A-CD) and the method according to the invention is therefore characterized in that the digital information signal is a single bit bitstream and that the method comprises low pass filtering the single bit bitstream for constructing the low frequency contents of the single bit bitstream, interpolating the low frequency contents during an error using low frequency contents before and/or after the error and converting the low frequency signal obtained after the interpolating into a regenerated single bit bitstream with concealed errors by means of a ⁇ -modulator.
  • S A-CD Super Audio Compact Disc
  • This method results in a cheap and easy to implement error concealment of single bit digital signals.
  • the quality standard is not very high.
  • the method implies that a signal, which is once quantized in a ⁇ -modulator, is requantized in a second ⁇ - modulator.
  • the higher signal frequencies which are still of importance for the faithful reproduction of the signal (e.g. about 100 kHz in case of audio-signals)
  • multiple quantization causes such deterioration of the signal quality that highest quality standards are not anymore fulfilled.
  • the method according to the invention may further be characterized by outputting the received single bit bitstream during the absence of an error and outputting the regenerated single bit bitstream during the occurrence of an error and by bit-synchronizing the ⁇ -modulator to the received single bit bitstream.
  • a single bit bitstream is low pass filtered and then remodulated into a second single bit bitstream, the two bitstreams are not any more identical so that switching between the two bitstreams causes audible clicks.
  • the two bitstreams have to be bit-synchronized in order to ensure that the two bitstreams are, substantially, equal around the moments of switching. Suitable methods of bit-synchronizing two bitstreams are disclosed in applicants copending European patent application... (ID 602604).
  • the invention also relates to an arrangement for carrying out the above described methods.
  • Such arrangement may be characterized in that it comprises in cascade a low pass filter for constructing the low frequency contents of the single bit bitstream, means for replacing the low frequency contents during an error by a low frequency approximation of the signal and a ⁇ -moduIator for converting the low frequency signal obtained after the replacement into a regenerated single bit bitstream with concealed errors.
  • the arrangement may preferably be further characterized by switching means applying the received single bit bitstream to an output terminal during the absence of an error and applying the regenerated single bit bitstream to the output terminal during the occurrence of an error and means for synchronizing the ⁇ -modulator to the received single bit bitstream.
  • Figure 1 a schematic diagram of a first arrangement according to the invention and Figure 2 a schematic diagram of a second arrangement according to the invention.
  • the arrangement of figure 1 comprises a compact disc storage unit S from which the stored information signal is obtained.
  • This signal which is a single bit digital signal in compressed format, is decompressed in decompressor unit D.
  • This unit also performs error correction on the received signal, so that at its output a corrected and uncompressed single bit bitstream is obtained.
  • the unit D also provides an error flag EF to identify those portions of the signal where the error correction failed and which portions have to be concealed in order to avoid or minimize audible distortions.
  • the single bit bitstream x(n) obtained from the decompressor unit D is e.g. a stream of +1 and -1 bits at a rate of 64 x 44,1 kHz and the mean value of which represents the useful low frequency (audio) information.
  • This information is extracted from the bitstream by a digital low pass filter F, which is preferably of fifth order and which has a cut off frequency of about 100 kHz.
  • This low frequency signal is fed to a unit I which is controlled by the error flag EF and which replaces, during an error, the damaged part of the signal by a reconstruction of the original signal which may be obtained by interpolation.
  • the interpolation is preferably done so, that with the undamaged parts of the signal discontinuities in the signal level are avoided.
  • a useful method of interpolation is e.g. the harmonic retrieval method which is described in the article: "Model Based Processing of Signals: A State Space Approach" of B.D. Rao and K.S. Arun in Proceedings of the IEEE Vol 80 , No 2 p.p. 283- 309, 1992.
  • the repaired LF-signal u(n) is converted to a new single bit bitstream y(n) by means of a ⁇ -modulator SD.
  • the low pass filter F has the object to free the input of the ⁇ -modulator from too large high frequency signal components.
  • the large HF signal components of the single bit bitstream would otherwise cause the ⁇ -modulator to malfunction and become unstable.
  • the cutoff frequency of the low pass filter is preferably chosen at about 100 kHz.
  • these higher LF frequencies have the disadvantage that they cause some distortion (noise) in the ⁇ - modulator SD. Therefore it is advisable to avoid that the signal, which has already been , converted to a single bit bitstream prior to its storage on the storage medium S, is converted a second time into a single bit bitstream. This is the object of the arrangement of figure 2.
  • this arrangement comprises a switch SW which is controlled by the error flag EF and which connects the original bitstream x(n) from the unit D directly to the output O when there is no error.
  • the switch SW connects the output of the ⁇ -modulator SD to the output O. Therefore, reconversion of the original bitstream into a second bitstream is avoided.

Abstract

A method of concealing errors in a single bit bitstream x(n) comprises low pass filtering (F) the bitstream, replacing the low pass filtered signal during an error (EF) by a low frequency approximation (J) of the signal u(n) and subsequently converting the signal by a ⊤Δ-modulator (SO) into a regenerated single bit bitstream y(n). During the absence of an error the original bitstream x(n) may be outputted and during an error the regenerated bitstream y(n), which is obtained from a ΣΔ-modulator (SD), which is bit-synchronized (SU) to the original bitstream x(n).

Description

Method and arrangement for concealing errors
This invention relates to a method for concealing errors in a digital information signal. Such method is e.g. known from US-patent 5.715.312.
Usually, when a digital information signal is stored on a storage medium, the storage medium also comprises an error correction code, which makes the retrieval from the medium more robust against possible errors in the information signal. However, sometimes the error correction fails and then the remaining failures may extend for at least one frame or a number of frames. Such failure will, because of its duration of e.g. 1/75 sec. or more, be very troublesome. The technique of error concealment seeks to replace the damaged area of the signal by a signal from a neighbouring undamaged frame.
The present invention has for its object to provide a method for concealing errors in a single bit bitstream signal. Such signal format is e.g. adopted for the Super Audio Compact Disc (S A-CD) and the method according to the invention is therefore characterized in that the digital information signal is a single bit bitstream and that the method comprises low pass filtering the single bit bitstream for constructing the low frequency contents of the single bit bitstream, interpolating the low frequency contents during an error using low frequency contents before and/or after the error and converting the low frequency signal obtained after the interpolating into a regenerated single bit bitstream with concealed errors by means of a ΣΔ-modulator.
This method results in a cheap and easy to implement error concealment of single bit digital signals. However, the quality standard is not very high. The method implies that a signal, which is once quantized in a ΣΔ-modulator, is requantized in a second ΣΔ- modulator. Especially at the higher signal frequencies, which are still of importance for the faithful reproduction of the signal (e.g. about 100 kHz in case of audio-signals), multiple quantization causes such deterioration of the signal quality that highest quality standards are not anymore fulfilled. In order to avoid such deterioration of the signal quality, the method according to the invention may further be characterized by outputting the received single bit bitstream during the absence of an error and outputting the regenerated single bit bitstream during the occurrence of an error and by bit-synchronizing the ΣΔ-modulator to the received single bit bitstream. When a single bit bitstream is low pass filtered and then remodulated into a second single bit bitstream, the two bitstreams are not any more identical so that switching between the two bitstreams causes audible clicks. To avoid these clicks the two bitstreams have to be bit-synchronized in order to ensure that the two bitstreams are, substantially, equal around the moments of switching. Suitable methods of bit-synchronizing two bitstreams are disclosed in applicants copending European patent application... (ID 602604).
The invention also relates to an arrangement for carrying out the above described methods. Such arrangement may be characterized in that it comprises in cascade a low pass filter for constructing the low frequency contents of the single bit bitstream, means for replacing the low frequency contents during an error by a low frequency approximation of the signal and a ΣΔ-moduIator for converting the low frequency signal obtained after the replacement into a regenerated single bit bitstream with concealed errors. The arrangement may preferably be further characterized by switching means applying the received single bit bitstream to an output terminal during the absence of an error and applying the regenerated single bit bitstream to the output terminal during the occurrence of an error and means for synchronizing the ΣΔ-modulator to the received single bit bitstream.
The invention will be further explained with reference to the attached figures. Herein shows:
Figure 1 a schematic diagram of a first arrangement according to the invention and Figure 2 a schematic diagram of a second arrangement according to the invention.
The arrangement of figure 1 comprises a compact disc storage unit S from which the stored information signal is obtained. This signal, which is a single bit digital signal in compressed format, is decompressed in decompressor unit D. This unit also performs error correction on the received signal, so that at its output a corrected and uncompressed single bit bitstream is obtained. The unit D also provides an error flag EF to identify those portions of the signal where the error correction failed and which portions have to be concealed in order to avoid or minimize audible distortions. The single bit bitstream x(n) obtained from the decompressor unit D is e.g. a stream of +1 and -1 bits at a rate of 64 x 44,1 kHz and the mean value of which represents the useful low frequency (audio) information. This information is extracted from the bitstream by a digital low pass filter F, which is preferably of fifth order and which has a cut off frequency of about 100 kHz. This low frequency signal is fed to a unit I which is controlled by the error flag EF and which replaces, during an error, the damaged part of the signal by a reconstruction of the original signal which may be obtained by interpolation. The interpolation is preferably done so, that with the undamaged parts of the signal discontinuities in the signal level are avoided. A useful method of interpolation is e.g. the harmonic retrieval method which is described in the article: "Model Based Processing of Signals: A State Space Approach" of B.D. Rao and K.S. Arun in Proceedings of the IEEE Vol 80 , No 2 p.p. 283- 309, 1992. Subsequently the repaired LF-signal u(n) is converted to a new single bit bitstream y(n) by means of a ΣΔ-modulator SD.
The low pass filter F has the object to free the input of the ΣΔ-modulator from too large high frequency signal components. The large HF signal components of the single bit bitstream would otherwise cause the ΣΔ-modulator to malfunction and become unstable. For this reason it would be wise to choose the cutoff frequency of the low pass filter as low as possible e.g. at about the highest audible frequency of 20 kHz. However, it has been found that the frequencies between 20 kHz and 100 kHz, although not audible per se, still contribute to the fidelity of the sound perception. For this reason the cutoff frequency of the low pass filter F is preferably chosen at about 100 kHz. On the other hand, these higher LF frequencies have the disadvantage that they cause some distortion (noise) in the ΣΔ- modulator SD. Therefore it is advisable to avoid that the signal, which has already been , converted to a single bit bitstream prior to its storage on the storage medium S, is converted a second time into a single bit bitstream. This is the object of the arrangement of figure 2.
In this arrangement elements, which correspond with those of figure 1, have been given corresponding references and need no further explanation. Additionally, this arrangement comprises a switch SW which is controlled by the error flag EF and which connects the original bitstream x(n) from the unit D directly to the output O when there is no error. On the other hand, when the error flag is set, the switch SW connects the output of the ΣΔ-modulator SD to the output O. Therefore, reconversion of the original bitstream into a second bitstream is avoided.

Claims

In the arrangement of figure 2 measures have to be taken to ensure that the • switching over from the original bitstream x(n) to the bitstream y(n) of the ΣΔ-modulator SD and vice versa does not cause audible clicks. These clicks would normally occur because the bits of the two bitstreams will usually not be equal, even when they carry exactly the same LF information. Therefore it is necessary to synchronise the bitstream y(n) of the ΣΔ- modulator to the received bitstream x(n) from the unit D. To this end, the arrangement of figure 2 comprises a synchronizing unit SU which receives the information of the original bitstream x(n) from unit D and the digital LF input signal u(n) of the ΣΔ-modulator and which generates a correction signal ε for application to one or more of the integrator states inside the ΣΔ-modulator. As already described in applicants copending European patent application (ID 602604) it is achieved by this measure that, after a certain number of bits, the bitstream of the ΣΔ-modulator runs substantially synchronously with the original bitstream. As an example: prior to the switching over from the original bitstream to the bitstream of the ΣΔ-modulator, the ΣΔ-modulator is synchronised to the original bitstream during about 5000 bits, then the switch SW supplies about 40000 bits of the ΣΔ-modulator to the output O, then, when the error flag is reset, the switch SW remains during 5000 bits connected to the ΣΔ- modulator until the ΣΔ-modulator is again synchronised to the original bitstream and then the switch reconnects the output O to this original bitstream.It is noted that the computational effort of the interpolator I is intensive because it has to be done at run time. To simplify or avoid the interpolation, the storage medium S may comprise, in a special area somewhere on the storage medium, a highly compressed image of the data stored normally on the medium. This highly compressed image is applied to the unit I through a dotted line HC and can be used to assist or replace the normal interpolation calculations. The same measure may be taken in the arrangement of figure 1. CLAIMS:
1. Method of concealing errors in a digital infonnation signal, characterized in that the digital information signal is a single bit bitstream (x(n)) and that the method comprises low pass filtering the single bit bitstream for constructing the low frequency contents (u(n)) of the single bit bitstream, replacing the low frequency contents during an error by a low frequency approximation of the single bit bitstream and converting the low frequency signal obtained after the replacement into a regenerated single bit bitstream (y(n)) with concealed errors by means of a ΣΔ-modulator (SD).
2. Method as claimed in claim 1 characterized by outputting the received single bit bitstream (x(n)) during the absence of an error and outputting the regenerated single bit bitstream (y(n)) during the occurrence of an error and by bit-synchronizing the ΣΔ-modulator (SD) to the received single bit bitstream (x(n)).
3. Arrangement for carrying out the method of claim 1 , characterized in that the arrangement comprises in cascade a low pass filter (F) for constructing the low frequency contents of the single bit bitstream, means (I) for replacing the low frequency contents during an error by a low frequency approximation of the signal and a ΣΔ-modulator (SD) for converting the low frequency signal (u(n)) obtained after the replacement into a regenerated single bit bitstream (y(n)) with concealed errors.
4. Arrangement as claimed in claim 3 characterized by switching means (SW) applying the received single bit bitstream (x(n)) to an output terminal (O) during the absence of an error and applying the regenerated single bit bitstream (y(n)) to the output terminal (O) during the occurrence of an error and means (SU) for synchronizing the ΣΔ-modulator (SD) to the received single bit bitstream.
PCT/EP2001/008814 2000-08-11 2001-07-31 Method and arrangement for concealing errors WO2002015186A1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP01969552A EP1309972A1 (en) 2000-08-11 2001-07-31 Method and arrangement for concealing errors
JP2002520228A JP2004507019A (en) 2000-08-11 2001-07-31 Method and configuration for concealing errors

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP00202832.2 2000-08-11
EP00202832 2000-08-11

Publications (1)

Publication Number Publication Date
WO2002015186A1 true WO2002015186A1 (en) 2002-02-21

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Country Status (6)

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US (1) US7127644B2 (en)
EP (1) EP1309972A1 (en)
JP (1) JP2004507019A (en)
KR (1) KR100810811B1 (en)
CN (1) CN1248228C (en)
WO (1) WO2002015186A1 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080004883A1 (en) * 2006-06-30 2008-01-03 Nokia Corporation Scalable audio coding
US8423852B2 (en) * 2008-04-15 2013-04-16 Qualcomm Incorporated Channel decoding-based error detection
US8358729B2 (en) * 2008-08-22 2013-01-22 Finisar Corporation Baseband phase-locked loop

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0578355A2 (en) * 1992-07-06 1994-01-12 Sony United Kingdom Limited Digital video tape recording/playback system and signal processing apparatus therefor
EP0776008A2 (en) * 1995-11-24 1997-05-28 Sony Corporation Recording method, reproducing apparatus, and a disc-shaped recording medium
WO1998016014A1 (en) * 1996-10-10 1998-04-16 Philips Electronics N.V. Data compression and expansion of an audio signal
JP2000163888A (en) * 1998-11-20 2000-06-16 Sony Corp Reproducing device

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4901077A (en) * 1988-04-18 1990-02-13 Thomson Consumer Electronics, Inc. Sigma-delta modulator for D-to-A converter
GB2263373B (en) * 1992-01-09 1995-05-24 Sony Broadcast & Communication Data error concealment
JPH06174147A (en) 1992-12-14 1994-06-24 Ebara Corp Vacuum valve
DE69612780T2 (en) 1995-03-24 2001-11-29 Sony Corp Method and device for interpolating digital data
WO1996033559A2 (en) 1995-04-21 1996-10-24 Philips Electronics N.V. Concealment method and arrangement and reproducing apparatus provided with the concealment arrangement
KR100587280B1 (en) * 1999-01-12 2006-06-08 엘지전자 주식회사 apparatus and method for concealing error

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0578355A2 (en) * 1992-07-06 1994-01-12 Sony United Kingdom Limited Digital video tape recording/playback system and signal processing apparatus therefor
EP0776008A2 (en) * 1995-11-24 1997-05-28 Sony Corporation Recording method, reproducing apparatus, and a disc-shaped recording medium
WO1998016014A1 (en) * 1996-10-10 1998-04-16 Philips Electronics N.V. Data compression and expansion of an audio signal
JP2000163888A (en) * 1998-11-20 2000-06-16 Sony Corp Reproducing device

Non-Patent Citations (4)

* Cited by examiner, † Cited by third party
Title
ANONYMOUS: "Super Audio Compact Disc - A Technical Proposal", INTERNET ARTICLE, 1997, pages 1 - 12, XP002186479, Retrieved from the Internet <URL:http://www.sel.sony.com/SEL/consumer/dsd/dsd.pdf> [retrieved on 20011220] *
D. REEFMAN, P. NUIJTEN: "AES Convention Paper : Editing and switching in 1-bit audio streams", INTERNET ARTICLE, 12 May 2001 (2001-05-12) - 15 May 2001 (2001-05-15), Amsterdam, Netherlands, pages 1 - 8, XP002186478, Retrieved from the Internet <URL:http://www.sacd.philips.com/b2b/downloads/edit_2.pdf> [retrieved on 20011219] *
PATENT ABSTRACTS OF JAPAN vol. 2000, no. 09 13 October 2000 (2000-10-13) *
See also references of EP1309972A1 *

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Publication number Publication date
CN1248228C (en) 2006-03-29
US7127644B2 (en) 2006-10-24
EP1309972A1 (en) 2003-05-14
KR20020039679A (en) 2002-05-27
JP2004507019A (en) 2004-03-04
CN1388970A (en) 2003-01-01
KR100810811B1 (en) 2008-03-06
US20020080957A1 (en) 2002-06-27

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