WO2002015262A1

WO2002015262A1 - Method of isolating semiconductor device

Info

Publication number: WO2002015262A1
Application number: PCT/KR2001/001364
Authority: WO
Inventors: Seung Joon Kim
Original assignee: Seung Joon Kim
Priority date: 2000-08-12
Filing date: 2001-08-10
Publication date: 2002-02-21
Also published as: AU2001277803A1

Abstract

An isolating method of a semiconductor substrate is provided. In the method, a silicon oxide layer, a polycrystalline silicon or amorphous silicon layer, a silicon nitride layer, and a photosensitive film pattern are formed. A portion of a lower layer formed over the semiconductor substrate is patterned using the photosensitive film patterned. A polymer spacer is formed on sidewalls of the patterned lower layer and the photosensitive film pattern to form a trench in the semiconductor substrate. A step difference between the semiconductor substrate and the lower layer is formed by the polymer spacer. The sidewall and bottom of the trench and the polycrystalline silicon or amorphous silicon layer having a step difference are transformed into a thermal oxide layer by an oxidation process. Thus, leakage current of the semiconductor device can be effectively inhibited and an isolation region becomes larger due to a step difference.

Description

D E S C R I P T I O N

METHOD OF ISOLATING SEMICONDUTOR DEVICE

1. Technical Field

The present invention relates to a method of isolating a semiconductor device, and more particularly, to a method of isolating a semiconductor device using a shallow trench.

2. Background Art

Conventionally, a local oxidation of silicon (LOCOS) method has been used as amethodof isolating semiconductor devices . Since intheLOCOSmethod, a silicon substrate itself is thermallyoxidized using a silicon nitride layer as a mask, a process of isolating semiconductor devices is simple and the quality of a generated silicon oxide layer is excellent. However, Bird's Beak occurs in the LOCOS method and the area of an isolation region is increased. Thus, the integration density of semiconductor devices cannot be increased.

To solve this problem, a shallow trench isolation (STI) method has been studied as an isolation technique to replace the LOCOS method. In the STI method, a trench is formed in a semiconductor device and is then filled with a dielectric material, thereby reducing the area of an isolation region. Thus, the STI method is advantageous to the downsizing of isolation regions, i.e., the integration density of semiconductor devices.

Aconventionalmethod of forming a STI regionwill be described with reference to FIGS. 1A through ID.

As shown in FIG. la, a silicon oxide layer 2 and a silicon nitride layer 3 are sequentially deposited on a semiconductor substrate 1 and then a photosensitive film is coated thereon. The photosensitive film is exposed/developed using an isolation mask (not shown) by a photolithography process to form a photosensitive filmpattern 4 which defines a semiconductor device isolation region FI.

As showing in FIG. IB, anexposedportionof the silicon nitride layer 3, the silicon oxide layer 2, and a predetermined thickness of the silicon substrate 1 are etched using the photosensitive film as a mask to form a trench 100.

As shown in FIG. 1C, the photosensitive film pattern 4 on the silicon nitride 3 is removed. A silicon oxide layer 5 is formed on the sidewall and bottom of the trench 10 by a thermal oxidation process .

A dielectric material (9 shown in FIG. ID) is deposited over the entire surface of the semiconductor substrate 1, by a chemical vapor deposition method, on which silicon oxide layer 5 is formed, to fill the trench 10. The silicon nitride layer 3 remaining on the semiconductor substrate 1 is removed by chemical mechanical polishing and then, the remaining silicon oxide layer 2 is removed, thereby completing an isolation layer (9 shown in FIG. ID) .

As shown in FIG. ID, a gate dielectric film 6 of a transistor and a polycrystalline silicon layer 7 are sequentially formed in a device region Al in the semiconductor substrate 1.

The silicon oxide layers 2 and 5 are necessarily removed to a predetermined thickness until the polycrystalline silicon layer

7 is formed when filling the trench 10 with a dielectric material and thenplanarizing the dielectricmaterial. As a result, an upper edge of the isolation layer 9 comes off from the isolation layer 9 to form a dent 8.

Accordingly, an electric field is concentrated in the dent

8 if a voltage is applied to the polycrystalline silicon layer 7 whichwill be a gate electrode. As a result leakage current occurs .

3. Disclosure of Invention

To solve the above-described problems, it is a first object of the present invention to provide a method of isolating a semiconductor device which can prevent leakage current from occurring due to the concentration of an electric field on upper edges of a device region and an isolation region. It is a second object of the present invention to provide a method of isolating a semiconductor device which is appropriate for the integration of the semiconductor device by increasing the size of an isolation region.

To achieve the first and second objects, according to an aspect of the present invention, a silicon oxide layer, a first material layer containing a silicon component, and a silicon nitride layer are sequentially formed over a semiconductor substrate and then the silicon nitride layer is coated with a photosensitive film. The coated photosensitive film is patterned using an isolation mask and then at least one layer underneath the patterned photosensitive film is etched to any one level ranging from a point near the bottom of the silicon nitride layer to a point near the top of the semiconductor substrate. A polymer spacer is formed on sidewalls of the patterned photosensitive film and the at least one etched layer underneath the patterned photosensitive film. Unetched layers underneath the patterned photosensitive film and the semiconductor substrate are etched to a predetermined depth using the polymer spacer and the patterned photosensitive film as a mask to form a trench. To achieve the first and second objects, according to another aspect of the present invention, a first silicon oxide layer, a first material layer containing a silicon component, a second silicon oxide layer, and a silicon nitride layer are sequentially formed over a semiconductor substrate and then the silicon nitride is coated with a photosensitive film. The coated photosensitive film is patterned using an isolation mask and then at least one layer underneath the patterned photosensitive film is etched to any one level ranging from a point near the bottom of the silicon nitride to a point near the top of the semiconductor substrate. A polymer spacer is formed on sidewalls of the patterned photosensitive film and the at least one etched layer underneath thepatternedphotosensitive film. Unetched layers underneath the patterned photosensitive film and the semiconductor substrate are etched to a predetermined depth using the polymer spacer and the patterned photosensitive film as a mask to form a trench.

In both aspects, after forming the trench, the patterned photosensitive film and the polymer spacer are removed to form a step difference over the semiconductor substrate. The resultant structure is oxidized in an oxygen atmosphere to form a bulky oxide layer on the inner wall and bottom of the trench and the side of the first material. Here, the first material may be formed of polycrystalline silicon or amorphous silicon. In both aspects, after forming the trench, the patterned photosensitive film and the polymer spacer are removed to form a step difference over the semiconductor substrate. A second material layer is formed over the resultant structure to form an oxide by a thermal process in an oxygen atmosphere. The second material layer is oxidized to transform the second material layer into a thermal oxide . Here, the secondmaterial layermay be formed of polycrystalline silicon or amorphous silicon.

To achieve the first and second objects, according to another aspect of the present invention, a silicon oxide layer and a nitride layer are sequentially formed over a semiconductor substrate and the nitride layer is coated with a photosensitive film. The coated photosensitive film is patterned and then the nitride layer is etched. Apolymer spacerhaving apredeterminedthickness is formed on the sidewall of the photosensitive film and the sidewall of the nitride layer using an isolation mask in a dry etcher. The silicon oxide layer and the semiconductor substrate are etched to a predetermined depth using the photosensitive film and the polymer spacer as a mask to etch a trench where a step difference is formed from the silicon oxide layer.

To achieve the first and second objects, according to another aspect of the present invention, a silicon oxide layer and a nitride layer are sequentially formed over a semiconductor substrate and the nitride layer is coated with a photosensitive film. The coated photosensitive film is patterned using an isolation mask and then the nitride layer is etched to a predetermined thickness . Apolymer spacer having a predetermined thickness is formed on the sidewall of the photosensitive film and the sidewall of the nitride layer in a dry etcher^'. The unetched remaining portion of the nitride layer, the silicon oxide layer, and the semiconductor substrate are etched to a predetermined depth using the photosensitive film and the polymer spacer as a mask to etch a trench where a step difference is formed fromthe nitride layer . Here, it is preferable that the thickness of the nitride layer remaining after etching the nitride layer to a predetermined thickness is 50 - 20% of the original nitride layer. Also, in all the above-described embodiments, the sidewall of the patterned nitride layer makes an angle of 80 - 100DD with the layers underneath the patterned photosensitive film. The polymer spacer is formed using at least one of bromine (Br) , chlorine (CI) , fluorine (F) , nitrogen (N) , argon (Ar) , and hydrogen (H) in a dry etcher. A chamber of the dry etcher for forming the polymer spacer is preferably at apressure of 2 - lOO Torr, at a power of 150 - 700W, and at an etching ratio of CF4:CHF3:Ar = 1:1-5:10-20.

Also, in all the above-described aspects, a step difference of the first material layer, the nitride layer, the silicon oxide layer, or the silicon substrate formed due to the polymer spacer is preferably 5 - 200 A when the width of the patterned isolation region is 0.2μm. The silicon oxide layer, the first silicon oxide layer, or the second silicon oxide layer is a thermal oxide layer formed by a thermal oxidation process or is an oxide layer formed by CVD or ALD. The silicon oxide layer, the first silicon oxide layer, or the second silicon oxide layer has a thickness of 30 - 300 A.

The polycrystalline silicon layer or the amorphous silicon layer is doped or implanted with arsenic (As) , phosphorus (P) , or boron (B) , or not doped or implanted with impurities.17. The polycrystalline silicon layer or the amorphous silicon layer has a thickness of 10 - 500 A.

As described above, in the present invention, an edge of a silicon substrate at the border between a device region and an isolation region protrudes a predetermined distance from the sidewall of an isolation layer using a polymer spacer and a thermal oxidation process in a process of forming a shallow trench for isolating a semiconductor device. Thus, leakage current can effectively be inhibited. In the prior art, a device region formed by a step difference formed due to a polymer spacer is larger than a device regionof a semiconductor device havingan isolation region. Accordingly, of transistors having the same dimensions, one to which the present invention is applied is supplied with a larger amount of current. Also, a process margin is increased and the isolation region is increased when forming a contact with a bit line or a storage electrode, thereby reducing contact resistance.

4. Brief Description of Drawings

The above objects and advantages of the present invention will become more apparent by describing in detail preferred embodiments thereof with reference to the attached drawings in which:

FIGS .1A through ID are cross-sectional views showing a method of isolating a semiconductor device according to the prior art;

FIGS.2A through 2H are cross-sectional views showing a first embodiment of amethod of isolating a semiconductor device according to the present invention;

FIGS. 3A and 3B are cross-sectional views showing a second embodiment of amethod of isolating a semiconductor device according to the present invention;

FIGS .4A through 4E are cross-sectional views showing a third embodiment of amethod of isolatinga semiconductor device according to the present invention;

FIGS. 5A and 5B are cross-sectional views showing a fourth embodiment of amethod of isolating a semiconductor device according to the present invention;

FIGS .6A through 6D are cross-sectional views showing a fifth embodiment of amethodof isolating a semiconductor device according to the present invention; and

FIGS.7A through 7D are cross-sectional views showing a sixth embodiment of amethodof isolating a semiconductor device according to the present invention. 5. Modes for Carrying out the Invention

Hereinafter, embodiments of the present invention will be described with reference to the attached drawings. First Embodiment Referring to FIGS. 2A through 2H, a silicon oxide 112, a material layer 113 containing a silicon component, and a silicon nitride layer 114 are sequentially formed over a semiconductor substrate 111. The material layer 113 containing a silicon component may be a polycrystalline silicon layer or an amorphous silicon layer and in the present embodiment, a polycrystalline silicon layer is used as the material layer 113 containing a silicon component. The silicon oxide layer 112 may be formed by a thermal oxidation process, a chemical vapor deposition (CVD) method or an atomic layer deposition (ALD) method. It is preferable that the silicon oxide layer 112 is formed to a thickness of 30 - 300 DD. The polycrystalline silicon layer (or the amorphous silicon layer) 113 may be doped with any one of arsenic (AS) , phosphorous (P) , and boron (B) . It is preferable that the polycrystalline silicon layer 113 is deposited to a thickness of 10 - 500 DD. A photosensitive film is coated on the silicon nitride layer 114 and is then patterned to form a photosensitive film pattern 115 by a photolithography process, thereby defining an isolation region Fill.

As shown in FIG.2B, an exposed portion of the silicon nitride layer 114 is etched to be removed using the photosensitive film 115 as a mask. Here, it is preferable that the polycrystalline silicon layer 113 makes an angle 116 of 80 - 100 DD with the sidewall of the silicon nitride layer 114.

As shown in FIG.2C, a polymer spacer 117 having a predetermined thickness is formed on the sidewall of the photosensitive film pattern 115 and the sidewall of the silicon nitride layer 114 using a dry etcher when the polycrystalline silicon layer 113 is exposed. Here, the polymer spacer 117 may be formed before, during or after etching the polycrystalline silicon layer (or the amorphous silicon layer) 113.

Here, it is preferable that the polymer spacer 117 is formed using at least one of bromine (Br) , chlorine (CI) , fluorine (F) , nitrogen (N) , argon (Ar) , and hydrogen (H) , and using a dry etcher . For example, the polymer spacer 117 having a thickness of 5 - 200 DD may be formed at a pressure of 2- 100 mTorr, at a power of 150 - 700W, and at a ratio of an etching gas of CF4:CHF3:Ar = 1:1 - 5: 10 - 20. As shown in FIG.2D, an exposed portion of the polycrystalline silicon layer (or the amorphous silicon layer) 113 and a portion of the silicon oxide layer 112 are etched to be removed using the photosensitive film 115 and the polymer spacer 117 as a mask to expose a portion of the semiconductor substrate 111 in the isolation region Fill.

As shown in FIG. 2E, the exposed portion of the semiconductor substrate 111 is etched to a predetermined depth using the photosensitive film 115 and the polymer spacer 117 as a mask to form a trench 128. As shown in FIG. 2F, the photosensitive film 115 and the polymer spacer 117 are removed. Here, the step difference W due to the polycrystalline silicon layer 113 is preferably 5 - 200 DD when the width of the isolation region Fill is 0.2 μm.

As shown in FIG.2G, the inner wall and sidewall of the trench

128 and the sidewall of the polycrystalline silicon layer 113 are oxidized by performing a thermal treatment under an oxygen atmosphere to form a thermal oxide layer 123. Thus, an upper edge ^' 122 of the trench 128 is covered with the thermal oxide layer 123.

A dielectric material is deposited over the surface of the semiconductor substrate 111 by a chemical vapor deposition method to fill the trench 128. Next, the silicon nitride layer 114 and the polycrystalline silicon layer 113 are removed by chemical mechanical polishing to planarize the semiconductor substrate 111, thereby forming an isolation layer 121 as shown in FIG. 2H.

Second Embodiment

After the steps shown in FIGS 2A through 2F, as shown in FIG. 3A, a material layer 118 containing a silicon component is formed over the surface of the semiconductor substrate 111 to form an oxide layer by a thermal process under an oxygen atmosphere. The material layer 118 containing a silicon component may be a polycrystalline silicon layer or an amorphous silicon layer, and a polycrystalline silicon layer having a thickness of 10 - 500 A is used as the material layer 118 containing a silicon component in the present embodiment.

As shown in FIG. 3B, the polycrystalline silicon layer 118 is oxidized by a thermal oxidation process to form a thermal oxide layer 119 on the inner wall and bottom of the trench 128 and the surf ces ofthe silicon oxide layer 112, thepolycrystalline silicon layer 113, and the silicon nitride layer 114. Here, a portion of the side ofthe polycrystalline silicon layer 113 interposedbetween the silicon oxide layer 112 and the silicon nitride layer 114 is oxidized by the thermal oxidation. Thus, an upper edge 120 of the trench 128 is covered with the thermal oxide layer 119.

However, as shown in FIG.3B, the upper edge 120 of the trench

128 is covered with the thermal oxide layer 119 having a lower etch rate or removal rate than the isolation layer 121. Thus, as shown in FIG. 2H, an upper edge of the isolation layer 121 is not dented after a planarization process.

In the first and second embodiments, the polymer spacer 117 is formed before etching the polycrystalline silicon layer 113. However, the polymer spacer 117 may be formed while or after etching the polycrystalline silicon layer 113 or the silicon oxide layer

112.

Third Embodiment

Steps shown in FIGS 4A through 4E are substantially the same as the steps shown FIGS.2A through 2H except that a second silicon oxide layer 214 as well as a polycrystalline silicon layer 213 is formed over a first silicon oxide layer 212. It is preferable that the second silicon oxide layer 214 is an oxide layer formed by a CVD method or ALD method and has a thickness of 30 - 300 A. Reference numerals 211, 212, 213, 215, 216, and 217 correspond to reference numerals 111, 112, 113, 114, 115, and 117 of the first and second embodiments.

Fourth Embodiment

Referring to FIGS. 5A and 5B, in the third embodiment, the STI is etched, the photosensitive film and the polymer spacer are removed, the polycrystalline silicon layer 218 (shown in FIG. 5A) is formed, and a thermal process is performed under an oxygen atmosphere. Then, as shown in FIG. 5B, a thermal oxide layer 219 is formed on the inner wall and sidewall of the trench 128 and the side of the polycrystalline silicon layer 218. Thus, an upper edge of the trench 128 is covered with the thermal oxide layer

219 so that an upper edge 220 of the isolation region is not dented.

In the third and fourth embodiments, the polymer spacer 217 is formed before the second silicon oxide layer 214 is etched. However, the polymer spacer 217 may be formed while or after etching the second silicon oxide layer 214, the polycrystalline silicon layer 213 or the silicon oxide layer 212. 5 Fifth Embodiment

Referring to FIGS.6Athrough 6D, as shown in FIG.6A, a silicon oxide layer 312 is grown from a semiconductor substrate 311. A silicon nitride layer 313 is stacked on the silicon oxide layer 312. A photosensitive film is coated on the silicon nitride layer 10 313 and is then patterned by a photolithography process to form a photosensitive film pattern 314. As shown in FIG.6B, an exposed portion of the silicon nitride layer 313 is etched to be removed using the photosensitive film pattern 314 as a mask to expose a portion of the silicon oxide layer 312 over the isolation region 15 Fill.

As shown in FIG.6C, apolymer spacer 315 having apredetermined thickness is formed on the sidewalls of the photosensitive film pattern 314 and the silicon nitride layer 313 using a dry etcher when the silicon oxide layer 312 is exposed. Here, the polymer 20 spacer 315 is formed before etching the silicon oxide layer 312, but may be formed while etching the silicon oxide layer 312.

As shown in FIG. 6D, the silicon oxide layer 312 is etched andthenthe semiconductor substrate 311 is etchedto apredetermined depth using the photosensitive film pattern 314 and the polymer 25 spacer 315 as a mask to form a trench 318.

It is not shown, but the polymer spacer 315 and the photosensitive film pattern 314 are removed to form steps. Sixth Embodiment

The exposed portion of the silicon nitride layer 313 is

30 entirely etched using the photosensitive film pattern 314 in the fifth embodiment, but only a predetermined thickness of an exposed portion of a silicon nitride layer 413 is etched using a photosensitive film pattern 414 in the present embodiment shown in FIGS.7A through 7D. Here, it is preferable that the thickness of the remaining exposed portion of the silicon nitride layer 413 is 50 - 20% of the thickness of the original silicon nitride layer 413. A polymer spacer 415 may be formed before or while etching the remaining exposed portion of the silicon nitride layer 413. Reference numerals 411, 412, 413, 414, and 415 correspond to reference numerals 311, 312, 313, 314, and 315 of the fifth embodiment.

Table 1 below shows characteristics of a transistor having dimensions of 0.22μmX 0.16μm isolated by an isolation layer formed according to the first embodiment of the present invention compared with characteristics of a transistor having dimensions of 0.22μm X 0.16μm isolated by an isolation layer formed according to the prior art shown in FIGS. 1A through ID. Here, resistance values were measured by a borderless contact. The silicon oxide layer has a thickness of 150 A, the polycrystalline silicon layer has a thickness of 450 A, and the nitride layer has a thickness of 1500 A when forming the isolation regions according to the first embodiment and the prior art shown in FIGS. 1A through ID. [Table 1]

Characteristic Prior Art Present Invention

Leakage Current (A) NMOS 4.55E-11 NMOS 8.01E-12

PMOS 1.96E-09 PMOS 6.55E-11

Drain Current (mA) NMPS 860.38 NMOS 961.74

PMOS 373.96 PMOS 392.70

Breakdown Voltage NMOS 0.51 NMOS 0.55 (V) PMOS -0.39 PMOS -0.47

Contact Resistance NMOS 33.61 NMOS 26.49 (Ω)

PMOS 33.14 PMOS 30.04

Claims

C L A I M S

1. A method of isolating a semiconductor device comprising:

(a) sequentially forming a silicon oxide layer, a first material layer containing a silicon component, and a silicon nitride layer over a semiconductor substrate and coating the silicon nitride layer with a photosensitive film;

(b) patterning the coated photosensitive film using an isolation mask, etching at least one layer underneath the patterned photosensitive film to any one level ranging from a point near the bottom of the silicon nitride layer to a point near the top of the semiconductor substrate, and forming a polymer spacer on sidewalls of the patterned photosensitive film and the at least one etched layer underneath the patterned photosensitive film; and (c) etching unetched layers underneath the patterned photosensitive film and the semiconductor substrate to a predetermined depth using the polymer spacer and the patterned photosensitive film as a mask to form a trench.

2. A method of isolating a semiconductor device comprising: (a) sequentially forming a first silicon oxide layer, a first material layer containing a silicon component, a second silicon oxide layer, and a silicon nitride layer over a semiconductor substrate, and coating the silicon nitride with a photosensitive film; (b) patterning the coated photosensitive film using an isolation mask, etching at least one layer underneath the patterned photosensitive film to any one level ranging from a point near the bottom of the silicon nitride to a point near the top of the semiconductor substrate, and forming a polymer spacer on sidewalls of the patterned photosensitive film and the at least one etched layer underneath the patterned photosensitive film; and

(c) etching unetched layers underneath the patterned photosensitive film and the semiconductor substrate to a predetermined depth using the polymer spacer and the patterned photosensitive film as a mask to form a trench.

3. The method of claim 1 or 2, after step (c) , further comprising: removing the patterned photosensitive film and the polymer spacer to form a step difference over the semiconductor substrate; and oxidizing the resultant structure in an oxygen atmosphere to form a bulky oxide layer on the inner wall and bottom of the trench and the side of the first material.

4. The method of claim 1 or 2, wherein the first material is formed of polycrystalline silicon or amorphous silicon.

5. Themethodof claim1 or 2, after step (c) further comprising; removing the patterned photosensitive film and the polymer spacer to form a step difference over the semiconductor substrate; forming a second material layer over the resultant structure to form an oxide by a thermal process in an oxygen atmosphere; and oxidizing the second material layer to transform the second material layer into a thermal oxide.

6. The method of claim 5, wherein the second material layer is formed of polycrystalline silicon or amorphous silicon.

7. A method of isolating a semiconductor device comprising: sequentially forming a silicon oxide layer and a nitride layer over a semiconductor substrate and coating the nitride layer with a photosensitive film; patterning the coated photosensitive film and then etching the nitride layer; forming a polymer spacer having a predetermined thickness on the sidewall of the photosensitive film and the sidewall of the nitride layer using an isolation mask in a dry etcher; and etching the silicon oxide layer and the semiconductor substrate to a predetermined depth using the photosensitive film and the polymer spacer as a mask to etch a trench where a step difference is formed from the silicon oxide layer.

8. A ethodof isolating a semiconductor substrate comprising: sequentially forming a silicon oxide layer and a nitride layer over a semiconductor substrate and coating the nitride layer with a photosensitive film; patterning the coated photosensitive filmusing an isolation maskandthenetchingthenitride layerto apredeterminedthickness; forming a polymer spacer having a predetermined thickness on the sidewall of the photosensitive film and the sidewall of the nitride layer in a dry etcher; and etching the unetched remaining portion of the nitride layer, the silicon oxide layer, and the semiconductor substrate to a predetermined depth using the photosensitive film and the polymer spacer as a mask to etch a trench where a step difference is formed from the nitride layer.

9. The method of claim 8, wherein the thickness of the nitride layer remaining after etching the nitride layer to a predetermined thickness is 50 - 20% of the original nitride layer.

10. The method of claim 1, 2, 7, or 8, wherein the sidewall of the patterned nitride layer makes an angle of 80 - 100DD with the layers underneath the patterned photosensitive film.

11. The method of claim 1, 2, 7, or 8 , wherein the polymer spacer is formed using at least one of bromine (Br) , chlorine (CI) , fluorine (F) , nitrogen (N) , argon (Ar) , and hydrogen (H) in a dry etcher.

12. Themethod of claim 11, wherein a chamber of the dry etcher for forming the polymer spacer is at a pressure of 2 - lOOmTorr, at a power of 150 - 700W, and at an etching ratio of CF4:CHF3:Ar = 1:1-5:10-20.

13. The method of claim 1, 2, 7, or 8, wherein a step difference of the first material layer, the nitride layer, the silicon oxide layer, or the silicon substrate formed due to the polymer spacer is 5 - 200 A when the width of the patterned isolation region is 0.2μm.

14. The method of claim 1, 2, 7, or 8, wherein the silicon oxide layer, the first silicon oxide layer, or the second silicon oxide layer is a thermal oxide layer formed by a thermal oxidation process or is an oxide layer formed by CVD or ALD.

15. The method of claim 14, wherein the silicon oxide layer, the first silicon oxide layer, or the second silicon oxide layer has a thickness of 30 - 300 A.

16. The method of claim 1, 2, or 4, wherein the polycrystalline silicon layer or the amorphous silicon layer is doped or implanted with arsenic (As) , phosphorus (P) , or boron (B) , or not doped or implanted with impurities.

17. Themethodof claiml6, whereinthepolycrystalline silicon layer or the amorphous silicon layer has a thickness of 10 - 500

A.