WO2002015356A1

WO2002015356A1 - Memory access conversion mechanism

Info

Publication number: WO2002015356A1
Application number: PCT/US2001/023967
Authority: WO
Inventors: Han-Ping Chen
Original assignee: Chen Han Ping
Priority date: 2000-08-16
Filing date: 2001-08-02
Publication date: 2002-02-21
Also published as: AU2001279102A1; GB0210937D0

Abstract

A method and apparatus controls the memory access of memory devices with a memory access controller (401) in order to bridge the memory type difference between the system memory interface and the primary memory unit, or to utilize partially defective memory devices to construct usable memory chip, module, or subsystem assemblies that meet the specification of a fully or partially functional assembly.

Description

MEMORY ACCESS CONVERSION MECHANISM BACKGROUND OF THE INVENTION

This invention relates to semiconductor memory devices, memory chips, memory modules, memory controllers, different memory types, defective memory elements, and memory operational conditions.

In order to speed up the memory access time, or to reduce the component cost, the memory industry introduces several generations of memory devices. In recent years, there are SRAM, DRAM, EDO DRAM, SDRAM, and DDR DRAM.

Each major category of memory device also contains a range of different memory access speeds. Among them, there are 80 MHz, 100 MHz, and 133 MHz memory devices.

System manufacturers need to find a particular memory type to meet the system requirements. To avoid excessive cost for faster memory units, a system may sometimes become unstable at a later time because of different memory operational conditions. Such a change in condition may be a result of increased loading introduced by system enhancements, especially memory expansion.

Furthermore, due to the yield limitation of semiconductor fabrication process, a semiconductor memory wafer usually contains defective memory devices. As the cell density of the semiconductor device increases, it is becoming harder to achieve high production yield. During the device fabrication process, certain repairing process may be used to replace defective rows or columns in the memory cell array. However, there is a limit as to the capability of such repairing process. Some memory devices remain defective at the semiconductor die level after the fabrication process.

To repair the memory devices above the die level is a complex issue regarding the feasibility, efficiency, and cost effectiveness. BRIEF SUMMARY OF THE INVENTION

This invention proposes a method and apparatus to efficiently handle the memory types, memory defects, and memory operational conditions.

It is an objective of the present invention to construct memory chip or module packages with one type of memory devices to meet the requirements of a different type of memory devices.

It is another objective of the present invention to control the memory access such that it will remain functional under different memory operational conditions.

This invention also provides a method to utilize partially defective memory devices to construct usable memory chip or module packages that meet the specification of a functional package.

This invention provides a method that maximizes the usage of non- defective memory data bits in the partially defective memory devices.

This invention further provides a method to minimize or eliminate the initialization of the chips or modules. BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram of a prior art memory chip.

FIG. 2 is a diagram of a prior art memory module.

FIG. 3 shows a preferred embodiment of the present invention for a memory assembly.

FIG. 4 shows a preferred embodiment of the present invention for a memory access controller.

FIG. 5 shows a preferred embodiment of the present invention for a block-address matching unit.

FIG. 6 shows a preferred embodiment of the present invention for a new block address selection unit.

FIG. 7 shows a preferred embodiment of the present invention for a memory status unit.

FIG. 8 shows another preferred embodiment of the present invention for a memory status unit.

FIG. 9 shows a different preferred embodiment of the present invention for a memory status unit.

DETAILED DESCRIPTION OF THE INVENTION

The present invention will be illustrated with some preferred embodiments.

FIG. 1 is a diagram of a prior art memory chip. The memory device 101 contains device data port 102, a device address unit 103, a device control unit 104, and a memory cell array 105. The device data port 102 is connected to the chip data bus 106. The device address unit 103 is connected to the chip address bus 107. The device control unit 104 is connected to the chip control bus 108.

FIG. 2 is a diagram of a prior art memory module. The memory module 201 receives address-control signals on a memory address-control bus 202. The address-control signals select memory data from the memory device 203. The selected memory data is placed on a device data port 204. The memory data further passes through a connection element 205 to reach the memory data bus 206. The combination of a memory device 203 and a connection element 205 constitutes a memory unit. This memory module contains a total of eight memory units.

FIG. 3 shows a preferred embodiment of the present invention for a memory assembly. The memory access control unit 301 is connected to the system memory bus 302.

A memory status unit 303 is connected to the system memory bus 302 and a controller status bus 304. A supporting memory unit 305 is connected to the system memory bus 302 and a controller supporting memory bus 306. A primary memory unit 307 is connected to the system memory bus 302 and two controller primary memory busses 308 and 309. The primary memory unit 307 is the main storage for the memory assembly. The supporting memory unit 305 contains memory blocks that are used as mirrored buffer storage blocks to reflect the contents of memory blocks in the primary

I memory unit.

Depending on the configuration of the system, the supporting memory unit 307 is used to bridge the memory timing difference between the assembly memory bus and the primary memory unit, or to compensate for defective memory cells in the primary memory unit.

The memory status unit 303 contains a list of memory block description entries for the mirrored memory blocks in the supporting memory unit. A block description entry includes the logical memory block address of corresponding mirrored memory block.

The memory access controller 301 receives address, data, and control signals from the system memory bus. It determines the memory access method according to the contents of the memory status unit 303.

The memory read-write access is then directed to either the supporting memory unit 305, or the primary memory unit 307, or both memory units at the appropriate memory timing cycles.

FIG. 4 shows a preferred embodiment of the present invention for a memory access controller. The memory access controller 401 consists of a timing control unit 402, an address generation unit 403, and a data routing unit 404. In this preferred embodiment, the address generation unit 403 consists of an existing block address matching unit 405 and a new block address selection unit 406.

The address-matching unit 405 receives the memory access address from the assembly address bus 407. It also receives the mirrored logical memory block addresses from the memory status unit 408. The memory access address is compared with the mirrored logical memory block addresses in the address comparators 409 to generate a list of matching condition signals.

These matching condition signals are combined in a logical OR operation to generate a matched condition signal in the existing block address generation unit 410. The matched condition signal indicates whether the requested memory block is currently mirrored in the supporting memory unit.

The matching condition signals are also used to generate the address of the mirrored memory block with an address encoder in the existing block address generation unit 410.

The data routing unit 404 links the assembly data bus to the data signals from either the supporting memory unit, or the primary memory unit, or some temporary registers, at the appropriate timing cycles.

The timing control unit 402 generates the control signals for the supporting memory unit, the primary memory unit, and the memory status unit.

For memory read access request to an existing mirrored memory block, the memory access controller reads the memory data from the corresponding block in the supporting memory unit and routes the data to the assembly memory data bus at the appropriate timing cycles.

For memory write access request to an existing mirrored memory block, the memory access controller writes the memory data to the corresponding block in the supporting memory unit. For updating the memory contents of the corresponding block in the primary memory unit, the memory access controller may initiate a simultaneous or scheduled write access according to a primary memory writing policy.

The memory access controller may use a write-through policy to write back the memory contents to the primary memory unit simultaneously or immediately following the write access to the supporting memory unit.

The memory access controller may also use a replacement writing policy to write back the memory contents to the primary memory unit only when the current mirrored memory block is being replaced by a new mirrored memory block.

The new block address selection unit 406 determines the memory location in the supporting memory unit to place the new memory block. During the initial phase, the available memory block space is not fully occupied. A new memory block is simply placed in the next empty memory block.

After the available memory block space becomes fully occupied, the new block address selection unit must select an existing memory block to replace with the new memory block. The selected memory block to be replaced may be determined using a least- recently-used mechanism or other simplified methods.

FIG. 5 shows a preferred embodiment of the present invention for a block- address matching unit. The block-address matching unit 501 consists of an address comparison unit 502, a matched address logic unit 503, and a matched address encoder 504.

The address comparison unit 502 receives the memory access address from the assembly address bus 505. It also receives the mirrored logical memory block addresses 506 from the memory status unit. The memory access address is compared with the mirrored logical memory block addresses in the address comparators to generate a list of matching condition signals.

In the matched address logic unit 503, matching condition signals are combined in a logical OR operation to generate a matched condition signal. The matched condition signal indicates whether the requested memory block is currently mirrored in the supporting memory unit.

In the matched address encoder 504, matching condition signals are encoded to generate the address of the mirrored memory block. This address is sent to the supporting memory unit at the appropriate timing cycles to perform memory access.

FIG. 6 shows a preferred embodiment of the present invention for a new block address selection unit. The new block address selection unit 601 maintains a memory access stack 602 to keep track of the least-recently-used memory block address.

Each memory access address 603 is compared with the contents of the current stack. The accessed block address is re-positioned to the top of the stack 604, indicating that it is the most-recently-accessed block address.

The bottom of the stack 605 is therefore the least-recently-used memory block address. Whenever a new block is to be placed in the supporting memory unit, this least-recently-used memory block will be replaced. The selection logic unit 606 controls the above selection logic to select a new block address 607.

For special memory block that is required to remain in the supporting memory unit, a special critical block indicator may be used to mark the block as not replaceable. Such a critical memory block will not participate in the new block address selection process using the least-recently-used mechanism.

This critical block retaining method may be used for permanently or temporarily defective memory blocks in the primary memory unit.

FIG. 7 shows a preferred embodiment of the present invention for a memory status unit. The memory status unit 701 contains a list of mirrored logical block address entries 702 and a list of critical block indicators 703.

In this preferred embodiment, mirrored logical blocks 704 and 705 are

marked as critical blocks. Mirrored logical blocks 704 are determined as critical during initialization, and marked accordingly. Mirrored logical block 705 is determined to be critical at a later time, possibly due to change of operational conditions. It is marked as critical at that time.

Instead of using a critical block retaining method, certain memory area in either the supporting memory unit or the primary memory unit may be reserved as an alternative memory area to compensate for defective memory cells in the primary memory unit.

Using this method, the mirrored memory blocks for defective memory blocks are treated as ordinary memory blocks for placement and replacement. However, a memory read-write access to the primary memory unit during a placement or replacement process is directed, in full or in part, to an alternative memory location in the reserved alternative memory area.

The alternative memory location for a particular defective memory block is maintained in the memory status unit.

FIG. 8 shows another preferred embodiment of the present invention for a memory status unit. The memory status unit 801 contains a mirrored logical memory block address list 802 and a defective memory block list 803.

The mirrored logical memory block address list 802 contains a list of mirrored logical memory block address entries 804.

The defective memory block list 803 contains a list of defective memory block entries 805 and a list of corresponding alternative memory location entries 806. A memory access request address is compared with both the mirrored logical memory block address entries 804 and defective memory block entries 805.

For a mirrored memory block, the memory access is directed to the supporting memory unit first. For memory write operations, the updating of the primary memory blocks are handled according to the specified logic sequence.

The read-write accesses to the defective portion of primary memory unit for either mirrored memory or new memory blocks are directed to the alternative memory locations specified in the alternative memory location entries 806.

FIG. 9 shows a different preferred embodiment of the present invention for a memory status unit. The memory status unit 901 contains a combined list of logical memory block entries. Each entry includes a memory block address field 902, an existence flag 903, and an alternative memory location field 904.

A memory access request address is compared with memory block address field 902. The corresponding existence flag 903 indicates that the requested memory block is currently mirrored in the supporting memory unit.

The read- write accesses to the defective portion of primary memory unit for either mirrored memory or new memory blocks are directed to the alternative memory locations specified in the alternative memory location field 904. The setting of the critical memory indicators or the alternative memory locations may be performed by fixed settings, during initialization, or with a failure detection mechanism.

The failure detection mechanism detects permanent or temporary memory failures either in real time or as a separate process.

Upon detection, the memory access controller will update the contents of the memory status unit automatically or with the assistance of other external controlling elements.

During the mirrored block placement or replacement process, the timing control unit may generate separate sets of memory control signals for different primary memory sub-units with different memory type and speed.

The timing control unit may also adjust the memory control signals for the primary memory sub-units according to changes in the operating conditions.

The timing control unit may maintain a set of parameter settings for the memory type, memory speed, and operating conditions.

These functions are performed while retaining the same system level interface. The memory subsystem, as a unit, meets the system-level functional specification.

Claims

CLAIMS: I claim:

1. A memory device, chip, module, or subsystem assembly comprising:

(a) a plurality of assembly memory bus lines for address, data, and control signals;

(b) a first group of at least one primary memory sub-assemblies, each having a plurality of sub-assembly memory bus lines and a plurality of sub-assembly memory cells partitioned into a plurality of sub-assembly memory blocks each containing at least one memory cells;

(c) a second group of at least one supporting memory sub-assemblies, each having a plurality of sub-assembly memory bus lines and a plurality of sub-assembly memory cells partitioned into a plurality of sub-assembly memory blocks each containing at least one memory cells;

(d) a memory status unit;

(e) a memory access controller; wherein the primary memory sub-assemblies contain at least one sub-assembly that has one or more permanently or temporarily defective memory cells; wherein the supporting memory sub-assemblies contain memory blocks that are used as mirrored buffer storage blocks to reflect the contents of functional or defective memory blocks in the primary memory sub-assemblies; wherein said memory status unit contains a plurality of mirrored memory block description entries, each having a logical memory block address field to specify the logical block address in the primary memory sub-assemblies for a mirrored buffer storage block; wherein said memory status unit also contains a plurality of memory block status indicators to indicate whether a logical memory block in the primary memory sub- assemblies is functional or defective; wherein said memory access controller determines whether a memory access request on the assembly memory bus is mirror-reflected in the supporting memory sub-assemblies according to the logical memory address fields in the mirrored memory block description entries; wherein said memory access controller, in response to a mirrored memory access request, controls the appropriate timing for an immediate read-write access to the supporting memory sub-assemblies, and for an optional simultaneous or scheduled write access to update the contents of the mirrored memory block in the primary memory sub-assemblies; wherein said memory access controller, in response to an un-mirrored memory read access, controls the appropriate timing for an immediate read access to the primary memory sub-assemblies, and for an optional creation of a new mirrored memory block in the supporting memory sub-assembly which includes the updating of mirrored memory description entries in the memory status unit; wherein said memory access controller, in response to an un-mirrored memory write access, controls the appropriate timing for either an immediate write access to the primary memory sub-assemblies or for an optional creation of a new mirrored memory block in the supporting memory subassembly which includes the updating of mirrored memory description entries in the memory status unit; wherein said memory access controller, when creating a new mirrored memory block, may optionally replace an existing mirrored memory block and update the mirrored memory block description entries and, if necessary, the memory contents in the primary memoiy sub-assemblies accordingly; wherein said memory access controller, for defective memory blocks in the primary memory sub-assemblies, retains the mirrored memory blocks in the supporting memory sub-assemblies so that these blocks will not be replaced by new mirrored memory blocks.

2. The memory assembly of claim 1, wherein the contents of the memory status unit is a set of fixed or variable settings, which is a set of metal contacts, jumpers, resistors, logic bits, programmable storage cells controlled by internal or external control signals, or a combination of the above items.

3. The memory assembly of claim 1, wherein some or all of the supporting memory sub-assemblies are embedded within the same device, chip, or module sub-assembly as the memory access controller or the memory status unit.

4. The memory assembly of claim 1, further comprising a failure detection mechanism, which detects permanent or temporary memory failures either in real time or as a separate process.

5. The memory assembly of claim 1, wherein the memory access controller generates separate sets of memory control signals for different primary memory sub-assemblies with different memory characteristics.

6. A memory device, chip, module, or subsystem assembly comprising:

(d) a memory status unit;

(e) a memory access controller; wherein the primary memory sub-assemblies contain at least one sub-assembly that has one or more permanently or temporarily defective memory cells; wherein the supporting memory sub-assemblies contain memory blocks that are used as mirrored buffer storage blocks to reflect the contents of functional or defective memory blocks in the primary memory sub-assemblies; wherein said memory status unit contains a plurality of mirrored memory block description entries, each having a logical memory block address field to specify the logical block address in the primary memory sub-assemblies for a mirrored buffer storage block; wherein said memory status unit further contains a plurality of defective memory block description entries, each having a physical memory location field to specify an alternative physical memory location in either the primary memory sub- assemblies or the supporting memory sub-assemblies to replace the full or partial address range or data segment of the defective logical memory block in the primary memory sub-assemblies; wherein said memory access controller determines whether a memory access request on the assembly memory bus is mirror-reflected in the supporting memory sub-assemblies according to the logical memory address fields in the mirrored memory block description entries; wherein said memory access controller, in response to a mirrored memory access request, controls the appropriate timing for an immediate read-write access to the supporting memory sub-assemblies, and for an optional simultaneous or scheduled write access to update the contents of the mirrored memory block in the primary memory sub-assemblies; wherein said memory access controller, in response to an un-mirrored memory read access, controls the appropriate timing for an immediate read access to the primary memory sub-assemblies, and for an optional creation of a new mirrored memory block in the supporting memory sub-assembly which includes the updating of mirrored memory description entries in the memory status unit; wherein said memory access controller, in response to an un-mirrored memory write access, controls the appropriate timing for either an immediate write access to the primary memory sub-assemblies or for an optional creation of a new mirrored memory block in the supporting memory subassembly which includes the updating of mirrored memory description entries in the memory status unit; wherein said memory access controller, when creating a new mirrored memory block, may optionally replace an existing mirrored memory block and update the mirrored memory block description entries and, if necessary, the memory contents in the primary memory sub-assemblies accordingly; wherein said memory access controller, for memory read-write access to the defective memory blocks in the primary memory sub-assemblies, directs the read- write access for the full or partial address range or data segment of the defective block to the alternative physical memory location as specified in the memory status unit, while optionally directing the read-write access for the remaining non- defective portion, if any, to the logical block address of the primary memory sub- assemblies.

7. The memory assembly of claim 6, wherein the contents of the memory status unit is a set of fixed or variable settings, which is a set of metal contacts, jumpers, resistors, logic bits, programmable storage cells controlled by internal or external control signals, or a combination of the above items.

8. The memory assembly of claim 6, wherein some or all of the supporting memory sub-assemblies are embedded within the same device, chip or module subassembly as the memory access controller or the memory status unit.

9. The memory assembly of claim 6, further comprising a failure detection mechanism, which detects permanent or temporary memory failures either in real time or as a separate process.

10. The memory assembly of claim 6, wherein the memory access controller generates separate sets of memory control signals for different primary memory sub-assemblies with different memory characteristics.

11. A memory device, chip, module, or subsystem assembly comprising:

(d) a memory status unit;

(e) a memory access controller; wherein the supporting memory sub-assemblies contain memory blocks that are used as mirrored buffer storage blocks to reflect the contents of memory blocks in the primary memory sub-assemblies; wherein said memory status unit contains a plurality of mirrored memory block description entries, each having a logical memory block address field to specify the logical block address in the primary memory sub-assemblies for a mirrored buffer storage block; wherein said memory access controller determines whether a memory access request on the assembly memory bus is mirror-reflected in the supporting memory sub-assemblies according to the logical memory address fields in the mirrored memory block description entries; wherein said memory access controller, in response to a mirrored memory access request, controls the appropriate timing for an immediate read-write access to the supporting memory sub-assemblies, and for an optional simultaneous or scheduled write access to update the contents of the mirrored memory block in the primary memory sub-assemblies; wherein said memory access controller, in response to an un-mirrored memory read access, controls the appropriate timing for an immediate read access to the primary memory sub-assemblies, and for an optional creation of a new mirrored memory block in the supporting memory sub-assembly which includes the updating of mirrored memory description entries in the memory status unit; wherein said memory access controller, in response to an un-mirrored memory write access, controls the appropriate timing for either an immediate write access to the primary memory sub-assemblies or for an optional creation of a new mirrored memory block in the supporting memory subassembly which includes the updating of mirrored memory description entries in the memory status unit; wherein said memory access controller, when creating a new mirrored memory block, may optionally replace an existing mirrored memory block and update the mirrored memory block description entries and, if necessary, the memory contents in the primary memory sub-assemblies accordingly; wherein said memory access controller, for critical memory blocks in the primary memory sub-assemblies, retains the mirrored memory blocks in the supporting memory sub-assemblies so that these blocks will not be replaced by new mirrored memory blocks.

12. The memory assembly of claim 11, wherein the contents of the memory status unit is a set of fixed or variable settings, which is a set of metal contacts, jumpers, resistors, logic bits, programmable storage cells controlled by internal or external control signals, or a combination of the above items.

13. The memory assembly of claim 11, wherein some or all of the supporting memory sub-assemblies are embedded within the same device, chip or module subassembly as the memory access controller or the memory status unit.

14. The memory assembly of claim 11, wherein the memory access controller generates separate sets of memory control signals for different primary memory sub-assemblies with different memory characteristics.

15. A memory device, chip, module, or subsystem assembly comprising:

(c) a memory status unit;

(d) a memory access controller; wherein the primary memory sub-assemblies contain at least one sub-assembly that has one or more permanently or temporarily defective memory cells; wherein said memory status unit contains a plurality of defective memory block description entries, each having a defective logical memory address field and a physical memory location field to specify an alternative physical memory location in either the primary memory sub-assemblies or an external supporting memory unit to replace the full or partial address range or data segment of the defective logical memory block; wherein said memory access controller determines whether a memory access request on the assembly memory bus is to a defective memory block according to the defective logical memory address fields in the defective memory block description entries; wherein said memory access controller, for memory read-write access to the defective memory blocks in the primary memory sub-assemblies, directs the read- write access for the full or partial address range or data segment of the defective block to the alternative physical memory location in either the primary memory sub-assemblies or an external supporting memory unit as specified in the memory status unit, while optionally directing the read-write access for the remaining non- defective portion, if any, to the logical block address of the primary memory sub- assemblies.

16. The memory assembly of claim 15, wherein the contents of the memory status unit is a set of fixed or variable settings, which is a set of metal contacts, jumpers, resistors, logic bits, programmable storage cells controlled by internal or external control signals, or a combination of the above items.

17. The memory assembly of claim 15, further comprising a second group of at least one supporting memory sub-assemblies to be used as alternative memory locations for defective memory blocks, wherein some or all of the supporting memory sub-assemblies may be embedded within the same device, chip or module sub-assembly as the memory access controller or the memory status unit.

18. The memory assembly of claim 15, further comprising a failure detection mechanism, which detects permanent or temporary memory failures either in real time or as a separate process.

19. A memory device, chip, module, or subsystem assembly comprising:

(e) a plurality of assembly memory bus lines for address, data, and control signals;

(f) a group of at least one primary memory sub-assemblies, each having a plurality of sub-assembly memory bus lines and a plurality of sub-assembly memory cells partitioned into a plurality of sub-assembly memory blocks each containing at least one memory cells;

(g) a memory status unit;

(h) a memory access controller; wherein the primary memory sub-assemblies contain at least one sub-assembly that has one or more permanently or temporarily defective memory cells; wherein said memory status unit contains a plurality of memory block description entries, each having a physical memory location field to specify an alternative physical memory location in either the primary memory sub-assemblies or an external supporting memory unit to replace the full or partial address range or data segment of a logical memory block; wherein said memory access controller, for a memory read-write access to a memory block in the primary memory sub-assemblies, directs the read-write access for the full or partial address range or data segment of the memory block to the alternative physical memory location in either the primary memory sub-assemblies or an external supporting memory unit as specified in the memory status unit, while optionally directing the read-write access for the remaining portion, if any, to the logical block address of the primaiy memory sub-assemblies.