WO2002021694A3 - Tileable field-programmable gate array architecture - Google Patents

Tileable field-programmable gate array architecture Download PDF

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Publication number
WO2002021694A3
WO2002021694A3 PCT/US2001/027172 US0127172W WO0221694A3 WO 2002021694 A3 WO2002021694 A3 WO 2002021694A3 US 0127172 W US0127172 W US 0127172W WO 0221694 A3 WO0221694 A3 WO 0221694A3
Authority
WO
WIPO (PCT)
Prior art keywords
regular
fgs
fpga
programmable gate
gate array
Prior art date
Application number
PCT/US2001/027172
Other languages
French (fr)
Other versions
WO2002021694A2 (en
Inventor
Fran Lien
Original Assignee
Actel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Actel Corp filed Critical Actel Corp
Priority to AU2001286979A priority Critical patent/AU2001286979A1/en
Priority to JP2002525998A priority patent/JP2004524715A/en
Priority to EP01966470A priority patent/EP1354404B1/en
Priority to DE60128960T priority patent/DE60128960T2/en
Publication of WO2002021694A2 publication Critical patent/WO2002021694A2/en
Publication of WO2002021694A3 publication Critical patent/WO2002021694A3/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
    • G06F30/347—Physical level, e.g. placement or routing
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17724—Structural details of logic blocks
    • H03K19/17732—Macroblocks
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/394—Routing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/394—Routing
    • G06F30/3947—Routing global
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17736—Structural details of routing resources
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/1778—Structural details for adapting physical parameters
    • H03K19/17796—Structural details for adapting physical parameters for physical disposition of blocks

Abstract

An apparatus includes a field-programmable gate array (FPGA). The FPGA includes a first FPGA tile, and the first FPGA tile includes a plurality of functional groups (FGs), a regular routing structure, and a plurality of interface groups (IGs). The plurality of FGs are arranged in rows and columns with each of the FGs being configured to receive regular input signals, perform a logic operation, and generate regular output signals. The regular routing structure is coupled to the FGs and configured to receive the regular output signals, route signals within the first FPGA tile, and provide the regular input signals to the FGs. The plurality of IGs surround the plurality of FGs such that one IG is positioned at each end of each row and column. Each of the IGs is coupled to the regular routing structure and configured to transfer signals from the regular routing structure to outside of the first FPGA tile.
PCT/US2001/027172 2000-09-02 2001-08-31 Tileable field-programmable gate array architecture WO2002021694A2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
AU2001286979A AU2001286979A1 (en) 2000-09-02 2001-08-31 Tileable field-programmable gate array architecture
JP2002525998A JP2004524715A (en) 2000-09-02 2001-08-31 Tileable Field Programmable Gate Array Architecture
EP01966470A EP1354404B1 (en) 2000-09-02 2001-08-31 Tileable field-programmable gate array architecture
DE60128960T DE60128960T2 (en) 2000-09-02 2001-08-31 ARCHITECTURE FOR TILTING BUILT-ON USER PROGRAMMABLE GATE FRAME

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/654,240 2000-09-02
US09/654,240 US6476636B1 (en) 2000-09-02 2000-09-02 Tileable field-programmable gate array architecture

Publications (2)

Publication Number Publication Date
WO2002021694A2 WO2002021694A2 (en) 2002-03-14
WO2002021694A3 true WO2002021694A3 (en) 2003-08-14

Family

ID=24624042

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2001/027172 WO2002021694A2 (en) 2000-09-02 2001-08-31 Tileable field-programmable gate array architecture

Country Status (6)

Country Link
US (11) US6476636B1 (en)
EP (1) EP1354404B1 (en)
JP (1) JP2004524715A (en)
AU (1) AU2001286979A1 (en)
DE (1) DE60128960T2 (en)
WO (1) WO2002021694A2 (en)

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