WO2002023203A1

WO2002023203A1 - Electronic device test socket

Info

Publication number: WO2002023203A1
Application number: PCT/US2001/041451
Authority: WO
Inventors: Mark S. Lewis; Simon Wood; Ron Burke
Original assignee: Raytheon Company
Priority date: 2000-09-14
Filing date: 2001-07-27
Publication date: 2002-03-21

Abstract

An electronic device test socket including a floor, a number of walls upstanding from the floor defining an oversized cavity therebetween such that any burrs extending from the device fit within the oversize cavity, and a number of alignment keys, each key extending inwardly from a wall to be received in a castellation in the device for aligning the device within the oversize cavity.

Description

ELECTRONIC DEVICE TEST SOCKET

FIELD OF THE INVENTION This invention relates to an electronic device test socket for leadless chip carriers, other surface mount devices, and other electronic device packages.

BACKGROUND OF THE INVENTION

Leadless chip carriers (LCCs) which include a chip (for example a power amplifier) mounted on a substrate, other surface mount devices, and other electronic device packages are routinely tested during assembly by placing them in test socket which resides on a test fixture mounted on a test board in a tester such as a model HP84000 Series RFIC tester connected to a computer-based "auto tester", for example, the RFIC auto tester.

A robotic handler such as the "Advantek" model M-1000T automatically feeds the LCCs into the tester whereupon individual LCCs are placed in the test socket for a short duration (e.g., 3 second) electrical test.

The cavity of the test socket typically is just large enough to accommodate an LCC so that the electrical contacts of the LCC correctly align with the electrical contacts of the test socket. This is problematic as explained next.

The substrate of a typical LCC is made of a ceramic material and, when the LCCs are manufactured, an array of many chips are deposited on a continuous ceramic sheet.

Then, a score is made in the ceramic substrate between the individual chips so that each individual LCC can be separated from the array.

During this process, it is often the case that one or more burrs are formed on each LCC extending outwardly from the substrate by as much as 6 mils.

When the device is then robotically placed in the test socket, because of the close fit between the perimeter of the LCC and the walls of the test socket cavity, the burr or burrs often break off.

The result is that the burr or burrs stay in the test socket and, when the next LCC is placed in the test socket, the proper electrical connections between the LCC and the test socket are not made causing the device to fail the electrical test even though the device is electrically sound.

Since LCCs are loaded into the test socket at a rate of up to 30 LCCs per minute, many devices can fail before test personnel note the poor yield condition, troubleshoot the test equipment, and then clear the test socket of any debris. All the "failed" devices must then be retested.

In other cases, the existence of a burr can damage the test socket resulting in expensive down time of the test equipment. In still other cases, a burr will cause an LCC to be misaligned in the test socket preventing a proper electrical connection between the LCC and the test socket again resulting in false negative test results.

BRIEF SUMMARY OF THE INVENTION It is therefore an object of this invention to provide an electrical device test socket with an oversized cavity which accommodates any burrs extending from the device.

It is a further object of this invention to provide such a test socket which eliminates false negative test results in the testing of LCC packaged devices and other electronic device packages. It is a further object of this invention to provide such a test socket which provides for automatic alignment of the LCC within the test socket.

This invention results from the realization that when the cavity of a prior art test socket was made just large enough to accommodate an LCC, burrs on the LCC resulted in expensive test equipment downtime and false negative test results and that this problem can be solved by fashioning an oversized test socket cavity- a solution which, however, can result in a misalignment of the LCC in the test socket again contributing to false negative test results and this consequence of the oversized cavity can be solved by the addition of alignment keys to the test socket which correctly align the LCC in the oversized test socket cavity and thus, in this way, the burrs do not break off the LCC and yet, at the same time, the LCC is always correctly positioned in the test socket.

This invention results from the further realization that the castellations inherent in the LCC can be used in conjunction with the alignment keys to correctly position the LCC in the test socket since burrs never form within the castellations.

This invention features an electronic device test socket comprising a floor; a number of walls upstanding from the floor defining an oversized cavity therebetween such that any burrs extending from the device fit within the oversized cavity; and a plurality of alignment keys, each key extending inwardly from a wall to be received in a castellation in the device for aligning the device within the oversized cavity.

Preferably, at least two of the alignment keys diametrically oppose each other and there may be one or two alignment keys per wall. In one embodiment, each alignment key has a downwardly sloping top face for grossly aligning the device package in the oversized cavity. The downwardly sloping top face also preferably tapers inwardly forming a wedge to provide fine alignment of the device package in the test socket. Alignment keys of other shapes and configurations may also be used.

The walls and the floor of the test socket may be continuous or discontinuous depending on the configuration of the device package, the test socket, and the associated test equipment.

An electronic device package test socket in accordance with this invention includes an oversized cavity which accommodate any defects extending from the device package and means for aligning the electronic device package within the oversized cavity. The means for aligning the electronic device package in the oversized cavity typically includes a plurality of alignment keys extending inwardly into the oversized cavity.

BRIEF DESCRIPTION OF THE DRAWINGS

Fig. 1 is a schematic view of the test equipment typically associated with testing LCCs;

Fig. 2 is a top view of a typical test socket mounted on a test fixture which is used in connection with the test equipment shown in Fig.l;

Fig. 3 is a schematic view of a typical LCC packaged device;

Fig. 4 is a top view of the LCC of Fig. 3 mounted in a test socket showing the problem associated with positioning an LCC with a burr in a prior art test socket;

Fig. 5 is a top view showing the same LCC with a burr received in the oversized cavity test socket of the subject invention;

Fig. 6 is a schematic three dimensional view of the test socket shown in Fig. 5;

Fig. 7 is a schematic three dimensional view of a preferred embodiment of a test socket with an oversized cavity in accordance with the subject invention; Fig. 8 is a top view of the test socket shown in Fig. 7; and Fig. 9 is a bottom view of the test socket shown in Figs. 7 and 8.

DETAILED SPECIFICATION

As discussed in the "Background" section above, LCCs are routinely tested before shipment or incorporation into a product by placing them in test socket 12, Fig. 1 which resides on text fixture 14 mounted on test board 16 in tester 18 connected to auto tester 20. Robotic handler 22 receives trays 24 and 26 of individual LCCs 28 and places them one at a time into test socket 12 for a short duration (e.g., 3 second) electrical test.

Fig. 2 is a top view of a typical test fixture 14 with test socket 12 mounted thereon receiving LCC 28 which is also shown in Fig. 3. LCC 28, Fig. 3, includes chip 30 mounted on ceramic substrate 32 with castellations 34 and problematic burr 36.

As shown in Fig. 4, prior art test socket 12 includes floor 40 and four discontinuous walls 42, 44, 46, and 48 upstanding from floor 40 defining a cavity therebetween which is just large enough to receive substrate 32 of LCC 28 but not burr 36.

The result, in the prior art, was that burr 36 tended to break off substrate 32 and then, when the next LCC is placed in test socket 12, a proper the electrical connection between the LCC and the test socket is not made causing the LCC to fail the electrical test even though the LCC may be electrically sound. Since LCCs are loaded into the test socket at a rate of up to 30 LCCs per minute, many LCCs can fail before test personnel notice the poor yield condition. Test personnel must then troubleshoot the test equipment, clear the test socket of any burrs, and then retest the improperly failed LCCs.

In other cases, the existence of burr 36 damages test socket 12 resulting in expensive down time of the test equipment. In still other cases, burr 36 causes the LCC to be misaligned in test socket 12 preventing the establishment of the proper electrical contacts between the LCC and the test socket, again resulting in false negative test results.

In the subject invention, in contrast, test socket 50, Figs. 5-6 has an oversized cavity between walls 52, 54, 56, and 58 upstanding from floor 60 which accommodates burr 36 extending from substrate 32.

In this way, burr 36 does not break off and then are no improper failures of LCCs when test socket 50 is used in tester 18, Fig. 1, nor is test socket 50 damaged.

Because of the oversized cavity (the area between walls 52, 54, 56, and 58), however, the electrical contacts on the bottom of the LCC and the electrical contacts on floor 60 of test socket 50 may not properly align. Thus, in this invention, alignment keys 70, typically one or two per wall, are included to extend inwardly from walls 52, 54, 56, and 58 as shown. Keys 70 fit in castellations 34 in ceramic substrate 32, Fig. 5, and properly align the LCC in the oversized test socket cavity.

It was discovered by the inventors that burr's never occur proximate the castellations and thus there are no burrs on the LCC which would interfere with the action of alignment keys 70 properly interlocking with the respective castellations 34 to thus accurately position the LCC in the oversized cavity of the test socket.

In the preferred embodiment, test socket 80, Figs. 7-9 has four continuous walls 82, 84, 86, and 88 and one or two alignment keys 90 per wall, typically with at least two alignment keys diametrically opposing each other as shown in Fig. 8. Floor 92 is discontinuous as shown in this example to receive a gold plated plug (not shown). Electrical contacts (not shown) reside in orifice 94. Structures 96 at the corners of the test socket receive fasteners used to mount the test socket to a test fixture.

Each alignment key 90 preferably has a downwardly sloping top face 98 for grossly aligning the LCC in the oversize cavity: as the LCC is robotically placed above the test socket, the downward slope of face 98 urges the LCC downward towards floor 92. For fine alignment, face 98 of each alignment key tapers inwardly as shown forming a wedge 100 which resides in the castellations of the LCC.

In this way, the cavity of the test socket is oversized to accommodate burrs and the alignment keys correctly align the LCC in the oversize test socket cavity so that the burrs do not break off the LCC and yet, at the same time, the LCC is always correctly positioned in the test socket.

The alignment keys, however, need not be shaped as shown in Figs. 7-9 and good results may be realized with the key shape shown in Figs. 5 and 6. Therefore, the shape of the alignment keys will depend to some extent on the specific design of the electronic device package and the test equipment used in connection with testing the electronic device package. Moreover, walls 82, 84, 86, and 88 as shown in Fig. 7 may be continuous or discontinuous (see Fig. 6) depending on the LCC and the handler subsystem. Furthermore, floor 92 may be discontinuous as shown in Fig. 7 or continuous as shown in Fig. 6.

Moreover, although the figures hereof describe a typical LCC, test socket 50, Figs. 5 and 6 and/or test socket 80, Fig. 7-9 may be configured for other LCCs, other surface mount devices, and other electronic device packages in which burrs or other defects are a problem.

In the embodiment shown in Fig. 7, floor 92 is square, .342 square inches in area to accommodate burrs 6 mils long on each side of a .330 square inch LCC. In the prior art, the clearance between the edge of the LCC and each wall of the test socket was 2 mils and thus not even a single burr longer than two mils on the LCC could be accommodated. A study of typical burrs by the inventors reveals that they are usually between 2 to 4 mils long and occasionally as long as 6 mils. Thus, the oversized test socket cavity is made large enough to accommodate two diametrically opposing 6 mil burrs. All of the above dimensions, however, are based on the size of the LCC to be tested, the manufacturer's practices and product and production history, and the prevalence and size of the majority of the burrs.

In general, if A=(LxW) is the area of the ceramic substrate of the LCC in square inches, the area of the oversized cavity of the test socket is (L+1.2") x (W+1.2"). In the prior art, the area of the cavity was (L+.4") x (W+.4").

Although specific features of the invention are shown in some drawings and not in others, this is for convenience only as each feature may be combined with any or all of the other features in accordance with the invention.

Other embodiments will occur to those skilled in the art and are within the following claims:

What is claimed is:

Claims

1. An electronic device test socket comprising: a floor; a number of walls upstanding from the floor defining an oversized cavity therebetween such that burrs extending from the device fit within the oversized cavity; and a plurality of alignment keys, each key extending inwardly from a wall to be received in a castellation in the device for aligning the device within the oversized cavity.

2. The test socket of claim 1 in which at least two of the alignment keys oppose each other.

3. The test socket of claim 1 in which each alignment key has a downwardly sloping face for grossly aligning the device in the oversized cavity.

4. The test socket of claim 3 in which the downwardly sloping face tapers inwardly forming a wedge to provide fine alignment of the device in the test socket cavity.

5. The test socket of claim 1 in which each wall has a key.

6. The test socket of claim 1 in which each wall is discontinuous.

7. The test socket of claim 1 in which each wall is continuous.

8. The test socket of claim 1 in which the floor is discontinuous.

9. The test socket of claim 1 in which the floor is continuous.

10. An electronic device test socket comprising: an oversized cavity which accommodate any defects extending from the device; and means for aligning the electronic device within the oversized cavity.

11. The electronic device package test socket of claim 10 in which the means for aligning the electronic device in the oversized cavity includes a plurality of alignment keys.