WO2002025819A1 - An apparatus for active high speed - low power analog voltage drive - Google Patents

An apparatus for active high speed - low power analog voltage drive Download PDF

Info

Publication number
WO2002025819A1
WO2002025819A1 PCT/US2001/029299 US0129299W WO0225819A1 WO 2002025819 A1 WO2002025819 A1 WO 2002025819A1 US 0129299 W US0129299 W US 0129299W WO 0225819 A1 WO0225819 A1 WO 0225819A1
Authority
WO
WIPO (PCT)
Prior art keywords
channel transistor
receive
operatively connected
voltage
drain
Prior art date
Application number
PCT/US2001/029299
Other languages
French (fr)
Inventor
Richard L. Hull
Randy L. Yach
Kent D. Hewitt
Original Assignee
Microchip Technology Incorporated
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Microchip Technology Incorporated filed Critical Microchip Technology Incorporated
Priority to AU2001291119A priority Critical patent/AU2001291119A1/en
Publication of WO2002025819A1 publication Critical patent/WO2002025819A1/en

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • H03K19/018521—Interface arrangements of complementary type, e.g. CMOS
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/30—Single-ended push-pull [SEPP] amplifiers; Phase-splitters therefor
    • H03F3/3001—Single-ended push-pull [SEPP] amplifiers; Phase-splitters therefor with field-effect transistors
    • H03F3/301—CMOS common drain output SEPP amplifiers
    • H03F3/3016—CMOS common drain output SEPP amplifiers with symmetrical driving of the end stage
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • H03K19/01855—Interface arrangements synchronous, i.e. using clock signals

Definitions

  • the present invention relates to voltage drive methods and circuits, and more particularly to a high speed, low power method and circuit for driving a desired voltage signal.
  • Figure 1 schematically illustrates one simple approach.
  • a reference voltage V REF is applied to a unity gain amplifier.
  • This approach has several drawbacks.
  • the effective resistance R of the operational amplifier draws current from V DD , thus dissipating power. If the effective resistance R is increased to reduce power consumption, than the output current is limited. This slows the responsiveness of the circuit.
  • the Figure 1 circuit typically occupies a relatively large chip area.
  • FIG. 2A schematically illustrates a precharged voltage driver circuit.
  • V PRE voltage
  • the node R is precharged to V DD through P- channel device TI .
  • the n-channel device T3 is turned off during this time.
  • V PRE goes high
  • device TI turns off and device T3 turns on causing node R to be pulled to V REF + V P ofT2..
  • the Figure 2A circuit precharges node R without active drive of the output at node R when V P E is high. Consequently, this circuit does not compensate for current draws out of a complacent load schematically illustrated as C Figures 2A. This causes the output voltage at node R to slowly drift down as indicted by the dash line in Figure 2B.
  • the present invention provides a voltage drive circuit that is operatively connectable to receive first and second supply voltages and a reference voltage.
  • the circuit comprises: a first n-channel transistor having a source operatively connected to receive the first supply voltage, a gate operatively connected to receive the reference voltage and a drain; and a first p-channel transistor having a source operatively connected to the drain of the first n-channel transistor, a drain operatively connected to receive the second supply voltage and a gate operatively connected to receive the reference voltage.
  • Figure 1 schematically illustrates a conventional voltage driver circuit.
  • Figure 2A schematically illustrates a precharged voltage driver circuit.
  • Figure 2B depicts wave forms of voltages in the Figure 2 A circuit.
  • FIG 3 is a schematic diagram of a voltage driver circuit embodying the present invention.
  • Figure 4 is a schematic diagram of another voltage driver circuit embodying the present invention.
  • Figure 5 is a schematic diagram of a reference voltage circuit that can be employed in drive circuits embodying the present invention.
  • Figure 3 is schematic diagram of a voltage drive circuit of the present invention.
  • the Figure 3 circuit actively drives the voltage Vo to a value in the range of V REF + V T p to V REF - V TN ; where V TN and VTP effectively are the threshold voltages of the n-channel device TI and the p-channel device T2. If Vo falls below V REF - V TN then TI turns on to drive Vo towards V REF until Vo ⁇ V R EF- VT N • For output voltages varying in the other direction, if Vo rises above VREF +VTP , then T2 turns on to drive Vo towards V RE F until Vo ⁇ VREF + V TP .
  • the Figure 3 circuit actively holds the output voltage Vo to within V REF + V TP and V REF - V TN without the necessity of bleeding current from the output. Also, because it needs only two transistors, it occupies a relatively small amount of chip area.
  • Figure 4 is a schematic diagram of another voltage drive circuit embodying the present invention.
  • the Figure 4 circuit adds a clock circuit to the Figure 3 embodiment.
  • the clock circuit includes p-channel device T3, n-channel device T4 and inverter II.
  • An advantage of the Figure 4 circuit over the Figure 3 circuit is that it can be used with multiple circuits of the type of Figure 4 to drive multiple voltage valves at different times. It is also an improvement over prior art of Figure 2 A because the degradation of Figure 2B is eliminated.
  • the Figure 4 circuit operates as does the Figure 3 circuit except that the active drive of the output is limited by the clock signal.
  • active drive occurs during a positive clock cycle.
  • both T3 and T4 are turned on; thus, coupling the pull-up path through T3 and the pull-down path through T4.
  • FIG. 5 is a schematic diagram of a reference voltage circuit that can be used in drive circuits embodying the present invention.
  • This circuit holds the output substantially at V EF •
  • the circuit uses the current limiting resistors Ri, and R 2 , it draws small amounts of current from V REF - This is unlike the circuits in Figures 3 and 4 where there is no load on V R E F - Transistors TI and T2 shown in Figure 4.
  • the speed of operation of Figure 5 is set by the size of transistors TI and T2, increasing the speed of the circuit will not change the DC current consumption of the circuit. DC current consumption is fixed only to that flowing through R ⁇ and R 2 .

Abstract

A high speed low power and active drive circuit that includes an n-channel transistor and a p-channel transistor serially connected between a positive and a negative supply voltage respectively, and having their respective gates driven by a reference voltage. A voltage drive circuit can also include a clock circuit serially connected between the n-channel transistor and the p-channel transistor and the positive and negative supply voltages.

Description

AN APPARATUS FOR ACTIVE HIGH SPEED - LOW POWER ANALOG VOLTAGE DRIVE
BACKGROUND OF THE INVENTION
The present invention relates to voltage drive methods and circuits, and more particularly to a high speed, low power method and circuit for driving a desired voltage signal. There are many approaches to providing a desired voltage. Figure 1 schematically illustrates one simple approach. In Figure 1 a reference voltage VREF , is applied to a unity gain amplifier. This approach has several drawbacks. First, the effective resistance R of the operational amplifier draws current from VDD , thus dissipating power. If the effective resistance R is increased to reduce power consumption, than the output current is limited. This slows the responsiveness of the circuit. In addition, the Figure 1 circuit typically occupies a relatively large chip area.
Figure 2A schematically illustrates a precharged voltage driver circuit. Referring to Figures 2A and 2B, when the voltage VPRE is low, the node R is precharged to VDD through P- channel device TI . The n-channel device T3 is turned off during this time. When VPRE goes high, device TI turns off and device T3 turns on causing node R to be pulled to VREF + V P ofT2..
The Figure 2A circuit precharges node R without active drive of the output at node R when VP E is high. Consequently, this circuit does not compensate for current draws out of a complacent load schematically illustrated as C Figures 2A. This causes the output voltage at node R to slowly drift down as indicted by the dash line in Figure 2B.
SUMMARY OF THE INVENTION
It is an object of the present to provide an apparatus for active drive of an output voltage. It is another object of the present invention to provide an apparatus for low power drive of an output voltage.
It is a further object of the present invention to provide an apparatus for low power drive of an output voltage occupying a small chip area.
It is still another object of the present invention to provide an apparatus for high speed drive of an output voltage.
It is still a further object of the present invention to provide an apparatus for active drive of an output voltage towards a high level or towards a low level as needed.
To achieve the above and other objects, the present invention provides a voltage drive circuit that is operatively connectable to receive first and second supply voltages and a reference voltage. The circuit comprises: a first n-channel transistor having a source operatively connected to receive the first supply voltage, a gate operatively connected to receive the reference voltage and a drain; and a first p-channel transistor having a source operatively connected to the drain of the first n-channel transistor, a drain operatively connected to receive the second supply voltage and a gate operatively connected to receive the reference voltage.
BRIEF DESCRIPTION OF THE DRAWINGS
Figure 1 schematically illustrates a conventional voltage driver circuit.
Figure 2A schematically illustrates a precharged voltage driver circuit.
Figure 2B depicts wave forms of voltages in the Figure 2 A circuit.
Figure 3 is a schematic diagram of a voltage driver circuit embodying the present invention. Figure 4 is a schematic diagram of another voltage driver circuit embodying the present invention.
Figure 5 is a schematic diagram of a reference voltage circuit that can be employed in drive circuits embodying the present invention.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
Figure 3 is schematic diagram of a voltage drive circuit of the present invention. The Figure 3 circuit actively drives the voltage Vo to a value in the range of VREF + VTp to VREF - VTN; where VTN and VTP effectively are the threshold voltages of the n-channel device TI and the p-channel device T2. If Vo falls below VREF - VTN then TI turns on to drive Vo towards VREF until Vo ~ VREF- VTN • For output voltages varying in the other direction, if Vo rises above VREF +VTP , then T2 turns on to drive Vo towards VREF until Vo ~ VREF + VTP . Thus, the Figure 3 circuit actively holds the output voltage Vo to within VREF + VTP and VREF - VTN without the necessity of bleeding current from the output. Also, because it needs only two transistors, it occupies a relatively small amount of chip area.
Figure 4 is a schematic diagram of another voltage drive circuit embodying the present invention. The Figure 4 circuit adds a clock circuit to the Figure 3 embodiment. The clock circuit includes p-channel device T3, n-channel device T4 and inverter II. An advantage of the Figure 4 circuit over the Figure 3 circuit is that it can be used with multiple circuits of the type of Figure 4 to drive multiple voltage valves at different times. It is also an improvement over prior art of Figure 2 A because the degradation of Figure 2B is eliminated.
The Figure 4 circuit operates as does the Figure 3 circuit except that the active drive of the output is limited by the clock signal. In the example shown in Figure 4, active drive occurs during a positive clock cycle. During this time, both T3 and T4 are turned on; thus, coupling the pull-up path through T3 and the pull-down path through T4.
Figure 5 is a schematic diagram of a reference voltage circuit that can be used in drive circuits embodying the present invention. This circuit provides two reference voltages VREFI = VREF + VTN and VREF2 = VREF - VTP. This circuit holds the output substantially at V EF • However, because the circuit uses the current limiting resistors Ri, and R2, it draws small amounts of current from VREF- This is unlike the circuits in Figures 3 and 4 where there is no load on VREF- Transistors TI and T2 shown in Figure 4. The speed of operation of Figure 5 is set by the size of transistors TI and T2, increasing the speed of the circuit will not change the DC current consumption of the circuit. DC current consumption is fixed only to that flowing through R\ and R2.

Claims

ClaimsWe claim:
1. A voltage drive circuit operatively connectable to receive first and second supply voltages and a reference voltage, comprising: first n-channel transistor having a source operatively connected to receive the first supply voltage, a gate operatively connected to receive the reference voltage and a drain; and a first p-channel transistor having a source operatively connected to the drain of the first n-channel transistor, a drain operatively connected to receive the second supply voltage and a gate operatively connected to receive the reference voltage.
2. A voltage drive circuit according to claim 1, wherein the first supply voltage is positive with respect to the second supply voltage.
3. A voltage drive circuit according to claim 1, pivotably connectable to receive a clock signal, further comprising a second p-channel transistor having a source operatively connected to receive the first supply voltage, a drain operatively connected to the source of the first n-channel transistor, and a gate; a second n-channel transistor, a source operatively connected to the drain of the first p-channel transistor, a drain operatively connected to receive the second supply voltage and a gate pivotably connectable to receive the clock signal; and an inverter having an input operatively connected to receive a clock signal and an output operatively connected to the gate of the second p-channel transistor.
4. A voltage drive circuit according to claim 1, further comprising: a second n-channel transistor having a drain pivotably connectable to receive the reference voltage, a source operatively connected to its gate and to the gate of the first n- channel transistor; a first resistive element pivotably connected to the source of the second n-channel transistor and operatively connectable to receive the first supply voltage; a second p-channel transistor having a source operatively connectable to receive the reference voltage and operatively connected to the drain of the second n-channel transistor, a drain operatively connected to a gate of the second p-channel transistor and to the gate of the first p-channel transistor; and a second resistive element operatively connectable to receive the second supply voltage and operatively connected to the drain of the second p-channel transistor.
5. A voltage drive circuit according to claim 3, further comprising: a third n-channel transistor having a drain pivotably connectable to receive the reference voltage, a source operatively connected to its gate and to the gate of the first n- channel transistor; a first resistive element pivotably connected to the source of the second n-channel transistor and operatively connectable to receive the first supply voltage; a third p-channel transistor having a source operatively connectable to receive the reference voltage and operatively connected to the drain of the third n-channel transistor, a drain operatively connected to a gate of the third p-channel transistor and to the gate of the first p-channel transistor; and a second resistive element operatively connectable to receive the second supply voltage and operatively connected to the drain of the third p-channel transistor.
PCT/US2001/029299 2000-09-21 2001-09-20 An apparatus for active high speed - low power analog voltage drive WO2002025819A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU2001291119A AU2001291119A1 (en) 2000-09-21 2001-09-20 An apparatus for active high speed - low power analog voltage drive

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US66655100A 2000-09-21 2000-09-21
US09/666,551 2000-09-21

Publications (1)

Publication Number Publication Date
WO2002025819A1 true WO2002025819A1 (en) 2002-03-28

Family

ID=24674516

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2001/029299 WO2002025819A1 (en) 2000-09-21 2001-09-20 An apparatus for active high speed - low power analog voltage drive

Country Status (2)

Country Link
AU (1) AU2001291119A1 (en)
WO (1) WO2002025819A1 (en)

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05335935A (en) * 1992-06-03 1993-12-17 Hitachi Ltd Semiconductor integrated circuit
EP0587943A1 (en) * 1992-09-18 1994-03-23 Yozan Inc. Voltage follower circuit
WO1996008870A1 (en) * 1994-09-12 1996-03-21 Tadashi Shibata Semiconductor device
US5513389A (en) * 1992-08-27 1996-04-30 Motorola, Inc. Push pull buffer with noise cancelling symmetry
US5585744A (en) * 1995-10-13 1996-12-17 Cirrus Logic, Inc. Circuits systems and methods for reducing power loss during transfer of data across a conductive line
EP0849876A1 (en) * 1996-12-20 1998-06-24 Fujitsu Limited Amplifier circuit with wide dynamic range and low power consumption
EP0883247A2 (en) * 1992-06-15 1998-12-09 Fujitsu Limited Semiconductor integrated circuit with input/output interface adapted for small-amplitude operation

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05335935A (en) * 1992-06-03 1993-12-17 Hitachi Ltd Semiconductor integrated circuit
EP0883247A2 (en) * 1992-06-15 1998-12-09 Fujitsu Limited Semiconductor integrated circuit with input/output interface adapted for small-amplitude operation
US5513389A (en) * 1992-08-27 1996-04-30 Motorola, Inc. Push pull buffer with noise cancelling symmetry
EP0587943A1 (en) * 1992-09-18 1994-03-23 Yozan Inc. Voltage follower circuit
WO1996008870A1 (en) * 1994-09-12 1996-03-21 Tadashi Shibata Semiconductor device
US5585744A (en) * 1995-10-13 1996-12-17 Cirrus Logic, Inc. Circuits systems and methods for reducing power loss during transfer of data across a conductive line
EP0849876A1 (en) * 1996-12-20 1998-06-24 Fujitsu Limited Amplifier circuit with wide dynamic range and low power consumption

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 018, no. 161 (E - 1526) 17 March 1994 (1994-03-17) *
SEDRA A. , SMITH K.: "microelectronic circuits", 1991, SAUNDERS COLLEGE PUBLISHING, US, XP002190812 *

Also Published As

Publication number Publication date
AU2001291119A1 (en) 2002-04-02

Similar Documents

Publication Publication Date Title
US4740717A (en) Switching device with dynamic hysteresis
US5291071A (en) High speed, low power output circuit with temperature compensated noise control
US5973552A (en) Power savings technique in solid state integrated circuits
US5767710A (en) Power-up reset signal generating circuit for an integrated circuit
JPH0720060B2 (en) Output circuit device
US6121789A (en) Output buffer with control circuitry
JP2796833B2 (en) High speed logic circuit with feedback to prevent current in output stage
US20080018365A1 (en) Coil Load Drive Output Circuit
JPH04229714A (en) Integrated circuit having buffer
EP0351820B1 (en) Output circuit
JPH10173511A (en) Voltage level shifting circuit
JPH04167298A (en) Sense amplifier and method of quickening output transition
US5489859A (en) CMOS output circuit with high speed high impedance mode
US5610542A (en) Power-up detection circuit
US5786723A (en) Voltage switching circuit for a semiconductor memory device
US5408145A (en) Low power consumption and high speed NOR gate integrated circuit
US5442304A (en) CMOS logic gate clamping circuit
KR960012789B1 (en) Bootstrap circuit
WO2002025819A1 (en) An apparatus for active high speed - low power analog voltage drive
JP3583442B2 (en) High-speed amplitude limiting pull-up circuit
US5101120A (en) BiCMOS output driver
US5703517A (en) Power reduction in a temperature compensating transistor circuit
US6548995B1 (en) High speed bias voltage generating circuit
US7064596B1 (en) Reducing crowbar current in a latch hysteresis receiver
KR0157956B1 (en) Output buffer

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A1

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EC EE ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NO NZ PL PT RO RU SD SE SG SI SK SL TJ TM TR TT TZ UA UG UZ VN YU ZA ZW

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): GH GM KE LS MW MZ SD SL SZ TZ UG ZW AM AZ BY KG KZ MD RU TJ TM AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG

121 Ep: the epo has been informed by wipo that ep was designated in this application
REG Reference to national code

Ref country code: DE

Ref legal event code: 8642

122 Ep: pct application non-entry in european phase
NENP Non-entry into the national phase

Ref country code: JP