WO2002027340A3 - Method and system for testing and/or diagnosing circuits using test controller access data - Google Patents
Method and system for testing and/or diagnosing circuits using test controller access data Download PDFInfo
- Publication number
- WO2002027340A3 WO2002027340A3 PCT/CA2001/001296 CA0101296W WO0227340A3 WO 2002027340 A3 WO2002027340 A3 WO 2002027340A3 CA 0101296 W CA0101296 W CA 0101296W WO 0227340 A3 WO0227340 A3 WO 0227340A3
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- testing
- access data
- test controller
- diagnosis
- controller access
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
- G01R31/318307—Generation of test inputs, e.g. test vectors, patterns or sequences computer-aided, e.g. automatic test program generator [ATPG], program translations, test program debugging
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/31724—Test controller, e.g. BIST state machine
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
- G01R31/318342—Generation of test inputs, e.g. test vectors, patterns or sequences by preliminary fault modelling, e.g. analysis, simulation
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
- G01R31/318371—Methodologies therefor, e.g. algorithms, procedures
Abstract
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
AU2001291552A AU2001291552A1 (en) | 2000-09-28 | 2001-09-14 | Method and system for testing and/or diagnosing circuits using test controller access data |
JP2002530868A JP2004509425A (en) | 2000-09-28 | 2001-09-14 | Method and system for testing and / or diagnosing a circuit using test controller access data |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CA002321346A CA2321346A1 (en) | 2000-09-28 | 2000-09-28 | Method, system and program product for testing and/or diagnosing circuits using embedded test controller access data |
CA2,321,346 | 2000-09-28 |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2002027340A2 WO2002027340A2 (en) | 2002-04-04 |
WO2002027340A3 true WO2002027340A3 (en) | 2002-05-16 |
Family
ID=4167265
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/CA2001/001296 WO2002027340A2 (en) | 2000-09-28 | 2001-09-14 | Method and system for testing and/or diagnosing circuits using test controller access data |
Country Status (5)
Country | Link |
---|---|
US (1) | US6961871B2 (en) |
JP (1) | JP2004509425A (en) |
AU (1) | AU2001291552A1 (en) |
CA (1) | CA2321346A1 (en) |
WO (1) | WO2002027340A2 (en) |
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---|---|---|---|---|
US7823015B2 (en) * | 2001-02-20 | 2010-10-26 | Siemens Aktiengesellschaft | Method and device for determining a full error description for at least on part of a technical system computer program element and computer-readable storage medium |
US7047174B2 (en) * | 2001-05-02 | 2006-05-16 | Freescale Semiconductor, Inc. | Method for producing test patterns for testing an integrated circuit |
US7079612B2 (en) * | 2002-01-29 | 2006-07-18 | Texas Instruments Incorporated | Fast bit-error-rate (BER) test |
US20030188044A1 (en) * | 2002-03-28 | 2003-10-02 | International Business Machines Corporation | System and method for verifying superscalar computer architectures |
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US6898545B2 (en) * | 2002-06-28 | 2005-05-24 | Agilent Technologies Inc | Semiconductor test data analysis system |
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US7571068B2 (en) * | 2002-08-14 | 2009-08-04 | Nxp B.V. | Module, electronic device and evaluation tool |
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US7131046B2 (en) * | 2002-12-03 | 2006-10-31 | Verigy Ipco | System and method for testing circuitry using an externally generated signature |
US20040225459A1 (en) * | 2003-02-14 | 2004-11-11 | Advantest Corporation | Method and structure to develop a test program for semiconductor integrated circuits |
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US7509226B2 (en) * | 2003-06-25 | 2009-03-24 | Teradyne, Inc. | Apparatus and method for testing non-deterministic device data |
US20050010650A1 (en) * | 2003-07-11 | 2005-01-13 | Ying-Chuan Tsai | Network-based computer platform external access method and system |
US7231616B1 (en) * | 2003-08-20 | 2007-06-12 | Adaptec, Inc. | Method and apparatus for accelerating test case development |
US7363567B2 (en) * | 2003-08-28 | 2008-04-22 | Agilent Technologies, Inc. | System and method for electronic device testing using random parameter looping |
US20050080581A1 (en) * | 2003-09-22 | 2005-04-14 | David Zimmerman | Built-in self test for memory interconnect testing |
JP2005127765A (en) * | 2003-10-22 | 2005-05-19 | Toshiba Corp | Semiconductor test module and test method of semiconductor device |
US7096142B2 (en) * | 2004-04-02 | 2006-08-22 | Agilent Technologies, Inc. | Report format editor for circuit test |
US7430486B2 (en) * | 2004-05-22 | 2008-09-30 | Advantest America R&D Center, Inc. | Datalog support in a modular test system |
US7321999B2 (en) * | 2004-10-05 | 2008-01-22 | Verigy (Singapore) Pte. Ltd. | Methods and apparatus for programming and operating automated test equipment |
US7376876B2 (en) * | 2004-12-23 | 2008-05-20 | Honeywell International Inc. | Test program set generation tool |
US8126577B2 (en) | 2005-06-03 | 2012-02-28 | Neophotonics Corporation | Monitoring and control of electronic devices |
WO2006134411A1 (en) * | 2005-06-13 | 2006-12-21 | Infineon Technologies Ag | Built-in-self-test method for a semiconductor memory |
US7660412B1 (en) * | 2005-12-09 | 2010-02-09 | Trend Micro Incorporated | Generation of debug information for debugging a network security appliance |
US7509611B2 (en) * | 2006-02-07 | 2009-03-24 | International Business Machines Corporation | Heuristic clustering of circuit elements in a circuit design |
US7398505B2 (en) * | 2006-02-07 | 2008-07-08 | International Business Machines Corporation | Automatic back annotation of a functional definition of an integrated circuit design based upon physical layout |
DE102006009224B4 (en) * | 2006-02-28 | 2017-04-06 | Advanced Micro Devices, Inc. | Selection of a test algorithm in a controller for built-in memory self-test |
US8098797B2 (en) | 2006-12-27 | 2012-01-17 | Verizon Patent And Licensing Inc. | Self-service circuit testing systems and methods |
US7778799B2 (en) * | 2007-01-02 | 2010-08-17 | Hypertherm, Inc. | Automated self test for a thermal processing system |
US7664613B2 (en) * | 2007-04-03 | 2010-02-16 | Honeywell International Inc. | System and method of data harvesting |
US20090013218A1 (en) * | 2007-07-02 | 2009-01-08 | Optimal Test Ltd. | Datalog management in semiconductor testing |
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CN102077102B (en) * | 2008-07-02 | 2013-06-19 | 爱德万测试株式会社 | Test equipment and method |
US8589886B2 (en) * | 2008-07-07 | 2013-11-19 | Qualisystems Ltd. | System and method for automatic hardware and software sequencing of computer-aided design (CAD) functionality testing |
US8296092B2 (en) * | 2008-08-15 | 2012-10-23 | International Business Machines Corporation | Platform specific test for computing hardware |
US20100076724A1 (en) * | 2008-09-23 | 2010-03-25 | Harold Lee Brown | Method for capturing and analyzing test result data |
US7839155B2 (en) * | 2008-12-15 | 2010-11-23 | Texas Instruments Incorporated | Methods and apparatus to analyze on-chip controlled integrated circuits |
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US20130227367A1 (en) * | 2012-01-17 | 2013-08-29 | Allen J. Czamara | Test IP-Based A.T.E. Instrument Architecture |
US9910086B2 (en) | 2012-01-17 | 2018-03-06 | Allen Czamara | Test IP-based A.T.E. instrument architecture |
US9121892B2 (en) * | 2012-08-13 | 2015-09-01 | Analog Devices Global | Semiconductor circuit and methodology for in-system scan testing |
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US20150026528A1 (en) * | 2013-07-16 | 2015-01-22 | Manuel A. d'Abreu | Controller based memory evaluation |
US9286181B2 (en) * | 2013-07-31 | 2016-03-15 | Globalfoundries Inc. | Apparatus for capturing results of memory testing |
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FR3015723A1 (en) * | 2013-12-21 | 2015-06-26 | Expressive Data | METHOD FOR PRODUCING BUSINESS DATA IN RELATION TO A TEST OF A PLURALITY OF PRODUCTS, SERVER USING THE METHOD, SYSTEM AND COMPUTER PROGRAMS THEREFOR |
JP5963316B2 (en) * | 2014-02-20 | 2016-08-03 | インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Machines Corporation | Generating apparatus, generating method, and program |
US9372626B2 (en) * | 2014-06-12 | 2016-06-21 | Lenovo Enterprise Solutions (Singapore) Pte. Ltg. | Parallel storage system testing wherein I/O test pattern identifies one or more set of jobs to be executed concurrently |
US20160003900A1 (en) * | 2014-07-04 | 2016-01-07 | Texas Instruments Incorporated | Self-test methods and systems for digital circuits |
US9311444B1 (en) * | 2014-07-10 | 2016-04-12 | Sandia Corporation | Integrated circuit test-port architecture and method and apparatus of test-port generation |
US10592370B2 (en) * | 2017-04-28 | 2020-03-17 | Advantest Corporation | User control of automated test features with software application programming interface (API) |
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US10593419B1 (en) * | 2018-02-12 | 2020-03-17 | Cadence Design Systems, Inc. | Failing read count diagnostics for memory built-in self-test |
CN109344078B (en) * | 2018-10-29 | 2022-05-17 | 北京京航计算通讯研究所 | Time performance test method for embedded real-time operating system applying FPGA |
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CN113393892A (en) | 2020-03-11 | 2021-09-14 | 长鑫存储技术有限公司 | Control chip test method and related equipment |
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US11144696B1 (en) * | 2020-05-27 | 2021-10-12 | Chinsong Sul | Low cost design for test architecture |
CN111833959B (en) * | 2020-07-20 | 2022-08-02 | 北京百度网讯科技有限公司 | Method and device for testing memory, electronic equipment and computer readable storage medium |
KR102380506B1 (en) * | 2020-10-29 | 2022-03-31 | 포스필 주식회사 | Self diagnostic apparatus for electronic device |
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Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5377203A (en) * | 1989-02-23 | 1994-12-27 | Texas Instruments Incorporated | Test data formatter |
US5745501A (en) * | 1995-10-20 | 1998-04-28 | Motorola, Inc. | Apparatus and method for generating integrated circuit test patterns |
Family Cites Families (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4766595A (en) * | 1986-11-26 | 1988-08-23 | Allied-Signal Inc. | Fault diagnostic system incorporating behavior models |
US5111402A (en) * | 1990-01-19 | 1992-05-05 | Boeing Company | Integrated aircraft test system |
IL94115A (en) | 1990-04-18 | 1996-06-18 | Ibm Israel | Dynamic process for the generation of biased pseudo-random test patterns for the functional verification of hardware designs |
JPH04211871A (en) | 1990-05-02 | 1992-08-03 | Toshiba Corp | Inspection supporting system for logic design |
KR970010656B1 (en) | 1992-09-01 | 1997-06-30 | 마쯔시다 덴기 산교 가부시끼가이샤 | Semiconductor test device, semiconductor test circuit chip and probe card |
JP3212423B2 (en) | 1993-09-30 | 2001-09-25 | 富士通株式会社 | Test pattern creation device |
US5586319A (en) | 1994-07-27 | 1996-12-17 | Vlsi Technology, Inc. | Netlist editor allowing for direct, interactive low-level editing of netlists |
US5682392A (en) * | 1994-09-28 | 1997-10-28 | Teradyne, Inc. | Method and apparatus for the automatic generation of boundary scan description language files |
US5539652A (en) | 1995-02-07 | 1996-07-23 | Hewlett-Packard Company | Method for manufacturing test simulation in electronic circuit design |
US6014033A (en) | 1995-08-31 | 2000-01-11 | Texas Instruments Incorporated | Method of identifying the point at which an integrated circuit fails a functional test |
JP3003587B2 (en) | 1996-08-02 | 2000-01-31 | 日本電気株式会社 | Individual test program creation method |
US6114870A (en) | 1996-10-04 | 2000-09-05 | Texas Instruments Incorporated | Test system and process with a microcomputer at each test location |
US6687865B1 (en) * | 1998-03-25 | 2004-02-03 | On-Chip Technologies, Inc. | On-chip service processor for test and debug of integrated circuits |
US6061283A (en) | 1998-10-23 | 2000-05-09 | Advantest Corp. | Semiconductor integrated circuit evaluation system |
US6757837B1 (en) * | 1999-10-19 | 2004-06-29 | Tivo, Inc. | Method and apparatus for software failure diagnosis and repair |
US6681359B1 (en) * | 2000-08-07 | 2004-01-20 | Cypress Semiconductor Corp. | Semiconductor memory self-test controllable at board level using standard interface |
CA2329597A1 (en) * | 2000-12-22 | 2002-06-22 | Logicvision, Inc. | Method for scan controlled sequential sampling of analog signals and circuit for use therewith |
-
2000
- 2000-09-28 CA CA002321346A patent/CA2321346A1/en not_active Abandoned
-
2001
- 2001-09-14 AU AU2001291552A patent/AU2001291552A1/en not_active Abandoned
- 2001-09-14 JP JP2002530868A patent/JP2004509425A/en active Pending
- 2001-09-14 WO PCT/CA2001/001296 patent/WO2002027340A2/en active Application Filing
- 2001-09-18 US US09/954,078 patent/US6961871B2/en not_active Expired - Lifetime
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5377203A (en) * | 1989-02-23 | 1994-12-27 | Texas Instruments Incorporated | Test data formatter |
US5745501A (en) * | 1995-10-20 | 1998-04-28 | Motorola, Inc. | Apparatus and method for generating integrated circuit test patterns |
Non-Patent Citations (4)
Title |
---|
MARINISSEN E J ET AL: "The role of test protocols in testing embedded-core-based system ICs", TEST WORKSHOP 1999. PROCEEDINGS. EUROPEAN CONSTANCE, GERMANY 25-28 MAY 1999, LOS ALAMITOS, CA, USA,IEEE COMPUT. SOC, US, 25 May 1999 (1999-05-25), pages 70 - 75, XP010358737, ISBN: 0-7695-0390-X * |
MARINISSEN E J ET AL: "TOWARDS A STANDARD FOR EMBEDDED CORE TEST: AN EXAMPLE", PROCEEDINGS INTERNATIONAL TEST CONFERENCE 1999. ITC'99. ATLANTIC CITY, NJ, SEPT. 28 - 30, 1999, INTERNATIONAL TEST CONFERENCE, NEW YORK, NY: IEEE, US, vol. CONF. 30, September 1999 (1999-09-01), pages 616 - 627, XP000928874, ISBN: 0-7803-5754-X * |
TAYLOR T: "STANDARD TEST INTERFACE LANGUAGE (STIL), EXTENDING THE STANDARD", PROCEEDINGS OF THE INTERNATIONAL TEST CONFERENCE 1998. ITC '98. WASHINGTON, DC, OCT. 19 - 20, 1998, INTERNATIONAL TEST CONFERENCE, NEW YORK, NY: IEEE, US, vol. CONF. 29, 19 October 1998 (1998-10-19), pages 962 - 970, XP000822441, ISBN: 0-7803-5093-6 * |
WOHL P ET AL: "A UNIFIED INTERFACE FOR SCAN TEST GENERATION BASED ON STIL", PROCEEDINGS OF THE INTERNATIONAL TEST CONFERENCE. ITC '97. WASHINGTON, DC, NOV. 1 - 6, 1997, INTERNATIONAL TEST CONFERENCE, NEW YORK, NY: IEEE, US, vol. CONF. 28, 1 November 1997 (1997-11-01), pages 1011 - 1019, XP000800366, ISBN: 0-7803-4210-0 * |
Also Published As
Publication number | Publication date |
---|---|
AU2001291552A1 (en) | 2002-04-08 |
CA2321346A1 (en) | 2002-03-28 |
WO2002027340A2 (en) | 2002-04-04 |
JP2004509425A (en) | 2004-03-25 |
US20020073374A1 (en) | 2002-06-13 |
US6961871B2 (en) | 2005-11-01 |
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