WO2002027928A3 - Method and apparatus for tolerating defects in a programmable logic device using runtime parameterizable cores - Google Patents

Method and apparatus for tolerating defects in a programmable logic device using runtime parameterizable cores Download PDF

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Publication number
WO2002027928A3
WO2002027928A3 PCT/US2001/029334 US0129334W WO0227928A3 WO 2002027928 A3 WO2002027928 A3 WO 2002027928A3 US 0129334 W US0129334 W US 0129334W WO 0227928 A3 WO0227928 A3 WO 0227928A3
Authority
WO
WIPO (PCT)
Prior art keywords
defects
programmable logic
logic device
tolerating
configurable logic
Prior art date
Application number
PCT/US2001/029334
Other languages
French (fr)
Other versions
WO2002027928A2 (en
Inventor
Steven A Guccione
Prasanna Sundararajan
Original Assignee
Xilinx Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Xilinx Inc filed Critical Xilinx Inc
Publication of WO2002027928A2 publication Critical patent/WO2002027928A2/en
Publication of WO2002027928A3 publication Critical patent/WO2002027928A3/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/14—Error detection or correction of the data by redundancy in operation
    • G06F11/1402—Saving, restoring, recovering or retrying
    • G06F11/1415—Saving, restoring, recovering or retrying at system level
    • G06F11/142—Reconfiguring to eliminate the error
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]

Abstract

Method and apparatus for tolerating defects in a programmable logic device (PLD). A PLD includes a plurality of configurable logic elements and interconnect resources, wherein one or more of the configurable logic elements and interconnect resources have circuit defects. A design program is executed that is suitable for run-time reconfiguration of the PLD. The design program includes executable code that specifies a circuit design and generates a configuration bitstream that implements the circuit design on the programmable logic device. The design program also includes code that selectively skips the configurable logic elements and interconnect resources that contain the defects. In various embodiments, an individual configurable logic element, an entire row, or an entire column of elements can be skipped responsive to an input parameter.
PCT/US2001/029334 2000-09-28 2001-09-18 Method and apparatus for tolerating defects in a programmable logic device using runtime parameterizable cores WO2002027928A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/676,298 2000-09-28
US09/676,298 US6530071B1 (en) 2000-09-28 2000-09-28 Method and apparatus for tolerating defects in a programmable logic device using runtime parameterizable cores

Publications (2)

Publication Number Publication Date
WO2002027928A2 WO2002027928A2 (en) 2002-04-04
WO2002027928A3 true WO2002027928A3 (en) 2002-07-11

Family

ID=24713964

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2001/029334 WO2002027928A2 (en) 2000-09-28 2001-09-18 Method and apparatus for tolerating defects in a programmable logic device using runtime parameterizable cores

Country Status (2)

Country Link
US (1) US6530071B1 (en)
WO (1) WO2002027928A2 (en)

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US6802026B1 (en) * 2001-05-15 2004-10-05 Xilinx, Inc. Parameterizable and reconfigurable debugger core generators
US6732348B1 (en) * 2001-09-07 2004-05-04 Xilinx, Inc. Method for locating faults in a programmable logic device
US7139995B1 (en) * 2002-03-19 2006-11-21 Xilinx, Inc. Integration of a run-time parameterizable core with a static circuit design
US7143295B1 (en) * 2002-07-18 2006-11-28 Xilinx, Inc. Methods and circuits for dedicating a programmable logic device for use with specific designs
US7145344B2 (en) 2002-10-25 2006-12-05 Xilinx, Inc. Method and circuits for localizing defective interconnect resources in programmable logic devices
US7251804B1 (en) * 2004-10-01 2007-07-31 Xilinx, Inc. Structures and methods of overcoming localized defects in programmable integrated circuits by routing during the programming thereof
US7284229B1 (en) 2004-10-01 2007-10-16 Xilinx, Inc. Multiple bitstreams enabling the use of partially defective programmable integrated circuits while avoiding localized defects therein
US7412635B1 (en) 2004-10-01 2008-08-12 Xilinx, Inc. Utilizing multiple bitstreams to avoid localized defects in partially defective programmable integrated circuits
US7424655B1 (en) 2004-10-01 2008-09-09 Xilinx, Inc. Utilizing multiple test bitstreams to avoid localized defects in partially defective programmable integrated circuits
US7228521B1 (en) * 2005-02-01 2007-06-05 Xilinx Inc. System for operating a programmable logic device having a defective region
US7493578B1 (en) 2005-03-18 2009-02-17 Xilinx, Inc. Correlation of data from design analysis tools with design blocks in a high-level modeling system
US7496869B1 (en) 2005-10-04 2009-02-24 Xilinx, Inc. Method and apparatus for implementing a program language description of a circuit design for an integrated circuit
US7363599B1 (en) 2005-10-04 2008-04-22 Xilinx, Inc. Method and system for matching a hierarchical identifier
US20070139074A1 (en) * 2005-12-19 2007-06-21 M2000 Configurable circuits with microcontrollers
US7793251B2 (en) * 2006-01-12 2010-09-07 International Business Machines Corporation Method for increasing the manufacturing yield of programmable logic devices
US8402409B1 (en) * 2006-03-10 2013-03-19 Xilinx, Inc. Method and apparatus for supporting run-time reconfiguration in a programmable logic integrated circuit
US7380232B1 (en) 2006-03-10 2008-05-27 Xilinx, Inc. Method and apparatus for designing a system for implementation in a programmable logic device
US7761272B1 (en) 2006-03-10 2010-07-20 Xilinx, Inc. Method and apparatus for processing a dataflow description of a digital processing system
EP1995663A1 (en) 2007-05-22 2008-11-26 Panasonic Corporation System and method for local generation of programming data in a programable device
US7853916B1 (en) 2007-10-11 2010-12-14 Xilinx, Inc. Methods of using one of a plurality of configuration bitstreams for an integrated circuit
US7810059B1 (en) 2007-10-11 2010-10-05 Xilinx, Inc. Methods of enabling the validation of an integrated circuit adapted to receive one of a plurality of configuration bitstreams
US7619438B1 (en) 2007-10-11 2009-11-17 Xilinx, Inc. Methods of enabling the use of a defective programmable device
US8990616B2 (en) * 2012-09-28 2015-03-24 International Business Machines Corporation Final faulty core recovery mechanisms for a two-dimensional network on a processor array
US9160617B2 (en) 2012-09-28 2015-10-13 International Business Machines Corporation Faulty core recovery mechanisms for a three-dimensional network on a processor array
US9372956B1 (en) * 2014-11-10 2016-06-21 Xilinx, Inc. Increased usable programmable device dice

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Publication number Publication date
US6530071B1 (en) 2003-03-04
WO2002027928A2 (en) 2002-04-04

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