WO2002029569A3 - A system and method to enhance manufacturing test failure analysis with dedicated pins - Google Patents

A system and method to enhance manufacturing test failure analysis with dedicated pins Download PDF

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Publication number
WO2002029569A3
WO2002029569A3 PCT/EP2001/011402 EP0111402W WO0229569A3 WO 2002029569 A3 WO2002029569 A3 WO 2002029569A3 EP 0111402 W EP0111402 W EP 0111402W WO 0229569 A3 WO0229569 A3 WO 0229569A3
Authority
WO
WIPO (PCT)
Prior art keywords
scan test
debugging
chain
test
supplemental
Prior art date
Application number
PCT/EP2001/011402
Other languages
French (fr)
Other versions
WO2002029569A2 (en
Inventor
Kenneth Jaramillo
Varaprasda Vajjhala
Original Assignee
Koninkl Philips Electronics Nv
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninkl Philips Electronics Nv filed Critical Koninkl Philips Electronics Nv
Priority to EP01980470A priority Critical patent/EP1370940A2/en
Priority to JP2002533075A priority patent/JP2004511045A/en
Publication of WO2002029569A2 publication Critical patent/WO2002029569A2/en
Publication of WO2002029569A3 publication Critical patent/WO2002029569A3/en

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Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
    • G01R31/318342—Generation of test inputs, e.g. test vectors, patterns or sequences by preliminary fault modelling, e.g. analysis, simulation
    • G01R31/31835—Analysis of test coverage or failure detectability

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Tests Of Electronic Circuits (AREA)

Abstract

The present invention is a scan test chain intermediate debugging system and method that facilitates simplified debugging of internal component scan test results with minimal impacts to normal operations and manufacturing processes. The scan test chain intermediate debugging system and method of the present invention enhances internal scan test analysis on internal scan test chains included in digital circuits and is compatible with scan test methodologies. One embodiment of the present invention includes a scan test chain intermediate debugging system including a test vector debugging control circuit (e.g., a multiplexer), a supplemental scan test output port and an intermediate control signal port. The test vector debugging control circuit selectively provides a communication path from an indicated intermediate scan test chain signal to the supplemental scan test output port. The intermediate scan test signal is a measurement or logical value captured from an intermediate point in the scan test chain. The intermediate control signal port provides a communication path for a control signal that directs the test vector debugging control circuit which intermediate scan test signal to transmit to the supplemental scan test output port. The supplemental scan test output port operates to transmit intermediate scan test signals off of the IC. By selectively transmitting one of the intermediate scan test chain signals off of the IC, the scan test chain intermediate debugging system and method facilitates greater granularity of test vector results and assists scan test analysis including debugging indications of faults.
PCT/EP2001/011402 2000-10-02 2001-10-02 A system and method to enhance manufacturing test failure analysis with dedicated pins WO2002029569A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP01980470A EP1370940A2 (en) 2000-10-02 2001-10-02 A system and method to enhance manufacturing test failure analysis with dedicated pins
JP2002533075A JP2004511045A (en) 2000-10-02 2001-10-02 System and method for enhancing manufacturing test failure analysis with dedicated pins

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US67793700A 2000-10-02 2000-10-02
US09/677,937 2000-10-02

Publications (2)

Publication Number Publication Date
WO2002029569A2 WO2002029569A2 (en) 2002-04-11
WO2002029569A3 true WO2002029569A3 (en) 2003-10-09

Family

ID=24720713

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/EP2001/011402 WO2002029569A2 (en) 2000-10-02 2001-10-02 A system and method to enhance manufacturing test failure analysis with dedicated pins

Country Status (3)

Country Link
EP (1) EP1370940A2 (en)
JP (1) JP2004511045A (en)
WO (1) WO2002029569A2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111443274B (en) * 2019-01-17 2022-06-17 瑞昱半导体股份有限公司 Circuit test system and circuit test method

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4701921A (en) * 1985-10-23 1987-10-20 Texas Instruments Incorporated Modularized scan path for serially tested logic circuit
US5592493A (en) * 1994-09-13 1997-01-07 Motorola Inc. Serial scan chain architecture for a data processing system and method of operation
US5757819A (en) * 1994-07-01 1998-05-26 Advanced Risc Machines Limited Integrated circuit test controller

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4701921A (en) * 1985-10-23 1987-10-20 Texas Instruments Incorporated Modularized scan path for serially tested logic circuit
US5757819A (en) * 1994-07-01 1998-05-26 Advanced Risc Machines Limited Integrated circuit test controller
US5592493A (en) * 1994-09-13 1997-01-07 Motorola Inc. Serial scan chain architecture for a data processing system and method of operation

Also Published As

Publication number Publication date
WO2002029569A2 (en) 2002-04-11
EP1370940A2 (en) 2003-12-17
JP2004511045A (en) 2004-04-08

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