WO2002033706A3 - Noise suppression for open bit line dram architectures - Google Patents

Noise suppression for open bit line dram architectures Download PDF

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Publication number
WO2002033706A3
WO2002033706A3 PCT/US2001/031159 US0131159W WO0233706A3 WO 2002033706 A3 WO2002033706 A3 WO 2002033706A3 US 0131159 W US0131159 W US 0131159W WO 0233706 A3 WO0233706 A3 WO 0233706A3
Authority
WO
WIPO (PCT)
Prior art keywords
bit line
dram
cells
coupling
approach
Prior art date
Application number
PCT/US2001/031159
Other languages
French (fr)
Other versions
WO2002033706A2 (en
Inventor
Shih-Lien Lu
Dinesh Somasekhar
Vivek De
Original Assignee
Intel Corp
Shih-Lien Lu
Dinesh Somasekhar
Vivek De
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp, Shih-Lien Lu, Dinesh Somasekhar, Vivek De filed Critical Intel Corp
Priority to GB0310604A priority Critical patent/GB2385201B/en
Priority to AU2002211437A priority patent/AU2002211437A1/en
Priority to DE10196802T priority patent/DE10196802B4/en
Publication of WO2002033706A2 publication Critical patent/WO2002033706A2/en
Publication of WO2002033706A3 publication Critical patent/WO2002033706A3/en
Priority to HK03107698A priority patent/HK1055506A1/en

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4097—Bit-line organisation, e.g. bit-line layout, folded bit lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4094—Bit-line management or control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/02—Arrangements for writing information into, or reading information out from, a digital store with means for avoiding parasitic signals

Abstract

An open bit line dynamic random access memory (DRAM) architecture uses a multiple layer bit line configuration to reduce coupling between switching bit lines in the device. In one approach, each successive cell within a row of DRAM cells is coupled to a bit line segment that is on a different metallization layer than a previous cell in the row. Shielding members are also provided between adjacent bit lines on a common metallization layer to further reduce noise coupling. Functionality is also provided for reducing the effect of word line to bit line coupling in the DRAM device using dummy signal injection techniques. In this manner, common mode noise that could otherwise saturate one or more sense amplifiers within the DRAM device is reduced or eliminated before such saturation can take place. In one approach, dummy cells and reference cells are provided for use in performing the signal injection. The principles of the present invention are particularly well suited for use within embedded DRAM structures where low charge storage capacity within individual cells reduces the signal voltage levels that are achievable.
PCT/US2001/031159 2000-10-17 2001-10-03 Noise suppression for open bit line dram architectures WO2002033706A2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
GB0310604A GB2385201B (en) 2000-10-17 2001-10-03 Noise suppression for open bit line dram architectures
AU2002211437A AU2002211437A1 (en) 2000-10-17 2001-10-03 Noise suppression for open bit line dram architectures
DE10196802T DE10196802B4 (en) 2000-10-17 2001-10-03 Noise reduction for open bit-line DRAM architectures
HK03107698A HK1055506A1 (en) 2000-10-17 2003-10-24 Noise suppression for open bit line dram architectures.

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/690,513 US6496402B1 (en) 2000-10-17 2000-10-17 Noise suppression for open bit line DRAM architectures
US09/690,513 2000-10-17

Publications (2)

Publication Number Publication Date
WO2002033706A2 WO2002033706A2 (en) 2002-04-25
WO2002033706A3 true WO2002033706A3 (en) 2003-04-17

Family

ID=24772765

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2001/031159 WO2002033706A2 (en) 2000-10-17 2001-10-03 Noise suppression for open bit line dram architectures

Country Status (8)

Country Link
US (2) US6496402B1 (en)
CN (3) CN101329904B (en)
AU (1) AU2002211437A1 (en)
DE (1) DE10196802B4 (en)
GB (4) GB2406199B (en)
HK (1) HK1055506A1 (en)
TW (1) TW529027B (en)
WO (1) WO2002033706A2 (en)

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Also Published As

Publication number Publication date
CN100511474C (en) 2009-07-08
US20030072172A1 (en) 2003-04-17
CN1572002A (en) 2005-01-26
CN101330086A (en) 2008-12-24
GB2406199B (en) 2005-05-18
GB0310604D0 (en) 2003-06-11
US6496402B1 (en) 2002-12-17
TW529027B (en) 2003-04-21
GB2406197B (en) 2005-06-08
GB2406198B (en) 2005-05-18
DE10196802T5 (en) 2004-04-15
GB2385201A (en) 2003-08-13
GB2385201B (en) 2005-04-27
DE10196802B4 (en) 2013-06-06
GB2406197A (en) 2005-03-23
HK1055506A1 (en) 2004-01-09
GB0425947D0 (en) 2004-12-29
WO2002033706A2 (en) 2002-04-25
US6721222B2 (en) 2004-04-13
CN101329904A (en) 2008-12-24
GB0425950D0 (en) 2004-12-29
GB2406199A (en) 2005-03-23
GB0425949D0 (en) 2004-12-29
CN101329904B (en) 2012-01-25
AU2002211437A1 (en) 2002-04-29
CN101330086B (en) 2011-02-23
GB2406198A (en) 2005-03-23

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