WO2002033706A3 - Noise suppression for open bit line dram architectures - Google Patents
Noise suppression for open bit line dram architectures Download PDFInfo
- Publication number
- WO2002033706A3 WO2002033706A3 PCT/US2001/031159 US0131159W WO0233706A3 WO 2002033706 A3 WO2002033706 A3 WO 2002033706A3 US 0131159 W US0131159 W US 0131159W WO 0233706 A3 WO0233706 A3 WO 0233706A3
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- bit line
- dram
- cells
- coupling
- approach
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4097—Bit-line organisation, e.g. bit-line layout, folded bit lines
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4094—Bit-line management or control circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/02—Arrangements for writing information into, or reading information out from, a digital store with means for avoiding parasitic signals
Abstract
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
AU2002211437A AU2002211437A1 (en) | 2000-10-17 | 2001-10-03 | Noise suppression for open bit line dram architectures |
DE10196802T DE10196802B4 (en) | 2000-10-17 | 2001-10-03 | Noise reduction for open bit-line DRAM architectures |
GB0310604A GB2385201B (en) | 2000-10-17 | 2001-10-03 | Noise suppression for open bit line dram architectures |
HK03107698A HK1055506A1 (en) | 2000-10-17 | 2003-10-24 | Noise suppression for open bit line dram architectures. |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/690,513 US6496402B1 (en) | 2000-10-17 | 2000-10-17 | Noise suppression for open bit line DRAM architectures |
US09/690,513 | 2000-10-17 |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2002033706A2 WO2002033706A2 (en) | 2002-04-25 |
WO2002033706A3 true WO2002033706A3 (en) | 2003-04-17 |
Family
ID=24772765
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US2001/031159 WO2002033706A2 (en) | 2000-10-17 | 2001-10-03 | Noise suppression for open bit line dram architectures |
Country Status (8)
Country | Link |
---|---|
US (2) | US6496402B1 (en) |
CN (3) | CN101330086B (en) |
AU (1) | AU2002211437A1 (en) |
DE (1) | DE10196802B4 (en) |
GB (4) | GB2385201B (en) |
HK (1) | HK1055506A1 (en) |
TW (1) | TW529027B (en) |
WO (1) | WO2002033706A2 (en) |
Families Citing this family (78)
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Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
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US4247917A (en) * | 1979-08-27 | 1981-01-27 | Intel Corporation | MOS Random-access memory |
US4363111A (en) * | 1980-10-06 | 1982-12-07 | Heightley John D | Dummy cell arrangement for an MOS memory |
US4622655A (en) * | 1983-05-04 | 1986-11-11 | Nec Corporation | Semiconductor memory |
US5031153A (en) * | 1988-12-13 | 1991-07-09 | Oki Electric Industry Co., Ltd. | MOS semiconductor memory device having sense control circuitry simplified |
EP0452648A1 (en) * | 1990-04-20 | 1991-10-23 | International Business Machines Corporation | Stacked bit line architecture for high density cross-point memory cell array |
US5292678A (en) * | 1991-11-04 | 1994-03-08 | International Business Machines Corporation | Forming a bit line configuration for semiconductor memory |
US5424977A (en) * | 1992-06-25 | 1995-06-13 | Texas Instruments Incorporated | Sense amplifier having shared dummy cell |
US6118708A (en) * | 1998-05-14 | 2000-09-12 | Fujitsu Limited | Semiconductor memory device |
WO2001026139A2 (en) * | 1999-10-04 | 2001-04-12 | Infineon Technologies North America Corp. | Dram bit lines and support circuitry contacting scheme |
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JPS6413290A (en) * | 1987-07-07 | 1989-01-18 | Oki Electric Ind Co Ltd | Semiconductor memory |
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US6496402B1 (en) * | 2000-10-17 | 2002-12-17 | Intel Corporation | Noise suppression for open bit line DRAM architectures |
-
2000
- 2000-10-17 US US09/690,513 patent/US6496402B1/en not_active Expired - Lifetime
-
2001
- 2001-10-03 CN CN2008101295851A patent/CN101330086B/en not_active Expired - Fee Related
- 2001-10-03 CN CNB018175287A patent/CN100511474C/en not_active Expired - Fee Related
- 2001-10-03 GB GB0310604A patent/GB2385201B/en not_active Expired - Fee Related
- 2001-10-03 GB GB0425949A patent/GB2406198B/en not_active Expired - Fee Related
- 2001-10-03 WO PCT/US2001/031159 patent/WO2002033706A2/en active Application Filing
- 2001-10-03 DE DE10196802T patent/DE10196802B4/en not_active Expired - Fee Related
- 2001-10-03 GB GB0425947A patent/GB2406197B/en not_active Expired - Fee Related
- 2001-10-03 CN CN2008101295847A patent/CN101329904B/en not_active Expired - Fee Related
- 2001-10-03 AU AU2002211437A patent/AU2002211437A1/en not_active Abandoned
- 2001-10-03 GB GB0425950A patent/GB2406199B/en not_active Expired - Fee Related
- 2001-10-17 TW TW090125640A patent/TW529027B/en active
-
2002
- 2002-11-19 US US10/300,398 patent/US6721222B2/en not_active Expired - Lifetime
-
2003
- 2003-10-24 HK HK03107698A patent/HK1055506A1/en not_active IP Right Cessation
Patent Citations (9)
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US4247917A (en) * | 1979-08-27 | 1981-01-27 | Intel Corporation | MOS Random-access memory |
US4363111A (en) * | 1980-10-06 | 1982-12-07 | Heightley John D | Dummy cell arrangement for an MOS memory |
US4622655A (en) * | 1983-05-04 | 1986-11-11 | Nec Corporation | Semiconductor memory |
US5031153A (en) * | 1988-12-13 | 1991-07-09 | Oki Electric Industry Co., Ltd. | MOS semiconductor memory device having sense control circuitry simplified |
EP0452648A1 (en) * | 1990-04-20 | 1991-10-23 | International Business Machines Corporation | Stacked bit line architecture for high density cross-point memory cell array |
US5292678A (en) * | 1991-11-04 | 1994-03-08 | International Business Machines Corporation | Forming a bit line configuration for semiconductor memory |
US5424977A (en) * | 1992-06-25 | 1995-06-13 | Texas Instruments Incorporated | Sense amplifier having shared dummy cell |
US6118708A (en) * | 1998-05-14 | 2000-09-12 | Fujitsu Limited | Semiconductor memory device |
WO2001026139A2 (en) * | 1999-10-04 | 2001-04-12 | Infineon Technologies North America Corp. | Dram bit lines and support circuitry contacting scheme |
Also Published As
Publication number | Publication date |
---|---|
GB2385201A (en) | 2003-08-13 |
GB2406199A (en) | 2005-03-23 |
GB0425950D0 (en) | 2004-12-29 |
GB2406197B (en) | 2005-06-08 |
GB0310604D0 (en) | 2003-06-11 |
GB2406198B (en) | 2005-05-18 |
CN1572002A (en) | 2005-01-26 |
GB2385201B (en) | 2005-04-27 |
US6496402B1 (en) | 2002-12-17 |
GB2406197A (en) | 2005-03-23 |
DE10196802B4 (en) | 2013-06-06 |
US20030072172A1 (en) | 2003-04-17 |
HK1055506A1 (en) | 2004-01-09 |
GB2406198A (en) | 2005-03-23 |
CN101330086A (en) | 2008-12-24 |
CN101329904B (en) | 2012-01-25 |
GB0425947D0 (en) | 2004-12-29 |
GB0425949D0 (en) | 2004-12-29 |
CN100511474C (en) | 2009-07-08 |
TW529027B (en) | 2003-04-21 |
DE10196802T5 (en) | 2004-04-15 |
WO2002033706A2 (en) | 2002-04-25 |
US6721222B2 (en) | 2004-04-13 |
GB2406199B (en) | 2005-05-18 |
CN101329904A (en) | 2008-12-24 |
AU2002211437A1 (en) | 2002-04-29 |
CN101330086B (en) | 2011-02-23 |
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