WO2002037340A2 - System and method for test generation with dynamic constraints using static analysis - Google Patents
System and method for test generation with dynamic constraints using static analysis Download PDFInfo
- Publication number
- WO2002037340A2 WO2002037340A2 PCT/IL2001/001011 IL0101011W WO0237340A2 WO 2002037340 A2 WO2002037340 A2 WO 2002037340A2 IL 0101011 W IL0101011 W IL 0101011W WO 0237340 A2 WO0237340 A2 WO 0237340A2
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- constraints
- dynamic
- instructions
- constraint
- graph
- Prior art date
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Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
- G01R31/318342—Generation of test inputs, e.g. test vectors, patterns or sequences by preliminary fault modelling, e.g. analysis, simulation
Definitions
- Design verification is the process of determining whether an integrated circuit, board, or system-level architecture, exactly implements the requirements defined by the specification of the architecture for that device.
- Design verification for a device under testing (DUT) may be performed on the actual device, or on a simulation model of the device.
- DUT device under testing
- GML generator mini-language
- These instructions are then executed in order to provide a correct random solution to a given set of dynamic constraints.
- the process of execution is preferably performed by a constraint resolution engine, optionally and more preferably implemented as software, which manages the requirements imposed by the constraints on the execution, while simultaneously enabling a random solution to the set of constraints to be provided.
- a constraint resolution engine may optionally be viewed as a type of state machine, in which individual elements of the state machine are more preferably represented by one or more dynamic graph(s).
- PC personal computers
- Such software operating systems include, but are not limited to, UNIX, VMS, Linux,
- the method of the present invention could also be described as a plurality of instructions being performed by a virtual or actual data processor, such that the
- a software application could be written in substantially any suitable programming language, which could ⁇ J i! J t 5 , J "M" ' , ⁇ _ fw n - easily be selected by one of ordinary skill in the art.
- the programming language chosen should be compatible with the computing platform according to which the software application is executed. Examples of suitable programming languages include, but are not limited to, C, C++ and Java.
- non-random refers to a process, or an entity selected by the process, which is not random but which is not necessarily deterministic.
- FIG. 1 is a schematic block diagram illustrating an exemplary system according to the present invention
- GML generator mini-language
- individual elements of the state machine are more preferably represented by one or more dynamic graph(s).
- the constraint resolution engine of the present invention enables the process of
- the present invention is capable of separating the process of constraint resolution into two stages: during static
- the present invention is also useful for verification
- Test engine 16 features a test generator 18, connected to a run-time system 21
- Run-time system 21 both
- module 31 preferably receives these instructions, and executes them in conjunction
- a data collector 24 requests the
- Data collector 24 is able to communicate with test
- Order manager 28 preferably maintains a dynamic graph 32 with bi-directional and uni-directional edges. Dynamic graph 32 is more preferably used to determine the order of incorporation of the instruction representing each constraint, according to the
- Each node represents field ranges for specific variables, for which particular values can be
- Dependency graph manager 30 uses
- OM_create__nodes for creating order graph nodes for a given set of nodes for the
- Specific instructions for dependency graph manager 30 optionally include, but are not limited to, DGM_create_constraint for creating a constraint node and
- the AGM AGM
- a generation role is a conceptualization of this need for a "struct-type in context", or for being able to define the struct according to the context,
- Initial ranges are statically inferred ranges, or sets of
- ROLE_gen_top in which the following instructions are executed: get next node Nfrom the OM using OM_get_next; if the picked node
- roles may be either statically ordered or unordered.
- OM_get_next( ) returns field A 38 with a ⁇ /indication.
- the returned dof is field B
Abstract
Description
Claims
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2002540016A JP2004513435A (en) | 2000-11-03 | 2001-10-31 | System and method for dynamic constrained test generation using static analysis |
IL15569201A IL155692A0 (en) | 2000-11-03 | 2001-10-31 | System and method for test generation with dynamic constraints using static analysis |
EP01982688A EP1374103A2 (en) | 2000-11-03 | 2001-10-31 | System and method for test generation with dynamic constraints using static analysis |
AU2002214229A AU2002214229A1 (en) | 2000-11-03 | 2001-10-31 | System and method for test generation with dynamic constraints using static analysis |
IL155692A IL155692A (en) | 2000-11-03 | 2003-04-30 | System and method for test generation with dynamic constraints using static analysis |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US24514600P | 2000-11-03 | 2000-11-03 | |
US60/245,146 | 2000-11-03 | ||
US09/799,066 US6684359B2 (en) | 2000-11-03 | 2001-03-06 | System and method for test generation with dynamic constraints using static analysis |
US09/799,066 | 2001-03-06 |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2002037340A2 true WO2002037340A2 (en) | 2002-05-10 |
WO2002037340A3 WO2002037340A3 (en) | 2003-10-16 |
Family
ID=26937028
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/IL2001/001011 WO2002037340A2 (en) | 2000-11-03 | 2001-10-31 | System and method for test generation with dynamic constraints using static analysis |
Country Status (6)
Country | Link |
---|---|
US (1) | US6684359B2 (en) |
EP (1) | EP1374103A2 (en) |
JP (1) | JP2004513435A (en) |
AU (1) | AU2002214229A1 (en) |
IL (1) | IL155692A0 (en) |
WO (1) | WO2002037340A2 (en) |
Cited By (1)
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Families Citing this family (60)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20030188044A1 (en) * | 2002-03-28 | 2003-10-02 | International Business Machines Corporation | System and method for verifying superscalar computer architectures |
US6968285B1 (en) | 2003-04-09 | 2005-11-22 | Hamid Adnan A | Method and apparatus for scenario search based random generation of functional test suites |
EP1621945B1 (en) * | 2004-07-30 | 2017-03-29 | Siemens Aktiengesellschaft | Ensuring data consistency in an automation system |
US7667582B1 (en) * | 2004-10-14 | 2010-02-23 | Sun Microsystems, Inc. | Tool for creating charts |
US7634761B2 (en) * | 2004-10-29 | 2009-12-15 | Microsoft Corporation | Breakpoint logging and constraint mechanisms for parallel computing systems |
US7376876B2 (en) * | 2004-12-23 | 2008-05-20 | Honeywell International Inc. | Test program set generation tool |
US7313772B2 (en) * | 2005-05-24 | 2007-12-25 | International Business Machines Corporation | Systems, methods, and media for block-based assertion generation, qualification and analysis |
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US7809369B2 (en) * | 2006-06-02 | 2010-10-05 | W2Bi, Inc. | Adaptive testing of system acquisition and roaming characteristics for CDMA wireless communication systems |
US7870523B1 (en) | 2006-06-15 | 2011-01-11 | Cadence Design Systems, Inc. | System and method for test generation with dynamic constraints using static analysis and multidomain constraint reduction |
US7779374B1 (en) | 2006-09-29 | 2010-08-17 | Breker Verification Systems, Inc. | Generating self-checking test cases from reduced case analysis graphs |
US7543266B2 (en) * | 2006-11-20 | 2009-06-02 | Microsoft Corporation | Lock-free state merging in parallelized constraint satisfaction problem solvers |
US20080155354A1 (en) * | 2006-12-20 | 2008-06-26 | Kolman Robert S | Method and apparatus for collection and comparison of test data of multiple test runs |
US8296697B2 (en) * | 2007-03-19 | 2012-10-23 | Cadence Design Systems, Inc. | Method and apparatus for performing static analysis optimization in a design verification system |
US8271257B2 (en) * | 2007-05-24 | 2012-09-18 | Palo Alto Research Center Incorporated | Troubleshooting temporal behavior in “combinational” circuits |
US8024610B2 (en) * | 2007-05-24 | 2011-09-20 | Palo Alto Research Center Incorporated | Diagnosing intermittent faults |
US7617468B2 (en) * | 2007-07-31 | 2009-11-10 | Synopsys, Inc. | Method for automatic maximization of coverage in constrained stimulus driven simulation |
US7904846B2 (en) * | 2007-07-31 | 2011-03-08 | Synopsys, Inc. | Method for automatically extracting a functional coverage model from a constraint specification |
US20090070570A1 (en) * | 2007-09-11 | 2009-03-12 | Shubhodeep Roy Choudhury | System and Method for Efficiently Handling Interrupts |
US8099559B2 (en) * | 2007-09-11 | 2012-01-17 | International Business Machines Corporation | System and method for generating fast instruction and data interrupts for processor design verification and validation |
US7669083B2 (en) * | 2007-09-11 | 2010-02-23 | International Business Machines Corporation | System and method for re-shuffling test case instruction orders for processor design verification and validation |
US7992059B2 (en) | 2007-09-11 | 2011-08-02 | International Business Machines Corporation | System and method for testing a large memory area during processor design verification and validation |
US8006221B2 (en) * | 2007-09-11 | 2011-08-23 | International Business Machines Corporation | System and method for testing multiple processor modes for processor design verification and validation |
US8019566B2 (en) * | 2007-09-11 | 2011-09-13 | International Business Machines Corporation | System and method for efficiently testing cache congruence classes during processor design verification and validation |
US8527965B2 (en) * | 2008-04-14 | 2013-09-03 | Oracle America, Inc. | Layered static program analysis framework for software testing |
US9294621B2 (en) | 2008-04-21 | 2016-03-22 | Aetherpal Inc. | Virtual mobile management—remote control |
US8140457B2 (en) * | 2008-07-09 | 2012-03-20 | International Business Machines Corporation | Determining compliance rates for probabilistic requests |
US7966521B2 (en) * | 2008-07-14 | 2011-06-21 | International Business Machines Corporation | Light weight and high throughput test case generation methodology for testing cache/TLB intervention and diagnostics |
US8694893B2 (en) * | 2008-08-08 | 2014-04-08 | Oracle International Corporation | Interactive product configurator with persistent component association |
US8209276B2 (en) * | 2008-10-27 | 2012-06-26 | Oracle International Corporation | Constraint based system with dynamic consistency checking |
US8065255B2 (en) * | 2008-11-13 | 2011-11-22 | Oracle International Corporation | Management of sub-problems in a dynamic constraint satisfaction problem solver |
US8504501B2 (en) * | 2008-11-13 | 2013-08-06 | Oracle International Corporation | Dynamic constraint satisfaction problem solver |
US9443210B2 (en) * | 2008-11-24 | 2016-09-13 | Oracle International Corporation | Interactive product configurator with automatic selections |
US8165980B2 (en) * | 2009-01-23 | 2012-04-24 | Oracle International Corporation | Dynamic constraint solver with cross problem constraints |
US20100191688A1 (en) * | 2009-01-29 | 2010-07-29 | Oracle International Corporation | Dynamic constraint solver with resource sum constraints |
US8386544B2 (en) * | 2009-02-05 | 2013-02-26 | Oracle International Corporation | Managing floating point variables in constraint satisfaction problems |
US8126834B2 (en) * | 2009-04-21 | 2012-02-28 | Oracle International Corporation | Dynamic constraint satisfaction problem solver with hierarchical union constraints |
US8229869B2 (en) * | 2009-04-22 | 2012-07-24 | Oracle International Corporation | Constraint processing with zero value handling |
US8645302B2 (en) * | 2009-04-28 | 2014-02-04 | Oracle International Corporation | Dynamic constraint satisfaction problem solver with part-whole hierarchy constraints |
US8229870B2 (en) * | 2009-04-28 | 2012-07-24 | Oracle International Corporation | Constraint based system with domain splitting |
US8949103B2 (en) * | 2009-05-01 | 2015-02-03 | Microsoft Corporation | Program code simulator |
US8751425B2 (en) * | 2009-06-12 | 2014-06-10 | Oracle International Corporation | Constraint satisfaction problem solver with interactive conflict resolution |
US8170970B2 (en) * | 2009-06-24 | 2012-05-01 | Oracle International Corporation | Constraint based system that identifies top constraint expressions |
US8447716B2 (en) * | 2009-07-27 | 2013-05-21 | Oracle International Corporation | Dynamic constraint satisfaction problem solver with inferred problem association removal |
US8301582B2 (en) * | 2009-10-15 | 2012-10-30 | Oracle International Corporation | Dynamic constraint satisfaction problem solver with sub-problem placeholder |
US20120174068A1 (en) * | 2010-12-30 | 2012-07-05 | Sap Ag | Testing Software Code |
US20120331124A1 (en) * | 2011-06-22 | 2012-12-27 | Raman Ramteke Venkatesh | Constraint definition for capacity mangement |
US8560893B1 (en) * | 2011-10-21 | 2013-10-15 | Cadence Design Systems, Inc. | Systems and methods for automatically generating executable system level-tests from a partially specified scenario |
US9015246B2 (en) | 2012-03-30 | 2015-04-21 | Aetherpal Inc. | Session collaboration |
US9141509B2 (en) | 2012-03-30 | 2015-09-22 | Aetherpal Inc. | Mobile device remote control session activity pattern recognition |
US9224001B2 (en) | 2012-03-30 | 2015-12-29 | Aetherpal Inc. | Access control list for applications on mobile devices during a remote control session |
US9069973B2 (en) | 2012-03-30 | 2015-06-30 | Aetherpal Inc. | Password protect feature for application in mobile device during a remote session |
US9473953B2 (en) | 2012-03-30 | 2016-10-18 | Aetherpal Inc. | Roaming detection and session recovery during VMM-RC |
US11468218B2 (en) | 2012-08-28 | 2022-10-11 | Synopsys, Inc. | Information theoretic subgraph caching |
US9720792B2 (en) | 2012-08-28 | 2017-08-01 | Synopsys, Inc. | Information theoretic caching for dynamic problem generation in constraint solving |
US8904320B2 (en) | 2013-03-13 | 2014-12-02 | Synopsys, Inc. | Solving multiplication constraints by factorization |
CN104462625B (en) * | 2013-09-23 | 2017-08-22 | 广州汽车集团股份有限公司 | A kind of automotive suspension kinetic model calibration method |
CN105160135B (en) * | 2015-10-08 | 2019-08-23 | 中国飞机强度研究所 | A method of calculating testpieces test data and analysis data consistency |
US10438682B2 (en) | 2017-12-21 | 2019-10-08 | International Business Machines Corporation | List insertion in test segments with non-naturally aligned data boundaries |
CN110175019B (en) * | 2019-06-04 | 2021-11-16 | 南京大学 | Interrupt driving system verification method based on interrupt sequence diagram |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1998055879A1 (en) * | 1997-06-03 | 1998-12-10 | Verisity Ltd. | Method and apparatus for test generation during circuit design |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04278475A (en) * | 1990-12-26 | 1992-10-05 | Internatl Business Mach Corp <Ibm> | Method and system for generation and simulation of look-ahead pattern |
US5377201A (en) * | 1991-06-18 | 1994-12-27 | Nec Research Institute, Inc. | Transitive closure based process for generating test vectors for VLSI circuit |
GB2278213A (en) * | 1993-05-18 | 1994-11-23 | Ibm | Test program generator. |
US6178533B1 (en) * | 1997-06-30 | 2001-01-23 | Sun Microsystems, Inc. | Method and system for design verification |
US6141630A (en) * | 1997-08-07 | 2000-10-31 | Verisity Design, Inc. | System and method for automated design verification |
US6212667B1 (en) * | 1998-07-30 | 2001-04-03 | International Business Machines Corporation | Integrated circuit test coverage evaluation and adjustment mechanism and method |
US6467058B1 (en) * | 1999-01-20 | 2002-10-15 | Nec Usa, Inc. | Segmented compaction with pruning and critical fault elimination |
US6341361B1 (en) * | 1999-06-01 | 2002-01-22 | Advanced Micro Devices, Inc. | Graphical user interface for testability operation |
US6484135B1 (en) * | 1999-08-30 | 2002-11-19 | Hewlett-Packard Company | Method for adaptive test generation via feedback from dynamic emulation |
-
2001
- 2001-03-06 US US09/799,066 patent/US6684359B2/en not_active Expired - Lifetime
- 2001-10-31 JP JP2002540016A patent/JP2004513435A/en active Pending
- 2001-10-31 IL IL15569201A patent/IL155692A0/en unknown
- 2001-10-31 EP EP01982688A patent/EP1374103A2/en not_active Ceased
- 2001-10-31 WO PCT/IL2001/001011 patent/WO2002037340A2/en not_active Application Discontinuation
- 2001-10-31 AU AU2002214229A patent/AU2002214229A1/en not_active Abandoned
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1998055879A1 (en) * | 1997-06-03 | 1998-12-10 | Verisity Ltd. | Method and apparatus for test generation during circuit design |
Non-Patent Citations (3)
Title |
---|
AHARON A ET AL: "VERIFICATION OF THE IBM RISC SYSTEM/6000 BY A DYNAMIC BIASED PSEUDO-RANDOM TEST PROGRAM GENERATOR" IBM SYSTEMS JOURNAL, IBM CORP. ARMONK, NEW YORK, US, vol. 30, no. 4, 1991, pages 527-538, XP000263591 ISSN: 0018-8670 * |
BISWAS P ET AL: "Functional verification of the superscalar SH-4 microprocessor" COMPCON '97. PROCEEDINGS, IEEE SAN JOSE, CA, USA 23-26 FEB. 1997, LOS ALAMITOS, CA, USA,IEEE COMPUT. SOC, US, 23 February 1997 (1997-02-23), pages 115-120, XP010219520 ISBN: 0-8186-7804-6 * |
LEWIN D ET AL: "A methodology for processor implementation verification" FORMAL METHODS IN COMPUTER-AIDED DESIGN. FIRST INTERNATIONAL CONFERENCE, FMCAD '96 PROCEEDINGS, PROCEEDINGS OF INTERNATIONAL CONFERENCE ON FORMAL METHODS IN COMPUTER-AIDED DESIGN (FMCAD - SUCCESSOR TO TPCD), PALO ALTO, CA, USA, 6-8 NOV. 1996, pages 126-142, XP002231570 1996, Berlin, Germany, Springer-Verlag, Germany ISBN: 3-540-61937-2 * |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN111125996A (en) * | 2019-12-10 | 2020-05-08 | 上海高性能集成电路设计中心 | Method for realizing instruction set based on bidirectional constraint tree of pseudo-random excitation generator |
CN111125996B (en) * | 2019-12-10 | 2023-04-07 | 上海高性能集成电路设计中心 | Method for realizing instruction set based on bidirectional constraint tree of pseudo-random excitation generator |
Also Published As
Publication number | Publication date |
---|---|
US20020166089A1 (en) | 2002-11-07 |
JP2004513435A (en) | 2004-04-30 |
US6684359B2 (en) | 2004-01-27 |
AU2002214229A1 (en) | 2002-05-15 |
WO2002037340A3 (en) | 2003-10-16 |
EP1374103A2 (en) | 2004-01-02 |
IL155692A0 (en) | 2003-11-23 |
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