WO2002037340A3 - System and method for test generation with dynamic constraints using static analysis - Google Patents
System and method for test generation with dynamic constraints using static analysis Download PDFInfo
- Publication number
- WO2002037340A3 WO2002037340A3 PCT/IL2001/001011 IL0101011W WO0237340A3 WO 2002037340 A3 WO2002037340 A3 WO 2002037340A3 IL 0101011 W IL0101011 W IL 0101011W WO 0237340 A3 WO0237340 A3 WO 0237340A3
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- dynamic
- constraints
- constraint
- test generation
- testing
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
- G01R31/318342—Generation of test inputs, e.g. test vectors, patterns or sequences by preliminary fault modelling, e.g. analysis, simulation
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
- Tests Of Electronic Circuits (AREA)
Abstract
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
AU2002214229A AU2002214229A1 (en) | 2000-11-03 | 2001-10-31 | System and method for test generation with dynamic constraints using static analysis |
JP2002540016A JP2004513435A (en) | 2000-11-03 | 2001-10-31 | System and method for dynamic constrained test generation using static analysis |
EP01982688A EP1374103A2 (en) | 2000-11-03 | 2001-10-31 | System and method for test generation with dynamic constraints using static analysis |
IL15569201A IL155692A0 (en) | 2000-11-03 | 2001-10-31 | System and method for test generation with dynamic constraints using static analysis |
IL155692A IL155692A (en) | 2000-11-03 | 2003-04-30 | System and method for test generation with dynamic constraints using static analysis |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US24514600P | 2000-11-03 | 2000-11-03 | |
US60/245,146 | 2000-11-03 | ||
US09/799,066 US6684359B2 (en) | 2000-11-03 | 2001-03-06 | System and method for test generation with dynamic constraints using static analysis |
US09/799,066 | 2001-03-06 |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2002037340A2 WO2002037340A2 (en) | 2002-05-10 |
WO2002037340A3 true WO2002037340A3 (en) | 2003-10-16 |
Family
ID=26937028
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/IL2001/001011 WO2002037340A2 (en) | 2000-11-03 | 2001-10-31 | System and method for test generation with dynamic constraints using static analysis |
Country Status (6)
Country | Link |
---|---|
US (1) | US6684359B2 (en) |
EP (1) | EP1374103A2 (en) |
JP (1) | JP2004513435A (en) |
AU (1) | AU2002214229A1 (en) |
IL (1) | IL155692A0 (en) |
WO (1) | WO2002037340A2 (en) |
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US20120331124A1 (en) * | 2011-06-22 | 2012-12-27 | Raman Ramteke Venkatesh | Constraint definition for capacity mangement |
US8560893B1 (en) * | 2011-10-21 | 2013-10-15 | Cadence Design Systems, Inc. | Systems and methods for automatically generating executable system level-tests from a partially specified scenario |
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US10438682B2 (en) | 2017-12-21 | 2019-10-08 | International Business Machines Corporation | List insertion in test segments with non-naturally aligned data boundaries |
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Citations (1)
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WO1998055879A1 (en) * | 1997-06-03 | 1998-12-10 | Verisity Ltd. | Method and apparatus for test generation during circuit design |
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-
2001
- 2001-03-06 US US09/799,066 patent/US6684359B2/en not_active Expired - Lifetime
- 2001-10-31 AU AU2002214229A patent/AU2002214229A1/en not_active Abandoned
- 2001-10-31 WO PCT/IL2001/001011 patent/WO2002037340A2/en not_active Application Discontinuation
- 2001-10-31 EP EP01982688A patent/EP1374103A2/en not_active Ceased
- 2001-10-31 IL IL15569201A patent/IL155692A0/en unknown
- 2001-10-31 JP JP2002540016A patent/JP2004513435A/en active Pending
Patent Citations (1)
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WO1998055879A1 (en) * | 1997-06-03 | 1998-12-10 | Verisity Ltd. | Method and apparatus for test generation during circuit design |
Non-Patent Citations (3)
Title |
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AHARON A ET AL: "VERIFICATION OF THE IBM RISC SYSTEM/6000 BY A DYNAMIC BIASED PSEUDO-RANDOM TEST PROGRAM GENERATOR", IBM SYSTEMS JOURNAL, IBM CORP. ARMONK, NEW YORK, US, vol. 30, no. 4, 1991, pages 527 - 538, XP000263591, ISSN: 0018-8670 * |
BISWAS P ET AL: "Functional verification of the superscalar SH-4 microprocessor", COMPCON '97. PROCEEDINGS, IEEE SAN JOSE, CA, USA 23-26 FEB. 1997, LOS ALAMITOS, CA, USA,IEEE COMPUT. SOC, US, 23 February 1997 (1997-02-23), pages 115 - 120, XP010219520, ISBN: 0-8186-7804-6 * |
LEWIN D ET AL: "A methodology for processor implementation verification", FORMAL METHODS IN COMPUTER-AIDED DESIGN. FIRST INTERNATIONAL CONFERENCE, FMCAD '96 PROCEEDINGS, PROCEEDINGS OF INTERNATIONAL CONFERENCE ON FORMAL METHODS IN COMPUTER-AIDED DESIGN (FMCAD - SUCCESSOR TO TPCD), PALO ALTO, CA, USA, 6-8 NOV. 1996, 1996, Berlin, Germany, Springer-Verlag, Germany, pages 126 - 142, XP002231570, ISBN: 3-540-61937-2 * |
Also Published As
Publication number | Publication date |
---|---|
AU2002214229A1 (en) | 2002-05-15 |
IL155692A0 (en) | 2003-11-23 |
JP2004513435A (en) | 2004-04-30 |
WO2002037340A2 (en) | 2002-05-10 |
US20020166089A1 (en) | 2002-11-07 |
EP1374103A2 (en) | 2004-01-02 |
US6684359B2 (en) | 2004-01-27 |
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