WO2002041246A3 - Video signal processing computer, cellular chip and method - Google Patents

Video signal processing computer, cellular chip and method Download PDF

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Publication number
WO2002041246A3
WO2002041246A3 PCT/HU2001/000113 HU0100113W WO0241246A3 WO 2002041246 A3 WO2002041246 A3 WO 2002041246A3 HU 0100113 W HU0100113 W HU 0100113W WO 0241246 A3 WO0241246 A3 WO 0241246A3
Authority
WO
WIPO (PCT)
Prior art keywords
video signals
output
input
signal processing
video signal
Prior art date
Application number
PCT/HU2001/000113
Other languages
French (fr)
Other versions
WO2002041246A2 (en
Inventor
Akos Zarandy
Tamas Roska
Original Assignee
Mta Szamitastechnikai Es Au
Akos Zarandy
Tamas Roska
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mta Szamitastechnikai Es Au, Akos Zarandy, Tamas Roska filed Critical Mta Szamitastechnikai Es Au
Priority to AU2002218423A priority Critical patent/AU2002218423A1/en
Publication of WO2002041246A2 publication Critical patent/WO2002041246A2/en
Publication of WO2002041246A3 publication Critical patent/WO2002041246A3/en

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/14—Picture signal circuitry for video frequency region

Abstract

A video signal processing computer, a cellular chip and methods are disclosed for converting one or more input video signals into one or more output video signals. A cellular network consisting of a plurality of programmable cells (30) is used for the conversion, wherein each of the programmable cells (30) is assigned to a respective pixel of a horizontal frame stripe extending over a number of video lines, wherein the stripe comprises a useful area and an overlapping area. Input memory elements are connected via controllable input switches (53) to conductor lines (51) carrying input video signals, and output memory elements are connected via controllable output switches (54) to conductor lines (52) carrying output video signals. The stripes located one below and overlapping one another in the overlapping areas are processed successively by reading in, processing and outputting analog values associated with the pixels.
PCT/HU2001/000113 2000-11-15 2001-11-15 Video signal processing computer, cellular chip and method WO2002041246A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU2002218423A AU2002218423A1 (en) 2000-11-15 2001-11-15 Video signal processing computer, cellular chip and method

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
HUP0004500 2000-11-15
HU0004500A HUP0004500A2 (en) 2000-11-15 2000-11-15 Computer for processing video signal, cellular chip and method for converting video signals

Publications (2)

Publication Number Publication Date
WO2002041246A2 WO2002041246A2 (en) 2002-05-23
WO2002041246A3 true WO2002041246A3 (en) 2002-07-25

Family

ID=89978763

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/HU2001/000113 WO2002041246A2 (en) 2000-11-15 2001-11-15 Video signal processing computer, cellular chip and method

Country Status (3)

Country Link
AU (1) AU2002218423A1 (en)
HU (1) HUP0004500A2 (en)
WO (1) WO2002041246A2 (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5355528A (en) * 1992-10-13 1994-10-11 The Regents Of The University Of California Reprogrammable CNN and supercomputer

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5355528A (en) * 1992-10-13 1994-10-11 The Regents Of The University Of California Reprogrammable CNN and supercomputer

Non-Patent Citations (5)

* Cited by examiner, † Cited by third party
Title
CARMONA R ET AL: "A 0.5 /spl mu/m CMOS CNN analog random access memory chip for massive image processing", CELLULAR NEURAL NETWORKS AND THEIR APPLICATIONS PROCEEDINGS, 1998 FIFTH IEEE INTERNATIONAL WORKSHOP ON LONDON, UK 14-17 APRIL 1998, NEW YORK, NY, USA,IEEE, US, PAGE(S) 271-276, ISBN: 0-7803-4867-2, XP010287725 *
EL-SHAFEI A A H ET AL: "A time-multiplexing simulator for cellular neural network", CELLULAR NEURAL NETWORKS AND THEIR APPLICATIONS PROCEEDINGS, 1998 FIFTH IEEE INTERNATIONAL WORKSHOP ON LONDON, UK 14-17 APRIL 1998, NEW YORK, NY, USA,IEEE, US, PAGE(S) 224-229, ISBN: 0-7803-4867-2, XP010287735 *
PINEDA DE GYVEZ J ET AL: "Large-image CNN hardware processing using a time multiplexing scheme", CELLULAR NEURAL NETWORKS AND THEIR APPLICATIONS, 1996. CNNA-96. PROCEEDINGS., 1996 FOURTH IEEE INTERNATIONAL WORKSHOP ON SEVILLE, SPAIN 24-26 JUNE 1996, NEW YORK, NY, USA,IEEE, US, PAGE(S) 405-410, ISBN: 0-7803-3261-X, XP010210282 *
RADVANYI A G ET AL: "A CNN solution for depth estimation from binocular stereo imagery", CELLULAR NEURAL NETWORKS AND THEIR APPLICATIONS PROCEEDINGS, 1998 FIFTH IEEE INTERNATIONAL WORKSHOP ON LONDON, UK 14-17 APRIL 1998, NEW YORK, NY, USA,IEEE, US, PAGE(S) 218-223, ISBN: 0-7803-4867-2, XP010287690 *
SLOT K ET AL: "Cellular neural network based VLSI architecture for image processing", CELLULAR NEURAL NETWORKS AND THEIR APPLICATIONS, 1996. CNNA-96. PROCEEDINGS., 1996 FOURTH IEEE INTERNATIONAL WORKSHOP ON SEVILLE, SPAIN 24-26 JUNE 1996, NEW YORK, NY, USA,IEEE, US, PAGE(S) 249-254, ISBN: 0-7803-3261-X, XP010210256 *

Also Published As

Publication number Publication date
AU2002218423A1 (en) 2002-05-27
WO2002041246A2 (en) 2002-05-23
HUP0004500A2 (en) 2002-06-29
HU0004500D0 (en) 2001-02-28

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