WO2002042782A1 - Method and apparatus for estimating the phase of a signal - Google Patents

Method and apparatus for estimating the phase of a signal Download PDF

Info

Publication number
WO2002042782A1
WO2002042782A1 PCT/GB2001/005095 GB0105095W WO0242782A1 WO 2002042782 A1 WO2002042782 A1 WO 2002042782A1 GB 0105095 W GB0105095 W GB 0105095W WO 0242782 A1 WO0242782 A1 WO 0242782A1
Authority
WO
WIPO (PCT)
Prior art keywords
signal
multiplied
predetermined relationship
magnitude
signals
Prior art date
Application number
PCT/GB2001/005095
Other languages
French (fr)
Inventor
Diego Giancola
Bhimantoro Yudho Prasetyo
Original Assignee
Ubinetics Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ubinetics Limited filed Critical Ubinetics Limited
Priority to DE60108416T priority Critical patent/DE60108416T2/en
Priority to EP01997701A priority patent/EP1336111B1/en
Priority to AT01997701T priority patent/ATE287090T1/en
Priority to JP2002545253A priority patent/JP3899027B2/en
Priority to AU2002223832A priority patent/AU2002223832A1/en
Priority to US10/432,319 priority patent/US6891362B2/en
Priority to KR1020037006843A priority patent/KR100817902B1/en
Publication of WO2002042782A1 publication Critical patent/WO2002042782A1/en

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R25/00—Arrangements for measuring phase angle between a voltage and a current or between voltages or currents
    • G01R25/08—Arrangements for measuring phase angle between a voltage and a current or between voltages or currents by counting of standard pulses
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/69—Spread spectrum techniques
    • H04B1/707—Spread spectrum techniques using direct sequence modulation
    • H04B1/7073—Synchronisation aspects
    • H04B1/7075—Synchronisation aspects with code phase acquisition
    • H04B1/70751—Synchronisation aspects with code phase acquisition using partial detection
    • H04B1/70753—Partial phase search
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/69—Spread spectrum techniques
    • H04B1/707—Spread spectrum techniques using direct sequence modulation
    • H04B1/7097—Interference-related aspects
    • H04B1/711—Interference-related aspects the interference being multi-path interference
    • H04B1/7115—Constructive combining of multi-path signals, i.e. RAKE receivers
    • H04B1/7117—Selection, re-selection, allocation or re-allocation of paths to fingers, e.g. timing offset control of allocated fingers

Definitions

  • This invention relates to a method for estimating the phase of a signal of interest, and to apparatus for estimating the phase of a signal of interest.
  • a method of estimating the phase rotation of a signal of interest from first and second signals comprising: a) determining whether a predetermined relationship exists between the magnitudes of the first and second signals; b) if the predetermined relationship is determined to exist, moving to step g); c) if the predetermined relationship does not exist, multiplying the first signal by a predetermined scaling factor to produce a multiplied signal; d) determining whether the predetermined relationship exists between the multiplied signal and the second signal; e) if the predetermined relationship does not exist between the multiplied signal and the second signal, multiplying the multiplied signal by the predetermined scaling factor; f) repeating steps d) and e) until the predetermined relationship exists; g) determining on how many occasions a signal was multiplied before the predetermined relationship came to exist; and h) estimating the phase rotation using the number of occasions of multiplication so determined.
  • apparatus for estimating the phase rotation of a signal of interest from first and second signals comprising: means for determining whether a predetermined relationship exists between the magnitudes of the first and second signals; means for, if the predetermined relationship does not exist, multiplying the first signal by a predetermined scaling factor to produce a multiplied signal; means for determining whether the predetermined relationship exists between the multiplied signal and the second signal; means for, if the predetermined relationship does not exist between the multiplied signal and the second signal, repeatedly multiplying the multiplied signal by the predetermined scaling factor until the predetermined relationship exists;
  • This invention allows frequency error mitigation to be accomplished without the extensive use of fixed point calculations and without using floating point calculations.
  • Figure 1 shows schematically part of a finger of a rake receiver to which the invention is applied
  • Figure 2 shows a flow diagram of a mathematical operation used to determine a frequency error in accordance with the invention.
  • Figure 3 shows the phase error obtained using the Figure 2 mathematical operation.
  • a finger 10 of a rake receiver to which the invention is applied is shown in Figure 1.
  • the finger 10 comprises generally a traffic channel 11 and a pilot channel 12.
  • a mixer 13 in the traffic channel 11 mixes an input signal, received from a schematic delay line 14, with a code provided by a scrambling code generator 15 and with a traffic channel specific code provided by a first ONSF code generator 16.
  • the resultant signal is fed to a first accumulator 17 and to a first-in-first-out (FIFO) buffer 18, in a conventional manner.
  • the input signal is mixed, in a second mixer 19, with the code provided by the scrambling code generator 15 and with a pilot channel specific code, generated by a second ONSF code generator 20.
  • This mixed signal is then accumulated in a second accumulator 21 over a period of time equal to 256 chips, or one symbol, of the scrambling code before being reset.
  • the reset period of the second accumulator is aligned with reset period of the ONSF code provided by the first ONSF code generator 16.
  • the resultant complex signals are fed to a second delay line 22 and, from there, to a complex multiplier 23 via a coherent phase reference device 24.
  • the complex multiplier 23 multiplies the output signals from the traffic channel 11 and the pilot channel 12, the result being provided to a coherent combiner (not shown) along with signals from other fingers (not shown) of the rake receiver.
  • the code generators 15, 16 and 20 are symbol locked with each other and run at code rate.
  • the complex value at a location P(n) in the second delay line 22 is provided to a first input of a multiplier 25.
  • the conjugate of a complex value at another location P(n+k) in the second delay line 22 is calculated by a conjugate calculation device 26, and the result provided a second input of the multiplier 25.
  • the multiplier 25 multiplies the two complex numbers it receives, and provides the resulting complex number at an output 27. Initially, the value of k is set to 2, the location P(n) then corresponding to an accumulation result two symbols subsequent to the location P(n+2).
  • the second delay line 22 operates in a rolling manner such that, when another accumulation result is provided by the second accumulator 21, this is fed through the second delay line and the multiplier 25 is then fed with signals from subsequent locations in the second delay line. A new complex number output is, therefore, provided every symbol.
  • the complex number output is a complex vector whose phase is a coherent measurement of the phase rotation occurring between the symbols corresponding to the locations P(n) and P(n+k).
  • the magnitude of the complex vector is proportional to the average power of the accumulation results from those two symbols.
  • the complex number provided by the multiplier is received at a processing block 30, which provides a first signal which is a 32 bit binary number showing the magnitude and the sign of the imaginary part of the output signal of the multiplier 25, and a second signal which is a 32 bit binary number showing the magnitude and sign of the real part of the output signal of the multiplier.
  • These first and second signals are passed to an initialisation block 31, from where they are passed both to a quadrant determination block 32 and to a comparator block 33.
  • the quadrant determination block 32 examines the signs of the first and second signals to determine the quadrant in which the phase of the input signal exists, and provides the result to an angle determination block 34.
  • the comparator block 33 determines if the magnitude of the first signal is greater than or equal to the magnitude of the second signal. If a negative determination is made, the magnitude of the first signal is doubled in a multiplication block 35 to form a multiplied signal, and a counter incremented from zero to one. Doubling is effected by a single leftwards bit shift of the first signal and by filling the last significant bit with a 'zero'. The comparator block 33 then determines if the multiplied signal is greater than or equal to the magnitude of the second signal. If a negative determination is again made, the multiplied signal is doubled in the multiplication block to provide a revised multiplied signal, and the counter is again incremented.
  • the process continues until the multiplied signal is equal to or exceeds the magnitude of the second signal, when progression is made to an upscaling block 36.
  • the information carried to the upscaling block 36 is the multiplied signal (or the first signal if there is no multiplied signal), the magnitude of the second signal and the count of the counter.
  • the count of the counter can be considered to be a multiplication factor. If the magnitude of the first signal was equal to or greater than the magnitude of the second signal i.e. no multiplied signals were calculated, the multiphcation factor is zero.
  • the upscaling block 36 examines the multiplied signal or the first signal, as the case may be, and determines how much the signal can be upscaled before it would exceed the limit imposed by the 32 bits assigned to accommodate the signals.
  • the degree of upscaling so determined is hereafter termed the upscaling factor.
  • the multiplied signal or the first signal, as the case may be, is multiplied by the scaling factor, as is the second signal, and the upscaled signals are provided to the angle determination block 34.
  • phase error ⁇ G in degrees is then estimated by the following formula:
  • FIG 3 shows how this estimated phase error differs from the actual phase error.
  • the tan of the phase 40 which is indicative of the true phase error, is shown next to a linear approximation 41 thereof.
  • the quantisation levels 42-44 result from the doubling and comparing effected by the multiplication block 35 and the comparing block 33.
  • the difference between the phase error obtained using the above formula and the actual phase error is shown at 45-47.
  • the calculated phase error is fed to an angle-to-frequency error conversion block 37, where a (possibly upscaled) frequency error f e is calculated using the following formula:
  • T m is the measurement period in chips (initially
  • This frequency error f e is then downscaled by dividing it by the upscaling factor in a downscaling block 38, and the resulting frequency error provided at an output.
  • the frequency error is fed back to control the frequency of an oscillator (not shown) forming part of the rake receiver.
  • the upscaling and subsequent downscaling results in improved accuracy of frequency error estimation since it reduces quantisation noise.
  • the downscaling block 38 is arranged such that it does not provide a frequency error signal which corresponds to a phase error in the region of -1° to +1°. If such a frequency error would be provided, the frequency error signal is increased incrementally until this criteria is met. Accordingly, once approximate convergence of the frequency of the received signals with the downconversion frequency effected in the rake receiver is reached, the error swings from one side of the true frequency to the other side, and so on.
  • the value of k is increased, so that the multiplier 25 receives signals which correspond to accumulation results spaced further apart in time. This allows more accurate phase, and therefore frequency, error signals to be calculated.
  • This invention allows a phase error, and therefore a frequency error, signal to be provided with relatively few fixed-point operations and with no floating-point operations.
  • the apparatus required is, therefore, of simpler construction than conventional digital phase and frequency error estimation apparatus.
  • the resultant frequency error signals are not, however, as accurate as those obtained conventionally, but the inventors see this as a disadvantage which is acceptable in view of the advantages obtained.
  • the invention can be used both with acquisition and with tracking of the carrier of received signals, and is not limited to use with code division multiple access receivers.

Abstract

An input signal is a complex vector whose phase is a coherent measurement of the phase rotation occurring between two separated symbols of a received CDMA signal. A processing block (30) provides a first signal showing the magnitude and the sign of the imaginary part of the input signal, and a second signal showing the magnitude and sign of the real part of the input signal to an initialisation block (31). A quadrant determination block (32) examines the signs of the signals to determine the quadrant in which the phase of the input signal exists. A comparator block (33) determines if the magnitude of the first signal is greater than or equal to the magnitude of the second signal. If a negative determination is made, the magnitude of the first signal is doubled in a multiplication block (35) to form a multiplied signal, and a counter incremented, initially from zero. The comparator block (33) then determines if the multiplied signal is greater than or equal to the magnitude of the second signal. This continues until the multiplied signal is equal to or exceeds the magnitude of the second signal. Carried to an upscaling block (36) is the multiplied signal (or the first signal if there is no multiplied signal), the magnitude of the second signal and the count of the counter (M). The upscaling block (36) examines the multiplied signal (or the first signal) and determines an upscaling factor. The multiplied signal (or the first signal) is multiplied by the scaling factor, as is the second signal, and the upscaled signals are provided to an angle determination block (34). The phase error υe in degrees is estimated by the formula υe=45°/2M.

Description

Method And Apparatus For Estimating The Phase Of A Signal
This invention relates to a method for estimating the phase of a signal of interest, and to apparatus for estimating the phase of a signal of interest.
In accordance with a first aspect of this invention, there is provided a method of estimating the phase rotation of a signal of interest from first and second signals, the method comprising: a) determining whether a predetermined relationship exists between the magnitudes of the first and second signals; b) if the predetermined relationship is determined to exist, moving to step g); c) if the predetermined relationship does not exist, multiplying the first signal by a predetermined scaling factor to produce a multiplied signal; d) determining whether the predetermined relationship exists between the multiplied signal and the second signal; e) if the predetermined relationship does not exist between the multiplied signal and the second signal, multiplying the multiplied signal by the predetermined scaling factor; f) repeating steps d) and e) until the predetermined relationship exists; g) determining on how many occasions a signal was multiplied before the predetermined relationship came to exist; and h) estimating the phase rotation using the number of occasions of multiplication so determined.
hi accordance with a second aspect of this invention, there is provided apparatus for estimating the phase rotation of a signal of interest from first and second signals, the apparatus comprising: means for determining whether a predetermined relationship exists between the magnitudes of the first and second signals; means for, if the predetermined relationship does not exist, multiplying the first signal by a predetermined scaling factor to produce a multiplied signal; means for determining whether the predetermined relationship exists between the multiplied signal and the second signal; means for, if the predetermined relationship does not exist between the multiplied signal and the second signal, repeatedly multiplying the multiplied signal by the predetermined scaling factor until the predetermined relationship exists;
. means for determining on how many occasions a signal was multiplied before the predetermined relationship came to exist; and means responsive to the number of occasions of multiplication so determined for estimating the phase rotation.
This invention allows frequency error mitigation to be accomplished without the extensive use of fixed point calculations and without using floating point calculations.
Embodiments of the present invention will now be described, by way of example only, with reference to the accompanying drawings, in which:
Figure 1 shows schematically part of a finger of a rake receiver to which the invention is applied;
Figure 2 shows a flow diagram of a mathematical operation used to determine a frequency error in accordance with the invention; and
Figure 3 shows the phase error obtained using the Figure 2 mathematical operation.
A finger 10 of a rake receiver to which the invention is applied is shown in Figure 1. Referring to Figure 1, the finger 10 comprises generally a traffic channel 11 and a pilot channel 12. A mixer 13 in the traffic channel 11 mixes an input signal, received from a schematic delay line 14, with a code provided by a scrambling code generator 15 and with a traffic channel specific code provided by a first ONSF code generator 16. The resultant signal is fed to a first accumulator 17 and to a first-in-first-out (FIFO) buffer 18, in a conventional manner. In the pilot channel 12, the input signal is mixed, in a second mixer 19, with the code provided by the scrambling code generator 15 and with a pilot channel specific code, generated by a second ONSF code generator 20. This mixed signal is then accumulated in a second accumulator 21 over a period of time equal to 256 chips, or one symbol, of the scrambling code before being reset. The reset period of the second accumulator is aligned with reset period of the ONSF code provided by the first ONSF code generator 16. The resultant complex signals are fed to a second delay line 22 and, from there, to a complex multiplier 23 via a coherent phase reference device 24. The complex multiplier 23 multiplies the output signals from the traffic channel 11 and the pilot channel 12, the result being provided to a coherent combiner (not shown) along with signals from other fingers (not shown) of the rake receiver.
The code generators 15, 16 and 20 are symbol locked with each other and run at code rate.
The complex value at a location P(n) in the second delay line 22 is provided to a first input of a multiplier 25. The conjugate of a complex value at another location P(n+k) in the second delay line 22 is calculated by a conjugate calculation device 26, and the result provided a second input of the multiplier 25. The multiplier 25 multiplies the two complex numbers it receives, and provides the resulting complex number at an output 27. Initially, the value of k is set to 2, the location P(n) then corresponding to an accumulation result two symbols subsequent to the location P(n+2). The second delay line 22 operates in a rolling manner such that, when another accumulation result is provided by the second accumulator 21, this is fed through the second delay line and the multiplier 25 is then fed with signals from subsequent locations in the second delay line. A new complex number output is, therefore, provided every symbol.
The complex number output is a complex vector whose phase is a coherent measurement of the phase rotation occurring between the symbols corresponding to the locations P(n) and P(n+k). The magnitude of the complex vector is proportional to the average power of the accumulation results from those two symbols. Referring now to Figure 2, the complex number provided by the multiplier is received at a processing block 30, which provides a first signal which is a 32 bit binary number showing the magnitude and the sign of the imaginary part of the output signal of the multiplier 25, and a second signal which is a 32 bit binary number showing the magnitude and sign of the real part of the output signal of the multiplier. These first and second signals are passed to an initialisation block 31, from where they are passed both to a quadrant determination block 32 and to a comparator block 33. The quadrant determination block 32 examines the signs of the first and second signals to determine the quadrant in which the phase of the input signal exists, and provides the result to an angle determination block 34.
The comparator block 33 determines if the magnitude of the first signal is greater than or equal to the magnitude of the second signal. If a negative determination is made, the magnitude of the first signal is doubled in a multiplication block 35 to form a multiplied signal, and a counter incremented from zero to one. Doubling is effected by a single leftwards bit shift of the first signal and by filling the last significant bit with a 'zero'. The comparator block 33 then determines if the multiplied signal is greater than or equal to the magnitude of the second signal. If a negative determination is again made, the multiplied signal is doubled in the multiplication block to provide a revised multiplied signal, and the counter is again incremented. This process continues until the multiplied signal is equal to or exceeds the magnitude of the second signal, when progression is made to an upscaling block 36. The information carried to the upscaling block 36 is the multiplied signal (or the first signal if there is no multiplied signal), the magnitude of the second signal and the count of the counter. The count of the counter can be considered to be a multiplication factor. If the magnitude of the first signal was equal to or greater than the magnitude of the second signal i.e. no multiplied signals were calculated, the multiphcation factor is zero.
The upscaling block 36 examines the multiplied signal or the first signal, as the case may be, and determines how much the signal can be upscaled before it would exceed the limit imposed by the 32 bits assigned to accommodate the signals. The degree of upscaling so determined is hereafter termed the upscaling factor. The multiplied signal or the first signal, as the case may be, is multiplied by the scaling factor, as is the second signal, and the upscaled signals are provided to the angle determination block 34.
The phase error ΘG in degrees, is then estimated by the following formula:
0e = 45° / 2]
where M is the count of the counter.
Figure 3 shows how this estimated phase error differs from the actual phase error. Referring to Figure 3, the tan of the phase 40, which is indicative of the true phase error, is shown next to a linear approximation 41 thereof. The quantisation levels 42-44 result from the doubling and comparing effected by the multiplication block 35 and the comparing block 33. The difference between the phase error obtained using the above formula and the actual phase error is shown at 45-47.
Referring again to Figure 2, the calculated phase error is fed to an angle-to-frequency error conversion block 37, where a (possibly upscaled) frequency error fe is calculated using the following formula:
θe fe IπiTmIC)
Where θe is the calculated phase error, Tm is the measurement period in chips (initially
512 chips), and C is the chip rate. The frequency error fe is rounded down to the nearest integer.
This frequency error fe is then downscaled by dividing it by the upscaling factor in a downscaling block 38, and the resulting frequency error provided at an output. The frequency error is fed back to control the frequency of an oscillator (not shown) forming part of the rake receiver. The upscaling and subsequent downscaling results in improved accuracy of frequency error estimation since it reduces quantisation noise.
The downscaling block 38 is arranged such that it does not provide a frequency error signal which corresponds to a phase error in the region of -1° to +1°. If such a frequency error would be provided, the frequency error signal is increased incrementally until this criteria is met. Accordingly, once approximate convergence of the frequency of the received signals with the downconversion frequency effected in the rake receiver is reached, the error swings from one side of the true frequency to the other side, and so on.
Once convergence is reached, the value of k is increased, so that the multiplier 25 receives signals which correspond to accumulation results spaced further apart in time. This allows more accurate phase, and therefore frequency, error signals to be calculated.
This invention allows a phase error, and therefore a frequency error, signal to be provided with relatively few fixed-point operations and with no floating-point operations. The apparatus required is, therefore, of simpler construction than conventional digital phase and frequency error estimation apparatus. The resultant frequency error signals are not, however, as accurate as those obtained conventionally, but the inventors see this as a disadvantage which is acceptable in view of the advantages obtained. The invention can be used both with acquisition and with tracking of the carrier of received signals, and is not limited to use with code division multiple access receivers.
Although the invention has been described with the multiplication block providing a doubling function, other scaling factors are possible, such as four and eight, although larger seating factors result in decreased accuracy.

Claims

Claims
1. A method of estimating the phase rotation of a signal of interest from first and second signals, the method comprising: a) determining whether a predetermined relationship exists between the magnitudes of the first and second signals; b) if the predetermined relationship is determined to exist, moving to step g); c) if the predetermined relationship does not exist, multiplying the first signal by a predetermined scaling factor to produce a multiplied signal; d) determining whether the predetermined relationship exists between the multiplied signal and the second signal; e) if the predetermined relationship does not exist between the multiplied signal and the second signal, multiplying the multiplied signal by the predetermined scaling factor; f) repeating steps d) and e) until the predetermined relationship exists; g) determining on how many occasions a signal was multiplied before the predetermined relationship came to exist; and h) estimating the phase using the number of occasions of multiphcation so determined.
2. A method according to claim 1, wherein the predetermined relationship exists when the magnitude of the first signal is greater than, or is greater than or equal to, the magnitude of the second signal.
3. A method according to any preceding claim, wherein the first and second signals are provided by: mixing a signal having a known data sequence with a de-spreading code; accumulating the mixed signal over a first period of time to provide a first complex value; accumulating the mixed signal over a second period of time, separated from the first period of time, to provide a second complex value; multiplying the first complex value by the conjugate of the' second complex value; taking the real part of the multiplication result as the second signal; and taking the imaginary part of the multiplication result as the first signal.
5. A method according to any preceding claim, further comprising determining the quadrant of the phase of the signal of interest by examining the signs of the first and second signals.
6. A method according to any preceding claim, further comprising adjusting the separation of the first and second periods of time.
7. A method according to any preceding claim, further comprising upscaling the second signal, and upscaling the first signal or, if the first signal was multiplied before the predetermined relationship existed, upscaling the multiplied signal which resulted in the predetermined relationship existing.
8. Apparatus for estimating the phase rotation of a signal of interest from first and second signals, the apparatus comprising: means for determining whether a predetermined relationship exists between the magnitudes of the first and second signals; means for, if the predetermined relationship does not exist, multiplying the first signal by a predetermined scaling factor to produce a multiphed signal; means for determining whether the predetermined relationship exists between the multiplied signal and the second signal; means for, if the predetermined relationship does not exist between the multiplied signal and the second signal, repeatedly multiplying the multiphed signal by the predetermined scaling factor until the predetermined relationship exists; means for determining on how many occasions a signal was multiplied before the predetermined relationship came to exist; and means responsive to the number of occasions of multiplication so determined for estimating the phase rotation.
9. Apparatus according to claim 8, wherein the means for determining whether predetermined relationship exists comprises means for detecting when the magnitude of the first signal is greater than, or is greater than or equal to, the magnitude of the second signal.
10. Apparatus according to claim 8 or claim 9, further comprising means to provide the first and second signals, the means comprising: a mixer for mixing a signal having a known data sequence with a de-spreading code; an accumulator for accumulating the mixed signal over a first period of time to provide a first complex value and for accumulating the mixed signal over a second period of time, separated from the first period of time, to provide a second complex value; means for multiplying the first complex value by the conjugate of the second complex value; means for taking the real part of the multiplication result as the second signal; and means for taking the imaginary part of the multiplication result as the first signal.
11. Apparatus according to any of claims 8 to 10, further comprising means for examining the signs of the first and second signals to determine the quadrant of the phase of the signal of interest.
12. Apparatus according to any of claims 8 to 11, further comprising means for adjusting the separation of the first and second periods of time.
13. Apparatus according to any of claims 8 to 12 further comprising means for upscaling the second signal, and means for upscaling the first signal or, if it is determined that the first signal was multiplied before the predetermined relationship existed, upscaling the multiplied signal which resulted in the predetermined relationship existing.
PCT/GB2001/005095 2000-11-21 2001-11-19 Method and apparatus for estimating the phase of a signal WO2002042782A1 (en)

Priority Applications (7)

Application Number Priority Date Filing Date Title
DE60108416T DE60108416T2 (en) 2000-11-21 2001-11-19 METHOD AND DEVICE FOR ASSESSING THE PHASE OF A SIGNAL
EP01997701A EP1336111B1 (en) 2000-11-21 2001-11-19 Method and apparatus for estimating the phase of a signal
AT01997701T ATE287090T1 (en) 2000-11-21 2001-11-19 METHOD AND DEVICE FOR ESTIMATING THE PHASE OF A SIGNAL
JP2002545253A JP3899027B2 (en) 2000-11-21 2001-11-19 Method and apparatus for estimating signal phase
AU2002223832A AU2002223832A1 (en) 2000-11-21 2001-11-19 Method and apparatus for estimating the phase of a signal
US10/432,319 US6891362B2 (en) 2000-11-21 2001-11-19 Method and apparatus for estimating the phase of a signal
KR1020037006843A KR100817902B1 (en) 2000-11-21 2001-11-19 Method and apparatus for estimating the phase of a signal

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB0028373A GB2369190B (en) 2000-11-21 2000-11-21 Method and apparatus for estimating the phase of a signal
GB0028373.9 2000-11-21

Publications (1)

Publication Number Publication Date
WO2002042782A1 true WO2002042782A1 (en) 2002-05-30

Family

ID=9903587

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/GB2001/005095 WO2002042782A1 (en) 2000-11-21 2001-11-19 Method and apparatus for estimating the phase of a signal

Country Status (10)

Country Link
US (1) US6891362B2 (en)
EP (1) EP1336111B1 (en)
JP (1) JP3899027B2 (en)
KR (1) KR100817902B1 (en)
CN (1) CN1265203C (en)
AT (1) ATE287090T1 (en)
AU (1) AU2002223832A1 (en)
DE (1) DE60108416T2 (en)
GB (1) GB2369190B (en)
WO (1) WO2002042782A1 (en)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101509943B (en) * 2008-12-25 2011-06-15 北京握奇数据系统有限公司 Phase detecting method and apparatus
KR101040262B1 (en) 2010-09-01 2011-06-10 엘아이지넥스원 주식회사 Broadband digital frequency tracking method
CN103760416B (en) * 2013-12-23 2016-05-18 中国科学院等离子体物理研究所 A kind of directional coupler is measured the error analysis method of High-Power Microwave phase place
CN103760419B (en) * 2014-02-18 2016-03-23 国家电网公司 The phase angle measurement method of transmission line of electricity electric current and voltage
CN105092967B (en) * 2015-07-09 2018-03-20 广东电网有限责任公司电力科学研究院 The frequency detecting method and system of electric power signal
CN105004925B (en) * 2015-07-09 2018-01-30 广东电网有限责任公司电力科学研究院 The all phase difference detection method and system of electric power signal
CN105319442B (en) * 2015-09-18 2018-05-04 广东电网有限责任公司电力科学研究院 The frequency power signal detection method and system modulated according to cosine function
CN105158558B (en) * 2015-09-18 2018-04-03 广东电网有限责任公司电力科学研究院 The frequency detecting method and system of electric power signal
CN105301355B (en) * 2015-09-18 2018-04-03 广东电网有限责任公司电力科学研究院 The frequency power signal detection method and system modulated according to SIN function

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4607218A (en) * 1983-03-03 1986-08-19 Wild Heerbrugg Ag Digital phase measurement method
US5787124A (en) * 1995-11-21 1998-07-28 Advantest Corporation Quadrature detector and amplitude error correction method for quadrature detector
US5856920A (en) * 1997-05-30 1999-01-05 Square D Company Method and apparatus for estimating a phase error between two independent timebases
WO1999018691A1 (en) * 1997-10-08 1999-04-15 Tropian, Inc. Digital phase discrimination based on frequency sampling

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3691474A (en) * 1970-12-04 1972-09-12 Burroughs Corp Phase detector initializer for oscillator synchronization
US5001724A (en) * 1989-01-13 1991-03-19 Hewlett-Packard Company Method and apparatus for measuring phase accuracy and amplitude profile of a continuous-phase-modulated signal
GB9311373D0 (en) * 1993-06-02 1993-07-21 Roke Manor Research Apparatus for use in equipment providing a digital radio link between a fixed and a mobile radio unit
US6097768A (en) * 1996-11-21 2000-08-01 Dps Group, Inc. Phase detector for carrier recovery in a DQPSK receiver
US6128584A (en) * 1998-11-30 2000-10-03 Abb Power T&D Company Inc. System and method for frequency compensation in an energy meter
KR100333704B1 (en) * 1999-06-21 2002-04-24 박종섭 modified circuit of decision region for phase rotation error caused by phase noise
US6787124B2 (en) 2002-03-15 2004-09-07 Exxonmobil Research And Engineering Company Synthetic porous crystalline material, EMM-1, its synthesis and use

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4607218A (en) * 1983-03-03 1986-08-19 Wild Heerbrugg Ag Digital phase measurement method
US5787124A (en) * 1995-11-21 1998-07-28 Advantest Corporation Quadrature detector and amplitude error correction method for quadrature detector
US5856920A (en) * 1997-05-30 1999-01-05 Square D Company Method and apparatus for estimating a phase error between two independent timebases
WO1999018691A1 (en) * 1997-10-08 1999-04-15 Tropian, Inc. Digital phase discrimination based on frequency sampling

Also Published As

Publication number Publication date
JP3899027B2 (en) 2007-03-28
JP2004515141A (en) 2004-05-20
EP1336111A1 (en) 2003-08-20
AU2002223832A1 (en) 2002-06-03
GB2369190B (en) 2004-07-14
GB0028373D0 (en) 2001-01-03
US6891362B2 (en) 2005-05-10
US20040032245A1 (en) 2004-02-19
GB2369190A (en) 2002-05-22
CN1265203C (en) 2006-07-19
KR20030051855A (en) 2003-06-25
KR100817902B1 (en) 2008-03-31
DE60108416D1 (en) 2005-02-17
EP1336111B1 (en) 2005-01-12
DE60108416T2 (en) 2005-12-29
ATE287090T1 (en) 2005-01-15
CN1476538A (en) 2004-02-18

Similar Documents

Publication Publication Date Title
US6463091B1 (en) Spread spectrum receiver using a pseudo-random noise code for ranging applications in a way that reduces errors when a multipath signal is present
EP1071966B1 (en) Matched Filter
JP2705613B2 (en) Frequency offset correction device
US7738606B2 (en) System and method for making correlation measurements utilizing pulse shape measurements
US7545854B1 (en) Doppler corrected spread spectrum matched filter
EP0488739A1 (en) Multi-channel digital receiver for global positioning system
EP0131260B1 (en) An arrangement to provide an accurate time-of-arrival indication for a received signal
EP2294518A2 (en) Adaptive correlation
EP0843828B1 (en) Multipath error reduction in a spread spectrum receiver for ranging applications
EP1336111B1 (en) Method and apparatus for estimating the phase of a signal
US8855171B2 (en) Satellite signal acquisition
CN102378921A (en) Method and apparatus for software GPS receiver
US7317752B2 (en) Method and system for locating a GPS correlated peak signal
EP0788225A1 (en) Frequency offset estimating circuit and AFC circuit using the same
US20030174792A1 (en) Gated time division multiplexed spread spectrum correlator
US6760592B2 (en) System and method for cyclic carrier de-rotation for earliest time of arrival estimation in a wireless communications system
CN101109802B (en) Method and apparatus for determining boundaries of information elements
JPWO2011001601A1 (en) Carrier frequency synchronization detection circuit and correlation calculator
US8149900B2 (en) Low complexity acquisition method for GNSS
US6683923B1 (en) Method and apparatus for detecting and tracking coded signals in a noisy background environment
EP1507377B1 (en) Automatic frequency control with symbol error detection
WO2001042973A1 (en) Method and apparatus for digital correlation
RU2153770C1 (en) Method of reception of wide-band signal and device for its realization ( versions )
JP2005031072A (en) Search method of gps correlated peak signal and system therefor

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A1

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EC EE ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NO NZ OM PH PL PT RO RU SD SE SG SI SK SL TJ TM TR TT TZ UA UG US UZ VN YU ZA ZM ZW

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): GH GM KE LS MW MZ SD SL SZ TZ UG ZM ZW AM AZ BY KG KZ MD RU TJ TM AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG

121 Ep: the epo has been informed by wipo that ep was designated in this application
WWE Wipo information: entry into national phase

Ref document number: 2001997701

Country of ref document: EP

WWE Wipo information: entry into national phase

Ref document number: 2002545253

Country of ref document: JP

Ref document number: 018192378

Country of ref document: CN

Ref document number: 1020037006843

Country of ref document: KR

WWE Wipo information: entry into national phase

Ref document number: 10432319

Country of ref document: US

WWP Wipo information: published in national office

Ref document number: 1020037006843

Country of ref document: KR

WWP Wipo information: published in national office

Ref document number: 2001997701

Country of ref document: EP

REG Reference to national code

Ref country code: DE

Ref legal event code: 8642

WWG Wipo information: grant in national office

Ref document number: 2001997701

Country of ref document: EP

DPE2 Request for preliminary examination filed before expiration of 19th month from priority date (pct application filed from 20040101)