WO2002043152A3 - Poly fuse rom - Google Patents
Poly fuse rom Download PDFInfo
- Publication number
- WO2002043152A3 WO2002043152A3 PCT/EP2001/013467 EP0113467W WO0243152A3 WO 2002043152 A3 WO2002043152 A3 WO 2002043152A3 EP 0113467 W EP0113467 W EP 0113467W WO 0243152 A3 WO0243152 A3 WO 0243152A3
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- fuse element
- gate
- terminal
- surrounds
- fuse
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
- G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
- G11C17/18—Auxiliary circuits, e.g. for writing into memory
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
- G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
- G11C17/16—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
- H01L23/4824—Pads with extended contours, e.g. grid structure, branch structure, finger structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B20/00—Read-only memory [ROM] devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B20/00—Read-only memory [ROM] devices
- H10B20/20—Programmable ROM [PROM] devices comprising field-effect components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
- H01L23/5256—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B20/00—Read-only memory [ROM] devices
- H10B20/27—ROM only
- H10B20/30—ROM only having the source region and the drain region on the same level, e.g. lateral transistors
Abstract
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2002544786A JP2004515061A (en) | 2000-11-27 | 2001-11-19 | Poly-fuse ROM having cell structure based on MOS device and method of reading and writing the same |
EP01997848A EP1340262A2 (en) | 2000-11-27 | 2001-11-19 | Poly fuse rom with mos device based cell structure and the method for read and write therefore |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US72341300A | 2000-11-27 | 2000-11-27 | |
US09/723,413 | 2000-11-27 |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2002043152A2 WO2002043152A2 (en) | 2002-05-30 |
WO2002043152A3 true WO2002043152A3 (en) | 2002-09-19 |
Family
ID=24906158
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/EP2001/013467 WO2002043152A2 (en) | 2000-11-27 | 2001-11-19 | Poly fuse rom |
Country Status (4)
Country | Link |
---|---|
EP (1) | EP1340262A2 (en) |
JP (1) | JP2004515061A (en) |
TW (1) | TWI268603B (en) |
WO (1) | WO2002043152A2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101780828B1 (en) | 2012-02-06 | 2017-09-22 | 매그나칩 반도체 유한회사 | Nonvolatile memory device |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
ATE430979T1 (en) | 2002-12-05 | 2009-05-15 | Nxp Bv | PROGRAMMABLE NON-VOLATILE SEMICONDUCTOR MEMORY ARRANGEMENT |
US7136322B2 (en) * | 2004-08-05 | 2006-11-14 | Analog Devices, Inc. | Programmable semi-fusible link read only memory and method of margin testing same |
GB0516423D0 (en) * | 2005-08-10 | 2005-09-14 | Cavendish Kinetics Ltd | Fuse cell, array and circuit therefor |
KR101211213B1 (en) * | 2005-08-31 | 2012-12-11 | 인터내셔널 비지네스 머신즈 코포레이션 | Random access electrically programmable e-fuse rom |
US20140027778A1 (en) * | 2012-07-25 | 2014-01-30 | International Rectifier Corporation | Robust Fused Transistor |
US9922720B2 (en) * | 2013-03-07 | 2018-03-20 | Intel Corporation | Random fuse sensing |
EP3382712B1 (en) | 2017-03-31 | 2020-11-04 | Nxp B.V. | Memory system |
FR3087290B1 (en) | 2018-10-16 | 2020-11-06 | St Microelectronics Sa | MEMORY POINT |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4517583A (en) * | 1981-03-03 | 1985-05-14 | Tokyo Shibaura Denki Kabushiki Kaisha | Semiconductor integrated circuit including a fuse element |
US5748025A (en) * | 1996-03-29 | 1998-05-05 | Intel Corporation | Method and apparatus for providing high voltage with a low voltage CMOS integrated circuit |
WO1998035387A1 (en) * | 1997-02-11 | 1998-08-13 | Actel Corporation | Antifuse programmed prom cell |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5553462A (en) | 1978-10-13 | 1980-04-18 | Int Rectifier Corp | Mosfet element |
JPS5863147A (en) * | 1981-10-09 | 1983-04-14 | Toshiba Corp | Semiconductor device |
JPS58197874A (en) * | 1982-05-14 | 1983-11-17 | Nec Corp | Semiconductor device and manufacture thereof |
JP3158738B2 (en) * | 1992-08-17 | 2001-04-23 | 富士電機株式会社 | High breakdown voltage MIS field-effect transistor and semiconductor integrated circuit |
US5412593A (en) * | 1994-01-12 | 1995-05-02 | Texas Instruments Incorporated | Fuse and antifuse reprogrammable link for integrated circuits |
US5976943A (en) * | 1996-12-27 | 1999-11-02 | Vlsi Technology, Inc. | Method for bi-layer programmable resistor |
JPH1187696A (en) * | 1997-09-12 | 1999-03-30 | Matsushita Electric Works Ltd | High breakdown strength semiconductor device |
-
2001
- 2001-11-19 WO PCT/EP2001/013467 patent/WO2002043152A2/en active Application Filing
- 2001-11-19 JP JP2002544786A patent/JP2004515061A/en active Pending
- 2001-11-19 EP EP01997848A patent/EP1340262A2/en not_active Withdrawn
-
2002
- 2002-01-03 TW TW091100020A patent/TWI268603B/en not_active IP Right Cessation
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4517583A (en) * | 1981-03-03 | 1985-05-14 | Tokyo Shibaura Denki Kabushiki Kaisha | Semiconductor integrated circuit including a fuse element |
US5748025A (en) * | 1996-03-29 | 1998-05-05 | Intel Corporation | Method and apparatus for providing high voltage with a low voltage CMOS integrated circuit |
WO1998035387A1 (en) * | 1997-02-11 | 1998-08-13 | Actel Corporation | Antifuse programmed prom cell |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101780828B1 (en) | 2012-02-06 | 2017-09-22 | 매그나칩 반도체 유한회사 | Nonvolatile memory device |
Also Published As
Publication number | Publication date |
---|---|
WO2002043152A2 (en) | 2002-05-30 |
TWI268603B (en) | 2006-12-11 |
EP1340262A2 (en) | 2003-09-03 |
JP2004515061A (en) | 2004-05-20 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US9418754B2 (en) | Anti-fuse type one-time programmable memory cell and anti-fuse type one-time programmable memory cell arrays | |
US5909049A (en) | Antifuse programmed PROM cell | |
JP2717051B2 (en) | Transistor antifuse for programmable ROM | |
EP1743380B1 (en) | Split-channel antifuse array architecture | |
CN101807580B (en) | Multiple time programmable non-volatile memory device with thick gate oxide | |
KR0150224B1 (en) | Semiconductor integrated circuit device and its making method | |
KR101523138B1 (en) | Programmable memory | |
US7741697B2 (en) | Semiconductor device structure for anti-fuse | |
US8743585B2 (en) | Semiconductor device with one-time programmable memory cell including anti-fuse with metal/polycide gate | |
US6670824B2 (en) | Integrated polysilicon fuse and diode | |
TW200518284A (en) | Nonvolatile semiconductor memory device and method of manufacturing the same | |
WO2002043152A3 (en) | Poly fuse rom | |
US8509023B2 (en) | Method and system for split threshold voltage programmable bitcells | |
JPH0729999A (en) | Nonvolatile semiconductor memory device and its manufacturing method | |
US20170186756A1 (en) | Anti-fuse type nonvolatile memory cells, arrays thereof, and methods of operating the same | |
KR900005604A (en) | Semiconductor integrated circuit device and its manufacturing method | |
JPH1056086A (en) | Nand cell array and its formation method | |
KR960015922A (en) | Nonvolatile Semiconductor Memory Formed with Silicon Structure on Insulator | |
US6268622B1 (en) | Non-volatile memory device and fabrication method thereof | |
WO2004055866A3 (en) | Programmable interconnect cell for configuring a field programmable gate array | |
JP3954209B2 (en) | Open drain input / output terminal structure of semiconductor device and manufacturing method thereof | |
KR100360398B1 (en) | Cell array region of NOR-type Mask ROM device and method for fabricating the same | |
TW200733363A (en) | Non-volatile memory cell and method of making the same | |
JP2005150677A (en) | High voltage transistor of flash memory | |
JPH0770628B2 (en) | Semiconductor device and manufacturing method thereof |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AK | Designated states |
Kind code of ref document: A2 Designated state(s): JP |
|
AL | Designated countries for regional patents |
Kind code of ref document: A2 Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE TR |
|
WWE | Wipo information: entry into national phase |
Ref document number: 2001997848 Country of ref document: EP |
|
ENP | Entry into the national phase |
Ref country code: JP Ref document number: 2002 544786 Kind code of ref document: A Format of ref document f/p: F |
|
AK | Designated states |
Kind code of ref document: A3 Designated state(s): JP |
|
AL | Designated countries for regional patents |
Kind code of ref document: A3 Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE TR |
|
121 | Ep: the epo has been informed by wipo that ep was designated in this application | ||
WWP | Wipo information: published in national office |
Ref document number: 2001997848 Country of ref document: EP |