WO2002047165A3 - Method and apparatus for considering diagonal wiring in placement - Google Patents

Method and apparatus for considering diagonal wiring in placement Download PDF

Info

Publication number
WO2002047165A3
WO2002047165A3 PCT/US2001/046406 US0146406W WO0247165A3 WO 2002047165 A3 WO2002047165 A3 WO 2002047165A3 US 0146406 W US0146406 W US 0146406W WO 0247165 A3 WO0247165 A3 WO 0247165A3
Authority
WO
WIPO (PCT)
Prior art keywords
placement
diagonal wiring
considering
considering diagonal
costs
Prior art date
Application number
PCT/US2001/046406
Other languages
French (fr)
Other versions
WO2002047165A2 (en
Inventor
Steven Teig
Joseph L Ganley
Original Assignee
Simplex Solutions Inc
Steven Teig
Joseph L Ganley
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US09/731,891 external-priority patent/US7024650B2/en
Priority claimed from US09/732,181 external-priority patent/US6826737B2/en
Application filed by Simplex Solutions Inc, Steven Teig, Joseph L Ganley filed Critical Simplex Solutions Inc
Priority to CN01821956XA priority Critical patent/CN1529864B/en
Priority to AU2002233977A priority patent/AU2002233977A1/en
Priority to EP01984980A priority patent/EP1362373A2/en
Priority to JP2002548785A priority patent/JP2004529402A/en
Publication of WO2002047165A2 publication Critical patent/WO2002047165A2/en
Publication of WO2002047165A3 publication Critical patent/WO2002047165A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/392—Floor-planning or layout, e.g. partitioning or placement
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/394—Routing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B7/00—Recording or reproducing by optical means, e.g. recording using a thermal beam of optical radiation by modifying optical properties or the physical structure, reproducing using an optical beam at lower power by sensing optical properties; Record carriers therefor
    • G11B7/08—Disposition or mounting of heads or light sources relatively to record carriers
    • G11B7/085—Disposition or mounting of heads or light sources relatively to record carriers with provision for moving the light beam into, or out of, its operative position or across tracks, otherwise than during the transducing operation, e.g. for adjustment or preliminary positioning or track change or selection
    • G11B7/0857—Arrangements for mechanically moving the whole head
    • G11B7/08582—Sled-type positioners

Abstract

Some embodiments of the invention are placers that use diagonal lines in calculating the costs of potential placement configurations. For instance, some embodiments estimate the wirelength cost of a placement configuration by using a line that is completely or partially diagonal. Other embodiments use diagonal lines to measure congestion costs of potential placement configurations.
PCT/US2001/046406 2000-12-06 2001-12-05 Method and apparatus for considering diagonal wiring in placement WO2002047165A2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
CN01821956XA CN1529864B (en) 2000-12-06 2001-12-05 Method and apparatus for considering diagonal wiring in placement
AU2002233977A AU2002233977A1 (en) 2000-12-06 2001-12-05 Method and apparatus for considering diagonal wiring in placement
EP01984980A EP1362373A2 (en) 2000-12-06 2001-12-05 Method and apparatus for considering diagonal wiring in placement
JP2002548785A JP2004529402A (en) 2000-12-06 2001-12-05 Method and apparatus for taking diagonal wiring into account during placement

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US09/731,891 US7024650B2 (en) 2000-12-06 2000-12-06 Method and apparatus for considering diagonal wiring in placement
US09/731,891 2000-12-06
US09/732,181 US6826737B2 (en) 2000-12-06 2000-12-06 Recursive partitioning placement method and apparatus
US09/732,181 2000-12-06

Publications (2)

Publication Number Publication Date
WO2002047165A2 WO2002047165A2 (en) 2002-06-13
WO2002047165A3 true WO2002047165A3 (en) 2003-08-21

Family

ID=27112314

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2001/046406 WO2002047165A2 (en) 2000-12-06 2001-12-05 Method and apparatus for considering diagonal wiring in placement

Country Status (7)

Country Link
US (1) US6904580B2 (en)
EP (1) EP1362373A2 (en)
JP (1) JP2004529402A (en)
CN (1) CN1529864B (en)
AU (1) AU2002233977A1 (en)
TW (1) TW564575B (en)
WO (1) WO2002047165A2 (en)

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US6826737B2 (en) 2000-12-06 2004-11-30 Cadence Design Systems, Inc. Recursive partitioning placement method and apparatus
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US7024650B2 (en) * 2000-12-06 2006-04-04 Cadence Design Systems, Inc. Method and apparatus for considering diagonal wiring in placement
US7055120B2 (en) * 2000-12-06 2006-05-30 Cadence Design Systems, Inc. Method and apparatus for placing circuit modules
US7080336B2 (en) 2000-12-06 2006-07-18 Cadence Design Systems, Inc. Method and apparatus for computing placement costs
US7073150B2 (en) 2000-12-07 2006-07-04 Cadence Design Systems, Inc. Hierarchical routing method and apparatus that use diagonal routes
US6915501B2 (en) * 2001-01-19 2005-07-05 Cadence Design Systems, Inc. LP method and apparatus for identifying routes
US6738960B2 (en) 2001-01-19 2004-05-18 Cadence Design Systems, Inc. Method and apparatus for producing sub-optimal routes for a net by generating fake configurations
US7155697B2 (en) 2001-08-23 2006-12-26 Cadence Design Systems, Inc. Routing method and apparatus
US7398498B2 (en) 2001-08-23 2008-07-08 Cadence Design Systems, Inc. Method and apparatus for storing routes for groups of related net configurations
US6795958B2 (en) 2001-08-23 2004-09-21 Cadence Design Systems, Inc. Method and apparatus for generating routes for groups of related node configurations
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CN102054068B (en) * 2009-10-30 2014-06-18 新思科技(上海)有限公司 Method and device for distributing line network in chip design
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Also Published As

Publication number Publication date
EP1362373A2 (en) 2003-11-19
CN1529864B (en) 2010-05-05
WO2002047165A2 (en) 2002-06-13
CN1529864A (en) 2004-09-15
JP2004529402A (en) 2004-09-24
AU2002233977A1 (en) 2002-06-18
US20020170027A1 (en) 2002-11-14
TW564575B (en) 2003-12-01
US6904580B2 (en) 2005-06-07

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