WO2002047323A2

WO2002047323A2 - Method and apparatus for transferring data and voice packets between packet and synchronous network

Info

Publication number: WO2002047323A2
Application number: PCT/SI2001/000034
Authority: WO
Inventors: Kristjan Pecanac
Original assignee: Daisy Technologies Inc.
Priority date: 2000-12-08
Filing date: 2001-12-07
Publication date: 2002-06-13
Also published as: WO2002047323A3; AU2002218646A1; SI20398A

Abstract

Method and apparatus for transferring and transformation of data and voice packets between packet network and synchronous telecommunication network. The invention is based on the use of packet manager (4), buffer memory (6) with two separate access points (DPRAM) and expansion module (2), which performs a function of packet transformation. Packet manager's (4) task is packet transferring between buffer memory (6) and electronic elements (3) on expansion module (2). Usage of the invention in a real case, disburdens the communication processor's core and it's external bus, because of the flexible expansion module (2) and packet manager (4) also quick and efficient adaptation of the main system to the changes in telecommunication area is possible and also to the different software manufacturers for packet transformation and electronic elements (3), like DSP processors and FPGA circuits.

Description

METHOD AND APPARATUS FOR TRANSFERRING DATA AND VOICE PACKETS BETWEEN PACKET AND SYNCHRONOUS NETWORK

Field of the Invention

Subject of the invention are method and apparatus for transferring data and voice packets between packet and synchronous network.

invention relates to field of electronic circuit boards and suitable software for use in communications. More specifically, the invention relates to field of transferring voice and also data packets on standard existing telecommunication and data networks.

Technical problem, which the invention resolves

Contemporary electronic circuit boards for use in communications are mainly comprised of main communication processor, which handles the control over the whole circuit board, and of electronic components, most often used are Digital Signal Processors (DSP), which are responsible for packet handling.

Main problem in this field is heavy load on the processor core and on the external bus of the communication processor while transferring packets between communication processor and electronic components for packet handling. Problematical is also the speed of this transfer, because it must not brake the data flow. The invention solves the described problems and assures lower load on communication processor's core and it's external bus and also assures needed packet transfer speed.

State of the art

For the solution of the described problems there already exist some solutions, but they contain some deficiencies. One of the solutions, shown in Figure 1, uses it's own specific integrated circuit (ASIC) 24, in which complete transfer control and also packet transfer between external Synchronous- Dynamic memory (SDRAM) 28 of the communication processor 36, on Figure 1, and internal memory of DSP processors 22, which transforms the packets, is realized. Data from packet network 34 shown in Figure 1, are intersected by communication processor 36, which stores packets with voice contents into SDRAM 28. Integrated circuit ASIC 24 transfers the packets through PCI bridge 30 and PCI bus 26 into internal memory of one of the DSP processors. In this case packets are transferred in parallel mode. Here the packet is transformed and transmitted into synchronous network 20, shown in Figure 1. Procedure for packet transfer from synchronous network 20 to packet network 34 is the same, but in reverse order. The whole transfer is handled by integrated circuit ASIC 24 and by doing that disburdens the communication processor's 36 core. The deficiency of this solution is that with reading and writing packets into SDRAM 28 from the DSP processor 22 side, the external bus of the communication processor 32, shown in Figure 1, is used, what causes burden of this bus. The second deficiency is that the integrated circuit 24 is an end and closed product, which cannot be changed and adapted to fast changes, which are evolving in the field of telecommunications.

The second solution, shown in Figure 2, for packet transferring uses serial data transfer by serial bus 50. Data from the packet network 44, shown in Figure 2, is intersected by communication processor 48, shown in Figure 2, which using the external processor bus 42, shown in Figure 2, stores packets with voice contents into SDRAM memory 40. Communication processor 48 sends the packets, stored in SDRAM 40, through the serial channel 50 to the DSP processors 52, where is saved in one of their internal memory. Data transfer on¹ the serial channel 50 can be performed transparently or by using HDLC (High- level Data Link Control) encapsulation. Selected DSP transforms the packet end transmits it into the synchronous network 46. Procedure for packet transfer from synchronous network 46, shown in Figure 2, to packet network 44 is the same, but in reverse order. The whole transfer is handled by communication processor 48, what additionally burdens its core, and is a big problem and remains unsolved in this case. For the communication between communication 48 and one of the DSP 52 processors, serial interfaces of the communication processor 48 and DSP processor is used. This method eliminates the problem of the burdening of the external processor bus 42.

Task and aim of the invention is that kind of method and apparatus for transferring data and voice packets between packet and synchronous network, that all the deficiencies of the known solutions will be resolved.

By the invention the task is solved with the method and apparatus for transferring data and voice packets between packet and synchronous network by the independent patent claims.

DESCRIPTION OF THE INVENTION

Besides offering solutions to described problems, the invention, also suppresses imperfections mentioned in existing solutions described above.

For realization of the invention is used

• expansion module 2, and two standard integrated circuits:

• memory with two separate accesses 6 (Dual Port RAM - DPRAM) and

• packet manager 4.

Expansion module 2 is an electronic circuit board, comprised of different electronic components 3, where most of them are integrated circuits. With the expression expansion module, the implementation of electronic components 3 into common electronic circuit board is defined. Expansion module can be part of the main electronic circuit board or it can be realized as an add-on card on the main electronic circuit board. Function of the expansion module 2 is transformation of voice and data packets. The advantage of usage of the expansion module 2 is, that different integrated circuits, designed for packet transformation, can be used, what as a consequence results in a very flexible solution. DSP processors and application specific integrated circuits are among possible integrated circuits. Main feature of the DPRAM, in the invention also advantage, is that it can be connected to two separate buses, so that the access to the memory 6 is possible from both buses at the same time. This feature is used in the invention in following way: one access point is connected to the external processor bus 10 (shown in Figure 3), of the communication processor 12 (shown in Figure 3), and the second to the expansion bus 8 to the expansion module 2. DPRAM is used as an external memory of the communication processor 12, which performs a function of buffer memory 6. Inside this memory, packets, which are transferred between communication processor 12 and expansion module 2, are stored. In case of reading and writing in DPRAM from expansion module 2, buffer memory 6 is accessed via the point, connected to the expansion bus 8. This ensures that this action does not burden the external processor bus 10. In this way, one of the deficiencies of the solutions described above is resolved.

Packet manager 4 is also the element of the invention. Its task is packet transfer between buffer memory 6 and electronic components 3 on expansion module 2, which are meant for packet transformation. This means that packet manager 4 performs the whole packet transfer and by doing that, it disburdens the communication processor's 12 core. The invention also solves the second deficiency mentioned in existing solutions. Very important invention's advantage over already realized solutions is, that software executed on packet manager 4 is not uniformly defined. This means that this invention is suitable for implementation in different systems, which are described in detailed description of the invention.

Brief description of the drawings

The solutions of the invention will become more apparent and clear after reviewing the following detailed description together with the accompanying drawings.

Fig. 1 shows state of the technic with the use of application specific integrated circuit ASIC.

Fig. 2 shows state of the technic with serial connection between communication processor and

DSP processors.

Fig. 3 shows placement and connection of the elements used in the invention.

Fig. 4 shows procedure for packet transfer from the communication processor to the expansion module. Fig. 5 shows procedure for packet transfer from the expansion module to the communication processor.

DETAILED DESCRIPTION OF THE INVENTION

For better illustration of the invention's procedure, the procedure for packet transferring in direction from communication processor to expansion module and vice versa is described in details below. Regarding shown abilities, capacities and advantages many possibilities of usage appear. Two examples of usage of the invention are described, but it's usage is not limited exclusively to the described examples.

Description of the procedure

As it can be seen in the general invention description, the procedure is composed of two parts, executed simultaneously. One part of the procedure is packet transfer from the communication processor to the expansion module, and the second part is packet transfer from the expansion module to the communication processor. Both parts of the procedure are executed simultaneously, thus starts 60 and 80 are simultaneous and single events. For this purpose two figures are drawn, figure 4 and figure 5, which describe above-mentioned parts of the procedure, and are related to the figure 3, which shows placement and connection of all the elements used in the invention. Procedure for both parts will be described by states, which are numbered in the figure 4 and 5.

Procedure of packet transfer from communication processor 12 to the expansion module 2 is executed in the following way. After the start 60 of the procedure execution, communication processor 12 goes into the state of waiting for arrived packet 62, and stays there until it receives a new packet. When communication processor 12 receives the new packet, which corresponds the transfer conditions, it transfers-saves 64 directly into the buffer memory 6, and after that signals 66 to the packet manager 4 about the newly arrived packet. Instead of signaling 66 about the newly arrived packet, packet manager 4 can also check the packets in buffer memory and transfers the prepared one into. Packet manager 4 transfers the packet 68 into expansion module. By doing that the packet transfer is completed and it starts executing from the state of waiting for new packet 62 again.

Procedure for packet transfer from the expansion module 2 to the communication processor 12 is executed in the following way. After the start 80 of the of the procedure execution, packet manager 4 starts searching 82 for the prepared packet in expansion module. In state 84 packet manager 4 checks every packet. If the packet is not prepared it returns to searching 82 for new packet and if the packet is prepared it transfers 86 it into the buffer memory 6. When the packet is already stored in buffer memory 6, packet manager signals to communication processor 12 about the transferred packet. If the communication processor 12 does not use the signalization method, it can also check the packets stored in the buffer memory 6 and determines which packet is new. After this action the procedure is returned to searching 82 for the new prepared packet.

Transfer of voice packets

Transfer of voice packets is very common function performed by electronic circuit boards in modern telecommunication systems, which are comprised of data and telecommunication networks. Use of the invention in this case enables essential increase of electronic circuit board's capabilities, meaning an increased capacity of voice data transfer and by that, increased number of voice channels that can be handled by the board.

Typical task, which this electronic circuit boards use is transfer of voice packets between packet data network 15, shown in Figure 3, (IP - Internet Protocol; ATM - Asynchronous Transfer Mode) and synchronous telecommunication network 14, shown in Figure 3, (TDM - Time Division Multiplexing). Voice data in synchronous network 14 are time multiplexed voice samples and are transferred in 125μs long following frames, with the specified number of 8 bits channels inside. If we multiply the size of the channel (8 bits) with the frame frequency (l/125μs) we get speed of 64kbit/s per voice channel. Each channel inside the frame represents one telephone conversation and the number of channels in the frame represents the capacity of the telephone line. Data in packet networks are arranged in different way. The whole data flow is transferred in exactly defined packets, dependent on the network type. Packet is composed of exactly defined header, which transfers necessary data about the packet content and about the sender and recipient's addresses, and of data containing the actual content. In case of voice packet, this content is coded voice, coded by defined standards (CODEC - Coding Decoding). Because the data format in mentioned networks is not the same, it is necessary to transform it before transferring between the networks. Software packages, which are mostly executed on DSP processors, are used for this purpose.

In this realization of the invention it is necessary to adjust the expansion module 2 in the way, that it will be capable of transforming the voice packets described above. In this purpose, DSP processors are used for electronic elements 3 on expansion module 2. Software for voice packet transformation is already realized and is offered by different manufacturers in different variations. In this case the advantage of solution with adjustable expansion module 2 is evident, because different software manufacturers support different DSP processors or they even have their own variations of them.

For transferring voice packets between the communication processor 12 and DSP processors on the expansion module 2, the packet manager 4 is used, which transfers voice packets through buffer memory 6 using expansion bus 8. Because of possible use of different DSP processors, also the transfer of voice packet has to be adjusted. Because of the adaptability of the packet manager, only software executed by it has to be adjusted to suit the selected type of DSP processor.

Transfer of a packet from the packet network 16 to synchronous network 14 is performed in the following way. When the communication processor 12 accepts a packet from packet network 16, first checks it's header. If the packet is labeled as a packet with voice content, it is transferred into the DPRAM buffer memory 6. Packet manager 4 transfers this packet into internal memory of one of the DSP processors on expansion module 2, using the expansion bus 8. DSP processor removes the head from the packet, decodes the packet content and sends it into the synchronous network as a 64kbit/s pulse modulated voice. From the example description can be seen, that the basic system for transferring and fransforming the voice packets is totally independent of the software manufacturer selection and of the DSP processors for voice transformation selection.

Redirection of packets

Use of the invention for packet redirection is also very suitable, because it offers great flexibility and a chance of quick adaptation to new standards on telecommunication filed, and also offers great speed of redirection.

In this case, redirection is based upon redirection between IP packet network and ATM packet network. For this realization, the expansion module has to be adjusted in the way, that it will be capable to redirect as many packets as possible. For this purpose, combination of DSP processors and application specific integrated circuit is used. Inside the integrated circuit we realize needed functionality (protocol) in the way that we write appropriate software, which will be executed on the circuit.

Packet redirection is executed in next way. Communication processor 12 receives the packets, which are comprised of headpr and contents, from packet network 16 (IP or ATM) and stores them directly into the buffer memory 6, by using external bus 8. Packet manager 4 transfers the packets into expansion module 2, using expansion bus 8, which transforms the packet header, while the content remains unchanged. Packet manager 4 transfers the transformed packet into the buffer memory 6, using expansion bus 8, where is at hand to the communication processor 12, to transmit it onto requested address in the other packet network (ATM or IP). Because of possible use of different DSP processors and different realized functions inside the specific integrated circuit, it is also necessary to adjust the method of packet transfer. Because of the adaptability of the packet manager it is necessary to adjust only software executed by it, in the way, that suits the selected type of DSP processors or application specific integrated circuit.

In this example it is possible to assure, that the elements on the expansion module through FPGA circuit, access to the buffer memory 6 by itself, what makes redirection even faster. By doing this, we achieve, that the main system for packet redirection is completely independent from the selection of electronic components (DSP processors and application specific integrated circuit) on expansion module 6, and from selection of the functionality (protocol) performed by it.

Claims

PATENT CLAIMS

1. Method for packet transferring between communication processor and expansion module, characterized in that, for packet transfer method buffer memory (6) and packet manager are used, where

- after start (60) of the method execution, communication processor (12) waits in state (62) for a new packet,

- if new arrived packet corresponds to the transfer conditions, communication processor (12) stores it directly into the buffer memory (6),

- communication processor (12) signals (66) to the packet manager (4) about arrived packet,

- if signalization {66) method is not used for informing about new arrived packets, packet manager (4) can check the packets stored in the buffer memory (6) by itself,

- when the packet manager (4) has information about new packet in buffer memory (6) it transfers (68) new prepared packet, into the expansion module (2),

- when the transfer (68) is completed, the method is returned into state (62), where communication processor (12) waits for new packet.

2. Method for packet transferring between communication processor and expansion module, characterized in that, for packet transfer method buffer memory (6) and packet manager are used, where

- after start (80) of the method execution, packet manager (4) starts with searching (82) for a prepared packet in expansion module (2),

- with every packet it goes in state (84) where it checks if the packet is prepared,

- if packet is not prepared, packet manager (4) goes back to search (82) for new packet,

- if the packet is prepared, packet manager (4) transfers (86) it into the buffer memory (6),

- when the packet is stored in buffer memory (6), packet manager (4) signals to the communication processor (12) about the arrived packet,

- if communication processor (12) does not use the signaling method, it can check the packets stored in the buffer memory (6) and finds out which packet is new, - when the packet is stored in the buffer memory (6), packet manager returns to searching (82) for prepared packet in expansion module (2).

3. Apparatus for packet transferring between communication processor and expansion module, characterized in that, it executes methods in accordance with claims 1 and 2.

4. Apparatus for packet transferring between communication processor and expansion module, characterized in that, for packet transfer buffer memory (6), packet manager (4) and expansion module (2) are used.

5. Apparatus in accordance with claim 4, characterized in that, for realization of the buffer memory (6), memory with two separate access points (DPRAM) is used; that the buffer memory (6) is with one access point connected to the external bus of the communication processor (12) and with the other access point to the expansion bus (8).

6. Apparatus in accordance with claim 4, characterized in that, for realization of packet manager (4) integrated circuit is used; that the packet manager (4) is connected to the expansion bus (8).

7. Apparatus in accordance with claim 4, characterized in that, expansion module (2) means the way of implementation of the electronic components (3); that for realization of expansion module (2) part of the main electronic circuit board or an add-on electronic circuit, on which different electronic components (3) can be included, is used; that for possible electronic components (3) one ore more digital signal processors (DSP) and one or more application specific integrated circuits are considered; that expansion module is connected to the expansion bus (8).