WO2002048860A2 - Synchronous memory controller - Google Patents

Synchronous memory controller Download PDF

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Publication number
WO2002048860A2
WO2002048860A2 PCT/GB2001/005547 GB0105547W WO0248860A2 WO 2002048860 A2 WO2002048860 A2 WO 2002048860A2 GB 0105547 W GB0105547 W GB 0105547W WO 0248860 A2 WO0248860 A2 WO 0248860A2
Authority
WO
WIPO (PCT)
Prior art keywords
synchronous
controller
physical address
memory
memory device
Prior art date
Application number
PCT/GB2001/005547
Other languages
French (fr)
Other versions
WO2002048860A3 (en
Inventor
Philip Eade
Original Assignee
Psion Digital Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from GB0030520A external-priority patent/GB0030520D0/en
Priority claimed from GB0118012A external-priority patent/GB0118012D0/en
Application filed by Psion Digital Limited filed Critical Psion Digital Limited
Publication of WO2002048860A2 publication Critical patent/WO2002048860A2/en
Publication of WO2002048860A3 publication Critical patent/WO2002048860A3/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/4401—Bootstrapping
    • G06F9/4403—Processor initialisation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation

Definitions

  • This invention relates to a synchronous memory controller.
  • the controller interfaces a synchronous memory device to a digital component enabling, for example, the synchronous transfer of an initial instruction sequence or protocol from the memory to the digital component.
  • the invention is usable in or together with a number of different kinds of digital component, including but not limited to microprocessors, micro-controllers and System On Chip (SoC) devices.
  • SoC System On Chip
  • a microprocessor system will normally have a memory device attached to it: when it is initiated, it will load an initial instruction sequence or software from this memory device, usually tailored to the device in which the microprocessor is installed. Normally, during the software development cycle, this instruction sequence, will be loaded into a "flash" memory device so as to allow editing and modification of the instruction sequence. Flash memory devices can be accessed at a high bandwidth and are therefore ideal for use during the development cycle. Once the software code is finalised using this flash device, it can then be made into a masked ROM memory device for installation and run time use in the final electronic product. This will normally reduce manufacturing costs and may improve performance and reliability.
  • a masked ROM device typically has an asynchronous interface; this can be addressed in exactly the same manner as the synchronous Flash device used during development. Both types of device will have address inputs from A 0 to A n While they might have a different number of address inputs, additional memory devices (together with some control logic) can be added to ensure that they are addressed in exactly the same way. Hence they will return the same data when a particular physical address is asserted whether the code is running from synchronous Flash memory or asynchronous masked ROM devices. This enables an asynchronous masked ROM device to be made that displays exactly the same software image as was used during the development process (using synchronous Flash) without significant modification.
  • a synchronous Mask ROM may return a different op-code or data constant from that in fact needed. Therefore it is not possible to directly use the code developed in a Flash memory in a synchronous ROM memory. Instead, data from the synchronous ROM memory must be manipulated at design time to ensure that it presents an equivalent image to the synchronous Flash memory device used in development. This can easily lead to mistakes and wasted ROM devices, as well as delay in adapting prototypes to final production devices.
  • a synchronous memory controller able to convert an incoming physical address request relating to a given process, the request being sent from a digital component to a memory device via the controller, in which the same physical address request that was used during the development of the software for that process is used by the component at run time because the controller is capable of mapping an incoming physical address request from the digital component to the physical address required by the memory device for it to return the correct data for the process.
  • the process is typically booting up.
  • one implementation of the invention enables the same boot up data to be read at run time (i.e. during normal operation in a mass produced device, as opposed to during the development phase) from both a synchronous ROM device and a synchronous Flash memory device, with a synchronous memory controller re-configuring the address mappings of the devices so both memory devices will present an identical software image.
  • This enables the same software image generated through development (using a synchronous Flash memory) to be made into a synchronous Mask ROM device without requiring any modification.
  • the controller may allow a first synchronous memory device to assert a consecutive sequence of addresses to the controller and the controller then maps those to a consecutive sequence of addresses that would have been asserted by a Flash memory device.
  • a method of designing a digital component comprising the step of designing a synchronous memory controller able to convert an incoming physical address request relating to a given process, the request being sent from the digital component to a memory device via the controller, in which the same physical address request that is used during the development of the software for that process is used by the component at run time because the controller is capable of mapping an incoming physical address request from the digital component to the physical address required by the memory device for it to return the correct data for the process.
  • a digital component adapted to co-operate with a synchronous memory controller as defined above.
  • Figure 1 is a schematic of a semiconductor device in accordance with the present invention developed by Psion PLC of Great Britain showing its relationship to various possible external memory devices. DETAILED DESCRIPTION OF THE PREFERRED IMPLEMENTATION
  • Halla has a processor core 1, memory controllers 2 and 3 and may boot (begin running software) either from an asynchronous memory device 4 (a Mask ROM) or from synchronous memory devices 5 (synchronous Flash) or 6 (synchronous RAM). If Halla is to load code from a synchronous memory device 5 or 6, the processor will request memory access to and from the synchronous memory controller 2. This controller in turn accesses synchronous memory devices attached to it via the External Bus Interface (as the address and data bus is shared with asynchronous memory devices).
  • asynchronous memory device 4 a Mask ROM
  • synchronous Flash synchronous Flash
  • 6 synchronous RAM
  • the particular microprocessor within Halla is referred to as the ARM920TTM processor and is based on a 16/32 bit embedded reduced instruction set (RISC) cached processor macrocell core developed by ARM Limited of the United Kingdom as part of a family of processors referred to as the ARM9TM Thumb® series. Development kits, including development boards for this processor are available from ARM Limited and further detailed information is available from the ARM website at arm.com.
  • RISC embedded reduced instruction set
  • SYAO represents the Synchronous Address
  • Bus bit 0 and SYBO represents the Synchronous Bank Address bit 0.
  • the mapping shown in Row 2 is normally used, but when bit 5, SROMLL is set within the Synchronous Memory
  • Synchronous Flash device will have 4 bank addresses which enable it to have up to 4 pages (rows) open at any one time and say 12 Synchronous Address lines.
  • a Synchronous ROM typically does not have any bank address pins, but has more Synchronous Address lines, say 14. Therefore by swapping the addresses on SYA12 & SYA13 with SYBO & SYB1, a Synchronous ROM will map consecutively to addresses A2 to A9 (Columns) and then A10 to A23 (Rows). This is shown in Row 2.
  • a Synchronous Flash will map to addresses A2 to A9 (Columns) and then A10 to A21 (Rows) and A22 to A23 (Banks) consecutively. This is shown in Row 6. Hence they appear the same.
  • boot selection pins see Table 3 which determine the type of memory device that Halla will boot from and the data width of that externally attached Memory device. Note that there are options for booting from both 16 and 32 bit wide devices for both Synchronous Flash and Synchronous ROM devices. By determining whether the device is Synchronous ROM or Synchronous Flash at boot up time, this then determines the state of the SROMLL bit and the memory mapping mode used. This enables synchronous boot from either type of device with the same memory map configuration: where synchronous Flash is used, no mapping is needed since the addresses equate to that used in development. But where synchronous ROM is used, the mapping described above is required.

Abstract

A synchronous memory controller is able to convert an incoming physical address request relating to a given process, the request being sent from a digital component to a memory device via the controller. The same address that was used during the development of the software for that process is used by the component at run time because the controller is capable of mapping the incoming physical address request to the physical address required by the memory device for it to return the correct data for the process.

Description

SYNCHRONOUS MEMORY CONTROLLER
BACKGROUND TO THE INVENTION
1. Field of the Invention
This invention relates to a synchronous memory controller. The controller interfaces a synchronous memory device to a digital component enabling, for example, the synchronous transfer of an initial instruction sequence or protocol from the memory to the digital component. The invention is usable in or together with a number of different kinds of digital component, including but not limited to microprocessors, micro-controllers and System On Chip (SoC) devices.
2. Description of the Prior Art
A microprocessor system will normally have a memory device attached to it: when it is initiated, it will load an initial instruction sequence or software from this memory device, usually tailored to the device in which the microprocessor is installed. Normally, during the software development cycle, this instruction sequence, will be loaded into a "flash" memory device so as to allow editing and modification of the instruction sequence. Flash memory devices can be accessed at a high bandwidth and are therefore ideal for use during the development cycle. Once the software code is finalised using this flash device, it can then be made into a masked ROM memory device for installation and run time use in the final electronic product. This will normally reduce manufacturing costs and may improve performance and reliability. A masked ROM device typically has an asynchronous interface; this can be addressed in exactly the same manner as the synchronous Flash device used during development. Both types of device will have address inputs from A0 to An While they might have a different number of address inputs, additional memory devices (together with some control logic) can be added to ensure that they are addressed in exactly the same way. Hence they will return the same data when a particular physical address is asserted whether the code is running from synchronous Flash memory or asynchronous masked ROM devices. This enables an asynchronous masked ROM device to be made that displays exactly the same software image as was used during the development process (using synchronous Flash) without significant modification.
There are however advantages to booting up at run time from a masked memory device with a synchronous interface as opposed to asynchronous; for example, a synchronous masked ROM in theory can be fast and efficient. However, when the attached masked memory device has a synchronous interface, the physical memory addresses will not equate to the addresses used in synchronous Flash memory because each has a different organisation. Normally, when a Microprocessor requests an address, it is converted to a Bank, Row and Column address and the attached memory device should then return a particular value which is either an op-code instruction or some data constant. Due to the different organisation of the synchronous masked ROM to the synchronous Flash memory device used in development, a synchronous Mask ROM may return a different op-code or data constant from that in fact needed. Therefore it is not possible to directly use the code developed in a Flash memory in a synchronous ROM memory. Instead, data from the synchronous ROM memory must be manipulated at design time to ensure that it presents an equivalent image to the synchronous Flash memory device used in development. This can easily lead to mistakes and wasted ROM devices, as well as delay in adapting prototypes to final production devices.
SUMMARY OF THE INVENTION
In a first aspect of the present invention, there is a synchronous memory controller able to convert an incoming physical address request relating to a given process, the request being sent from a digital component to a memory device via the controller, in which the same physical address request that was used during the development of the software for that process is used by the component at run time because the controller is capable of mapping an incoming physical address request from the digital component to the physical address required by the memory device for it to return the correct data for the process.
The development of the software for the process will typically have used a synchronous Flash memory and the controller is then able to map the physical addresses associated with such a Flash memory device to a synchronous ROM, so that at run time a synchronous Flash memory device or asynchronous masked ROM can be used without any mapping, or a synchronous masked ROM can be used with mapping.
The process is typically booting up. Hence, one implementation of the invention enables the same boot up data to be read at run time (i.e. during normal operation in a mass produced device, as opposed to during the development phase) from both a synchronous ROM device and a synchronous Flash memory device, with a synchronous memory controller re-configuring the address mappings of the devices so both memory devices will present an identical software image. This enables the same software image generated through development (using a synchronous Flash memory) to be made into a synchronous Mask ROM device without requiring any modification. More specifically, the controller may allow a first synchronous memory device to assert a consecutive sequence of addresses to the controller and the controller then maps those to a consecutive sequence of addresses that would have been asserted by a Flash memory device.
In another aspect, there is a method of designing a digital component, the method comprising the step of designing a synchronous memory controller able to convert an incoming physical address request relating to a given process, the request being sent from the digital component to a memory device via the controller, in which the same physical address request that is used during the development of the software for that process is used by the component at run time because the controller is capable of mapping an incoming physical address request from the digital component to the physical address required by the memory device for it to return the correct data for the process.
In a final aspect, there is a digital component adapted to co-operate with a synchronous memory controller as defined above.
FIGURES
Figure 1 is a schematic of a semiconductor device in accordance with the present invention developed by Psion PLC of Great Britain showing its relationship to various possible external memory devices. DETAILED DESCRIPTION OF THE PREFERRED IMPLEMENTATION
This invention is described with reference to a new device designed by Psion Computers Limited of the United Kingdom named Ηalla", which is a microprocessor System On Chip, a schematic of which is shown as Figure 1. Halla has a processor core 1, memory controllers 2 and 3 and may boot (begin running software) either from an asynchronous memory device 4 (a Mask ROM) or from synchronous memory devices 5 (synchronous Flash) or 6 (synchronous RAM). If Halla is to load code from a synchronous memory device 5 or 6, the processor will request memory access to and from the synchronous memory controller 2. This controller in turn accesses synchronous memory devices attached to it via the External Bus Interface (as the address and data bus is shared with asynchronous memory devices).
The particular microprocessor within Halla is referred to as the ARM920T™ processor and is based on a 16/32 bit embedded reduced instruction set (RISC) cached processor macrocell core developed by ARM Limited of the United Kingdom as part of a family of processors referred to as the ARM9™ Thumb® series. Development kits, including development boards for this processor are available from ARM Limited and further detailed information is available from the ARM website at arm.com. There are many configuration parameters that can be set within the Synchronous Memory Controller 2 and this is done by the Microprocessor 1 writing into the Synchronous Memory Configuration register shown in Table 1. These parameters determine the clock cycles upon which commands will be issued to the attached devices, the type of commands and the particular address mapping used. Hence, bit 5, SROMLL (Sync ROM Look Alike Mode) within the Synchronous Memory Configuration register will change the address mapping mode to make a Synchronous Flash device look like a Synchronous ROM device.
The effect that this setting will have is shown in Table 2. This shows how a physical address asserted by the Microprocessor is converted by the Synchronous Memory Controller 2 to a Row,
Bank, Column address for the Synchronous device. SYAO represents the Synchronous Address
Bus bit 0 and SYBO represents the Synchronous Bank Address bit 0. The mapping shown in Row 2 is normally used, but when bit 5, SROMLL is set within the Synchronous Memory
Configuration register, the mapping shown in Row 6 is used. This swaps the addresses on
SYA12 & SYA13 with SYBO & SYB1 respectively.
Typically a Synchronous Flash device will have 4 bank addresses which enable it to have up to 4 pages (rows) open at any one time and say 12 Synchronous Address lines. However a Synchronous ROM typically does not have any bank address pins, but has more Synchronous Address lines, say 14. Therefore by swapping the addresses on SYA12 & SYA13 with SYBO & SYB1, a Synchronous ROM will map consecutively to addresses A2 to A9 (Columns) and then A10 to A23 (Rows). This is shown in Row 2. Similarly a Synchronous Flash will map to addresses A2 to A9 (Columns) and then A10 to A21 (Rows) and A22 to A23 (Banks) consecutively. This is shown in Row 6. Hence they appear the same.
There are also three dedicated boot selection pins (see Table 3) which determine the type of memory device that Halla will boot from and the data width of that externally attached Memory device. Note that there are options for booting from both 16 and 32 bit wide devices for both Synchronous Flash and Synchronous ROM devices. By determining whether the device is Synchronous ROM or Synchronous Flash at boot up time, this then determines the state of the SROMLL bit and the memory mapping mode used. This enables synchronous boot from either type of device with the same memory map configuration: where synchronous Flash is used, no mapping is needed since the addresses equate to that used in development. But where synchronous ROM is used, the mapping described above is required.

Claims

1. A synchronous memory controller able to convert an incoming physical address request relating to a given process, the request being sent from a digital component to a memory device via the controller, in which the same physical address request that was used during the development of the software for that process is used by the component at run time because the controller is capable of mapping an incoming physical address request from the digital component to the physical address required by the memory device for it to return the correct data for the process.
2. The synchronous memory controller of Claim 1 in which the development of the software for the process used a synchronous Flash memory and the controller is able to map the physical addresses associated with a synchronous Flash memory to a synchronous ROM, so that at run time either a synchronous Flash or a synchronous ROM can be used for the process.
3. The controller of Claim 2 in which the process is booting up.
4. The controller of Claim 1 in which the controller allows a first synchronous memory device to assert a consecutive sequence of addresses to the controller and the controller maps those to a consecutive sequence of addresses that would have been asserted by a Flash memory device.
5. A method of designing a digital component, the method comprising the step of designing a synchronous memory controller able to convert an incoming physical address request relating to a given process, the request being sent from the digital component to a memory device via the controller, in which the same physical address request that is used during the development of the software for that process is used by the component at run time because the controller is capable of mapping an incoming physical address request from the digital component to the physical address required by the memory device for it to return the correct data for the process.
6. A digital component adapted to co-operate with a synchronous memory controller as claimed in Claims 1 — 4.
PCT/GB2001/005547 2000-12-14 2001-12-14 Synchronous memory controller WO2002048860A2 (en)

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
GB0030520A GB0030520D0 (en) 2000-12-14 2000-12-14 Microprocessors,microcontrollers,system on chip (SoC) synchronous memory device boot,synchronous flash memory
GB0030520.1 2000-12-14
GB0103409.9 2001-02-10
GB0103409A GB0103409D0 (en) 2000-12-14 2001-02-10 Method of booting up a digital component using synchronous or Flash memory
GB0118012A GB0118012D0 (en) 2000-12-14 2001-07-25 Synchronous memory controller
GB0118012.4 2001-07-25

Publications (2)

Publication Number Publication Date
WO2002048860A2 true WO2002048860A2 (en) 2002-06-20
WO2002048860A3 WO2002048860A3 (en) 2002-11-14

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Cited By (1)

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Publication number Priority date Publication date Assignee Title
GB2493340A (en) * 2011-07-28 2013-02-06 St Microelectronics Res & Dev Address mapping of boot transactions between dies in a system in package

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US5619471A (en) * 1995-06-06 1997-04-08 Apple Computer, Inc. Memory controller for both interleaved and non-interleaved memory
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EP0907124A1 (en) * 1997-03-31 1999-04-07 Seiko Epson Corporation Microcomputer and electronic equipment

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GB2278211A (en) * 1993-05-04 1994-11-23 Motorola Inc Memory management system
US6047361A (en) * 1996-08-21 2000-04-04 International Business Machines Corporation Memory control device, with a common synchronous interface coupled thereto, for accessing asynchronous memory devices and different synchronous devices
US5987574A (en) * 1997-04-30 1999-11-16 Sony Corporation Bank arbitration for SDRAM memory control
GB2357602A (en) * 1999-12-22 2001-06-27 Nokia Mobile Phones Ltd Memory controller for a memory array comprising different memory types

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US5752066A (en) * 1992-01-06 1998-05-12 International Business Machines Corporation Data processing system utilizing progammable microprogram memory controller
US5619471A (en) * 1995-06-06 1997-04-08 Apple Computer, Inc. Memory controller for both interleaved and non-interleaved memory
EP0907124A1 (en) * 1997-03-31 1999-04-07 Seiko Epson Corporation Microcomputer and electronic equipment

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2493340A (en) * 2011-07-28 2013-02-06 St Microelectronics Res & Dev Address mapping of boot transactions between dies in a system in package
US9026774B2 (en) 2011-07-28 2015-05-05 Stmicroelectronics (Research & Development) Limited IC with boot transaction translation and related methods

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Publication number Publication date
WO2002048860A3 (en) 2002-11-14
GB2372604A (en) 2002-08-28
GB0129971D0 (en) 2002-02-06

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