WO2002052287A2 - Method and device for testing of a transistor using a network analyzer - Google Patents
Method and device for testing of a transistor using a network analyzer Download PDFInfo
- Publication number
- WO2002052287A2 WO2002052287A2 PCT/IB2001/002610 IB0102610W WO02052287A2 WO 2002052287 A2 WO2002052287 A2 WO 2002052287A2 IB 0102610 W IB0102610 W IB 0102610W WO 02052287 A2 WO02052287 A2 WO 02052287A2
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- WIPO (PCT)
- Prior art keywords
- input
- output
- impedance
- reflection coefficient
- performance characteristic
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/282—Testing of electronic circuits specially adapted for particular applications not provided for elsewhere
- G01R31/2822—Testing of electronic circuits specially adapted for particular applications not provided for elsewhere of microwave or radiofrequency circuits
Definitions
- the field of the present invention relates generally to testing transistor devices and, more specifically, to methods and apparatus employing "virtual" impedance fixturing for testing transistor devices.
- FIG. 1 depicts a power amplifier circuit using parallel transistors, as adapted from Gonzalez, Guillermo, Microwave Transistor Amplifiers Analysis and Design, Second Edition, Prentice Hall, 1997, p. 364.
- a signal source V s 105 with source impedance Z s 110 is connected to the parallel transistor device input 130 through an input impedance transformation network 115.
- a load impedance Z 145 is coupled to the parallel transistor device output 135 via an output impedance transformation network 125.
- the gates of each transistor in the parallel transistor device are coupled together in a single input node 130.
- FIG. 3 represents a block diagram of a typical test fixture 300 used to house a device under test (“DUT") 305, while the DUT 305 undergoes testing by automated testing equipment (ATE).
- the DUT 305 is coupled at its input terminal by an input impedance transformation (or "matching") network 310.
- the DUT is coupled at its outpu terminal by an output matching network 315.
- the input and output matching networks 310 and 315 are often implemented using microstrip technology. However, many other designs for reducing the imaginary components of capacitance and inductance may be employed, including on-board discrete components like capacitors and inductors.
- the input and output matching networks 310 and 315 are application specific, requiring a separate and distinct test fixture for each type of device. Because the matching networks 310 and 315 of FIG 3 are physical components of the ATE, application independence also requires separate ATE for each device type.
- fixture cross-correlation must be maintained within tolerances to ensure that a device tested at one ATE station will produce the same results that the same device, or a nearly identical device, would produce if it were tested at a different ATE station.
- This maintenance of fixture cross-correlation is time consuming, inexact, and highly error-prone.
- modifications to microstrip impedance matching networks often involve an imprecise manipulation of board-level components, contributing to even greater fixture cross-correlation miscalibration.
- the present invention is directed to "virtual" fixturing of a device being tested, the virtual fixturing being implemented by “de-embedding" the input and output matching networks of a physical test fixture.
- a method for testing a transistor device comprising measuring small signal scatter parameters of the device, measuring a performance characteristic of the device, and transforming the measured performance characteristic based on the measured small signal scatter parameters of the device.
- a system for testing a transistor device, such as a laterally diffused metal oxide semiconductor (LDMOS) power transistor package.
- the system includes a test station having an input for coupling to a input terminal and an output for coupling to an output terminal, respectively, of the device, a network analyzer coupled to the test station for measuring small signal scatter parameters and for measuring a performance characteristic of the device, and a processor coupled to the network analyzer, the processor configured for transforming the measured performance characteristic based on the measured small signal scatter parameters.
- LDMOS laterally diffused metal oxide semiconductor
- An advantage of the invention is that a universal test fixture may be used for multiple types of devices to be tested, without having to change out the impedance matching networks at both ends of the device. Having a universal test fixture for multiple device applications eliminates errors associated with inter-fixture calibration from testing station to testing station within the manufacturing environment. Calibration of the virtual device fixture is performed in software and is consequently less cumbersome than the making board-level modifications otherwise required for impedance calibrations when preparing a test fixture for product testing.
- FIG. 1 is a circuit diagram of a power amplifier incorporating a parallel transistor device, as adopted from Gonzalez, Guillermo, Microwave Transistor Amplifiers Analysis and Design. Second Edition, Prentice Hall, 1997, p. 364.
- FIG. 2 is an enlarged view of an exemplary power amplifier device, illustrating an interleaved transistor construction.
- FIG. 3 is a block diagram of a typical test figure used by automated testing equipment (ATE) to test a packaged power amplifier product.
- ATE automated testing equipment
- FIG. 4 is a simplified functional diagram representing the four stages of the semiconductor microchip fabrication process adapted from Nan Zant, Peter, Microchip Fabrication. A Practical Guide to Semiconductor Processing, Fourth Edition, McGraw Hill, 2000, p. 85.
- FIG. 5 is a schematic block diagram of a preferred system for virtual fixturing of laterally diffused metal oxide semiconductor (“LDMOS”) power transistor devices, according to one aspect of the present invention.
- LDMOS laterally diffused metal oxide semiconductor
- FIG. 6 represents a sample output of a typical frequency-dependent two-port scatter parameter file with scatter parameters revealed in polar form (magnitude and phase angle) for LDMOS devices.
- FIGS. 7 A and 7B represent a sample output of the input and output reflection coefficients from the frequency-dependent two-port scatter parameter file of FIG. 6, graphically depicted on a pair of Smith charts.
- FIG. 8 is a flow diagram of a preferred method for LDMOS device testing employing virtual fixturing.
- FIG. 9 is a diagram showing a physical representation of a preferred universal test fixture for LDMOS device testing employing virtual fixturing.
- FIG. 10 is a schematic block diagram of a preferred system for performing LDMOS device testing employing virtual fixturing.
- microchip device fabrication is commonly thought to take place in a series of four stages, as adapted from Nan Zant, Peter, Microchip Fabrication. A Practical Guide to Semiconductor Processing. Fourth Edition, McGraw Hill, 2000, p. 85.
- Stage 1 is the preparation stage where a crystalline silicon ingot is grown and purified from sand. It is here that individual wafers are prepared and "sliced" from the ingot.
- Stage 2 is the fabrication, or device fabrication stage. Layering, patterning, doping, and heat treatment are among the technologies employed during this stage to create the chips, called die, that become the electronic components in the final packaged product.
- stage 3 precision electrical testing of individual die is performed. This stage is sometimes called the wafer sort stage because bad die are sorted from good die based on the results of the electrical tests.
- stage 4 the die are packaged and tested before being placed into production as live electronic components. Packaging takes many forms but in every case the package chosen helps to protect the product from the harsh operating environment in which the product will operate.
- a transistor device may undergo a host of final tests prior to leaving fabrication. Stress tests, burn-in, temperature treatment, and possibly other tests are often employed during different stages of the fabrication process or during prototyping. It is generally not feasible in a production environment to subject every product to the full battery of tests.
- crucial performance criteria to be tested include DC and RF performance characteristics, which are typically measured during the final packaging and testing stage of the amplifier. Together, DC and RF performance test measurements provide a complete characterization of a product making them useful in passing meaningful quality control judgment on a product before allowing the product to enter the market.
- FIG. 5 is a block diagram of a system 500 for virtual LDMOS device fixturing, in accordance with a general embodiment of the invention.
- Automated test equipment 525 interfaces with a universal test fixture 515 through ATE software 520.
- the input and output impedance matching networks 310 and 315 of FIG. 3 are supplanted in system 500 by the de-embedded input scatter parameter ("S parameter") blocks 505 and 510.
- the input S parameter block 505 and the output S parameter block 510 are "virtual" impedance transformation networks de-embedded (i.e., implemented) in ATE software.
- the system 500 has both a virtual component 515 and a physical component 520.
- some vestiges of the input and output matching network blocks of FIG. 3 must remain as part of system 500 in order to secure the physical connections between the testing equipment and the test fixture.
- the input matching block 310 of FIG. 3 performed the dual function of both impedance matching a test probe connectivity
- the micro-strip implementation of the ATE test fixture of system 500 serves only to secure a test probe to the fixture, the impedance matching function having been de-embedded.
- the output connectivity of the test fixture of system 500 can be made regarding the output connectivity of the test fixture of system 500.
- the input and output matching networks 310 and 315 of the prior art test fixtures are substituted with input S parameter block 505 and S parameter output block 510 by employing a mathematical transformation that maps the input reflection coefficient Sn to its input impedance equivalent, and likewise maps the output reflection coefficient S 2 to its output impedance equivalent.
- the conversion is given by the relationship:
- S and Z parameters permits the S parameter input and output blocks of system 500 to "proxy" the input and output impedance matching networks 310 and 315 of FIG. 3.
- the input and output S parameter blocks exemplify a software or "virtual" transformation.
- the particular de-embedded S parameter blocks integral to virtual device fixturing are fundamental byproducts of power amplifier design. In other words, a design engineer develops the S parameter block components that the test engineer uses during final product testing to present each device with an accurately engineered and calibrated virtual Z transform.
- the modularity of the S parameter blocks allows a test engineer to easily swap blocks between fabrication runs.
- the design engineer may make incremental alterations to the test equipment merely by selecting another S parameter modular block.
- the benefits of the virtual Z transform functionality of the S parameter modular blocks quite nearly eliminate the need to make hardware adjustments altogether.
- S parameter scatter parameter
- the standard three- character extension referencing a two-part S parameter file is "*.S2P.”
- the contents of a typical scatter parameter file are revealed in FIG. 6 over a sample spectrum of frequency ranging from a fundamental frequency of 2.11 to 2.17 GHz and the associated second and third harmonic frequencies of 4.22 to 4.34 GHz and 6.33 to 6.51 GHz, respectively.
- the input reflectivity coefficients over this range of frequencies pass (in polar notation) from 0.96
- Smith charts (convenient for graphically visualizing the frequency-dependent nature of scatter parameters) are provided in FIGS. 7A and 7B.
- End-point 805 of the input reflection coefficient smith chart corresponds with the first polar coordinate (0.96
- the interpolated trace of input reflectivity values terminates at end-point 810 with polar coordinate 0.73
- a similar analysis derives the interpolated trace of the output reflection coefficient beginning with end-point 815 (0.62 [-29.9) and terminating with end-point
- the two-port S parameter file is produced at design-time by the design engineer and later delivered to the test engineer along with specific instruction as to how and when the two-port S parameter file ought to be invoked, and for which device type.
- the test engineer need not know, or even be aware of the specific contents of an S parameter file, as setting tolerances is normally a domain of the designer, who ensures that the all performance criteria are accurately reflected in the two-port S parameter file, allowing for greater uniformity across ATE stations.
- the measured and interpolated set of S parameters together with the aforementioned S-to-Z transformation, form the basis for the virtual device fixturing. While a product endures testing across a range of operating test signal frequencies, the two-port S parameter file ensures that the device is presented with the precise Su parameter (if testing input) or S 22 parameter (if testing output) as derived during design.
- step 905 the method begins by first receiving an assembled, packaged device from a previous manufacturing stage.
- the device is called a product at this stage to differentiate it from its prior existence as a naked die, and to make clear that a product must be packaged prior to insertion into the universal test fixture.
- step 910 the product is inserted into the universal test fixture.
- a principle advantage to the method of and apparatus of FIG. 8 is the universality of the test fixture.
- a single fixture can be used to mount and test each different device type. For instance, a product from a 3 -cell power amplifier fabrication run could be mounted and tested using the same test fixture used to later mount and test a 5-cell power amplifier from a separate manufacturing run.
- FIG. 9 is a diagram showing a device under test 1005 mounted onto a 2® universal test fixture 1000. Every ATE test station is supplied with a single universal test fixture 1000.
- the universal test fixture is part of the ATE apparatus.
- the universal test fixture is cabled to the ATE equipment via an input connector 1010 and an output connector 1015.
- the input and output connectors are threaded female coaxial connectors 25 for electrically coupling the universal test fixture to the ATE with coaxial cable.
- the device under test (DUT) is clamped or otherwise fixed to the universal test fixture housing 1020 for the purpose of ensuring adequate heat dissipation.
- solid electrical contact between the fixture and the respective input and output terminals of the DUT i.e., gate and drain terminals of the LDMOS device
- TM guarantees a proper signal ground for testing.
- a cable properly fastened to each ATE connector 1010, 1015 maintains signal integrity by ensuring that the test signal from the signal generator is properly applied to the device input (gate) or device output (drain), as required.
- Notably absent from the universal test fixture 1000 are the bulky impedance- matching lumped elements.
- two small, unobtrusive one-step impedance transformation elements 1025 (of a dimension just wide enough to accommodate the input and output leads of the device) remain. These two elements only exist on the fixture to correct any impedance mismatch as a result of connectivity.
- the 50-ohm board-level Z transform functionality is absent from the two one-step impedance transforms, having been de-embedded in ATE software as earlier discussed herein.
- step 915 the test engineer establishes connectivity between the universal test fixture and the ATE equipment. This step is optional under the embodiment mentioned above, wherein the universal test fixture is part of the ATE apparatus.
- the test engineer makes a software selection according to the device type of the DUT 920.
- the software selection for a given device type is a simple matter of choosing an option or selecting a file that pairs the input and output S parameter blocks, pre-selected and tuned by the designer, with the specific device type under test.
- the ATE software interface is a graphical interface in which a test engineer makes a software selection by choosing an option, such as by clicking on one or more icons with a pointing device.
- the ATE software is implemented as a command-line or menu-driven interface, in which case S parameter block selection would entail manual or auto-loading a separate file into memory, or choosing an option from a menu.
- the goal of software selection at this step is to input the predetermined S parameter blocks for the DUT to the ATE software running on the test engineer's testing station.
- step 925 the device undergoes DC electrical and large signal RF testing at signal frequencies representative of the eventual operating environment envisioned for the product.
- the large signal RF testing employed preferably pushes the power amplifier into a non-linear operating region, causing the device to generate substantial heat.
- the universal test fixture should be constructed of material(s) capable of withstanding the resulting heat dissipation by virtue of its construction.
- Quality control criteria are applied to the product at step 930, marking the test engineer's ultimate approval or disapproval of a particular DUT' viability, based on results of the testing process.
- a power amplifier package that fails any one of the battery of DC and RF tests employed will normally be discarded.
- the quality control criteria set for a given device run are critical to manufacturability.
- FIG. 10 is a schematic block diagram of a preferred LDMOS test system 700 for performing LDMOS device testing using virtual fixturing in accordance with the invention.
- the test system 700 includes a ATE station 710 having an input probe 712 for coupling to a gate terminal and an output probe 716 for coupling to a drain terminal, respectively, of a LDMOS device 704.
- the ground reference (source) is at the back metal of the device being evaluated and is connected to the same ground plane as the test system 700 during the evaluation.
- a vector network analyzer 720 is coupled to the input and output probes 712 and 716 for measuring one or more performance characteristics, as well as the small signal scatter parameter data, of the LDMOS device 704 using the respective probes.
- the measured performance characteristics include at least one of output power, gain, input return loss, efficiency, inter-modulation distortion, gain compression, and adjacent channel power.
- a processor having virtual fixturing software stored thereon e.g. computer 730
- NNA vector network analyzer
- the system further includes a user interface 740 and display 750 (e.g., for displaying the calibrated performance characteristics of the device 704) to allow for user control and oversight of the testing and evaluation process.
- calibration and fine-tuning of the S parameter blocks may be user-controlled via the virtual fixturing software as loaded and executing on a stand-alone computer workstation, remote terminal, or similar digital computing device or system.
- the input and output S parameter blocks are each implemented as individual files in the virtual fixturing software.
- the S parameter blocks are implemented in ROM, or as firmware, or using other known forms of data storage.
- the apparatus for virtual device fixturing may be embodied as either a turn-key stand-alone system, such as a manufacturing embedded system, or as a modular system wherein a purchaser of the apparatus is able to load the module directly into an existing system, such as a personal computer system.
- the invention also eliminates some of the problems of fixture cross- correlation from ATE to ATE. Calibrating the universal test fixture to a particular device type is a simple matter of either making small adjustments to the de-embedded input and output S parameter blocks in software, or selecting a different set of S
- transistor devices e.g., Bi-Polar or MOSFET transistor devices. Accordingly, the invention is not to be restricted, except as set forth in the following claims and their equivalents.
Abstract
Description
Claims
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
AU2002222391A AU2002222391A1 (en) | 2000-12-26 | 2001-12-21 | Method and device for testing of a transistor using a network analyzer |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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US09/749,027 | 2000-12-26 | ||
US09/749,027 US6541993B2 (en) | 2000-12-26 | 2000-12-26 | Transistor device testing employing virtual device fixturing |
Publications (2)
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WO2002052287A2 true WO2002052287A2 (en) | 2002-07-04 |
WO2002052287A3 WO2002052287A3 (en) | 2002-12-05 |
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PCT/IB2001/002610 WO2002052287A2 (en) | 2000-12-26 | 2001-12-21 | Method and device for testing of a transistor using a network analyzer |
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US (1) | US6541993B2 (en) |
AU (1) | AU2002222391A1 (en) |
TW (1) | TW562933B (en) |
WO (1) | WO2002052287A2 (en) |
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US6965226B2 (en) | 2000-09-05 | 2005-11-15 | Cascade Microtech, Inc. | Chuck for holding a device under test |
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US7492172B2 (en) | 2003-05-23 | 2009-02-17 | Cascade Microtech, Inc. | Chuck for holding a device under test |
US7500161B2 (en) * | 2003-06-11 | 2009-03-03 | Agilent Technologies, Inc. | Correcting test system calibration and transforming device measurements when using multiple test fixtures |
US7250626B2 (en) | 2003-10-22 | 2007-07-31 | Cascade Microtech, Inc. | Probe testing structure |
WO2005065258A2 (en) | 2003-12-24 | 2005-07-21 | Cascade Microtech, Inc. | Active wafer probe |
US7187188B2 (en) | 2003-12-24 | 2007-03-06 | Cascade Microtech, Inc. | Chuck with integrated wafer support |
CN100403038C (en) * | 2003-12-30 | 2008-07-16 | 上海贝岭股份有限公司 | Test circuit of double Rutherford horizontal dual diffusion field-effect transistor conducting resistor |
DE102004014731B4 (en) * | 2004-03-25 | 2007-05-03 | Infineon Technologies Ag | Measuring circuit for the output of a power amplifier and a measuring amplifier comprehensive power amplifier |
JP2008512680A (en) | 2004-09-13 | 2008-04-24 | カスケード マイクロテック インコーポレイテッド | Double-sided probing structure |
JP4828542B2 (en) * | 2004-10-06 | 2011-11-30 | エプコス アクチエンゲゼルシャフト | Impedance detector |
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US20140124678A1 (en) * | 2011-06-02 | 2014-05-08 | Konica Minolta, Inc. | Radiation imaging system |
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US9054793B2 (en) | 2013-07-19 | 2015-06-09 | International Business Machines Corporation | Structure, system and method for device radio frequency (RF) reliability |
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CN105891628B (en) * | 2016-03-30 | 2018-05-29 | 清华大学 | General four port is in piece high frequency De- embedding method |
JP6832654B2 (en) * | 2016-09-09 | 2021-02-24 | 東京エレクトロン株式会社 | Inspection system adjustment method and auxiliary elements used for it |
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- 2001-12-21 WO PCT/IB2001/002610 patent/WO2002052287A2/en not_active Application Discontinuation
- 2001-12-21 AU AU2002222391A patent/AU2002222391A1/en not_active Abandoned
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Publication number | Publication date |
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US6541993B2 (en) | 2003-04-01 |
AU2002222391A1 (en) | 2002-07-08 |
US20020118034A1 (en) | 2002-08-29 |
WO2002052287A3 (en) | 2002-12-05 |
TW562933B (en) | 2003-11-21 |
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