WO2002052803A1

WO2002052803A1 - Distribution/combining packet switching apparatus using brief scheduling information

Info

Publication number: WO2002052803A1
Application number: PCT/KR2001/002275
Authority: WO
Inventors: Yong Il Jun; Man Soo Han; Kyu Ouk Lee; Kwon Chul Park
Original assignee: Electronics And Telecommunications Research Institute; Korea Telecom
Priority date: 2000-12-27
Filing date: 2001-12-27
Publication date: 2002-07-04
Also published as: KR20030074665A; KR20020053664A

Abstract

a distributing/combining packet switching apparatus for use in a next generation packet network is disclosed. The distributing/combining packet switching apparatus includes: a distributing unit including a first predetermined number of unit switch modules each having a second predetermined number of queues, for distributing packets; a queue controlling unit for controlling inputs and outputs of the packets to/from the queues; a distribution arbitrating unit for outputting the packets according to the cyclic link allocation priorities of the packet queues of the distribution switching unit; a combination arbitrating unit for receiving the packets from the distribution switching unit and for outputting the packets without output link contention according to the allocated cyclic priorities of the packet queues of the distribution switching unit; a switching unit having the first predetermined number of unit switch modules, for classifying and outputting the packets based on combining arbitrating information from the combining arbitrating unit; a combining unit having the first predetermined number of unit switch modules, for classifying and queuing the packets based on destination information of the packets and for outputting the packets classified based on the destination information to destination; and a connecting unit for connecting the distributing unit to the switching unit and connecting the switching unit to the combining unit.

Description

DISTRIBUTION/COMBINING PACKET SWITCHING APPARATUS USING BRIEF SCHEDULING INFORMATION

Technical Field • The present invention relates to a packet switching apparatus, and, more particularly, to a distribution/ combining packet switching apparatus for one hop switching with brief scheduling information and an internal blocking scheduling apparatus for use in a next generation packet network .

Background Art

It is widely forecasted that one of an ATM (Asynchronous Transfer Mode) network using IP (Internet Protocol) and an IP network using ATM will be employed as a next generation integrated communication network. The ATM+ network solves inability to directly accommodate a connectionless Internet service by a virtual path characteristic of an ATM while enjoying its benefits, e.g., QOS (Quality Of Service) and so on. The IP+ network solves QOS and network stability problems of an IP network. That is, the next generation integrated communication network would be a packet switching network.

Among the existing packet networks, delay performance of the Internet that recently gets immense popularity shows about "400 ms 90 percentile delay". However, the delay performance required to ensure voice service quality as of a conventional PSTN (Public Switched Telephone Network) telephone is approximately "less than 50 ms 90 percentile delay" .

This low grade delay performance characteristic of the Internet could be caused by its multi-hop switching/routing. That is, since it is difficult to efficiently implement a high scale of routing/switching function, the Internet is conventionally constructed by connecting multiple low scale switch/routers. Therefore, a packet sent from its origination inevitably passes through a complex multi-hop path and arrives at its destination with a large switching delay.

Next, a conventional packet switch will be described in detail.

The packet switches are categorized an output buffering, a shared buffering, an input buffering, and an input and output buffering,^' depending on location of a packet buffer. In the output buffering, the switch operates in N times faster speed than switching input and output link speed, N being the number of the inputs and the outputs in the switch, so that N packets at maximum can be transferred to the outputs per unit time. Therefore, packet buffering occurs only at the outputs and shows ideal performance in respect of throughput and packet delay time. However, in the output buffering, an individual output buffer should have capability of N+l times speed operation, thereby, resulting in high costs of output buffering and difficulty in implementing the large scale switch.

On the other hand, in the shared buffering, shared buffers, having bandwidth 2N times input/output link bandwidth, enable N reading and N writing per unit time so that optimum throughput and packet delay time can be obtained. Also, because one buffer is shared by N inputs and N outputs, minimum packet loss can be acquired with same number of buffers. However, since it is difficult to implement the 2N times speed buffer, the shared buffering can not freely applied to a high speed large scale switch. Using 0.2 um class CMOS semiconductor technique currently available, a switch with throughput of about 40 Gigabit/sec at maximum can be manufactured.

In the input buffering, the input buffer and the switching fabric operate in a link speed. Accordingly, only one packet at one input is transferred to the output and blocked packets are stored at the input buffer. Buffer memory bandwidth required for storing packets in the input buffering is double the speed of packet input speed, which is minimum among the buffering techniques.

However, in spite of those advantages of the input buffering, when a destination output of a head packet stored at a particular input buffer is blocked by a head packet of another input, the maximum throughput is restricted to 58.6 % by HOL (Head-Of-Line) in which the packet can not be transferred even if the destination output of the packet after the head packet are empty.

Since that problem occurs when the input has one FIFO (First In First Out) queue and uses N x N switching fabric, there have been widely studied methods to increase the maximum throughput of the input buffering switch by mitigating this condition. Among them, most widely used one is a method that performs virtual output queuing or N FIFO queuing for every output at each of input buffers and then selects maximum number of packets that can be transferred without output collision when the packet transferred to the output. That is, since N output queues are prepared at each input in a N x N switch, the input packet is stored at the queue corresponding to its output. The switch has N² queues and input/output schedule schedulers of the switch distribute the packets at these N² queues as N outputs fairly and efficiently.

Among operational algorithms for the schedule scheduler, there are mostly known PIM (T. Anderson, S. Owichi, J. Saxe, and C. Thacker, "High Speed Switch Scheduling for Local Area Networks," ACM Transactions on Computer Systems 11, 4, November 1993), RRM, iSLIP (Nick Mckeown, "iSLIP: A Scheduling Algorithm for Input-Queued Switches", IEEE Transactions on Networking, April 1999), 2DRR (R. 0. LaMaire et al, "Two-dimensional round-robin schedulers for packet switches with multiple input queues", IEEE/ACM Trans. Networking, vol. 2, No. 5, Oct 1994), WFA (C. Partridge, et al., "A 50-Gb/s IP router", IEEE/ACM Trans. Networking, vol. 6, pp. 237-248, June 1998), MUCS (H. Duan, "A high-performance OC-12/OC-48 Queue Design Prototype for Input-buffered ATM switches", IEEE Infocom '97, Kobe, Japan, pp. 20-28, April 7-11, 1997), RRGS (A. Smiljanic, "RRGS-Round-Robin Greedy Scheduling for Electronic/Optical Terabit Switches", IEEE GLOBECOM'99, pp. 1244-1250, 1999), and CORP (Cavendish, D. , "High Performance Switching and routing", ATM 2000, Proceedings of the IEEE Conference on High Performance Switching and routing, pp. 55-64, 2000).

Since packet at the input is stored and managed for each of destinations in the switch that uses one of the above scheduling control algorithms, the HOL blocking can be eliminated and high throughput can be accomplished. Mckewon, a developer of the iSLIP among operational algorithms for the schedule scheduler, (Nick McKeown, et al, "Achieving 100% throughput in an input-queued switch", IEEE Transactions on Communications, vol. 47, No. 8, August 1999, pp. 1260-1267) proved that the maximum size matching algorithm accomplishes 100% throughput when input traffic is uniform and the maximum weight matching algorithm accomplishes 100% throughput even under non-uniform traffic environment.

However, the VOQ switch of the input buffering has some problems as follows. Firstly, it requires N² queues and its switching delay characteristic increases in proportional to N during high input load. A number of repeated contention control and high speed contention control apparatus are required for contention control of high throughput. Practically, available maximum speed of the spatial switch during switching is at most about 80Gigabit/sec with currently available 0.2 um class CMOS semiconductor technique, and this speed is not much higher than available maximum speed 40 Gigabit/sec of the shared buffering. Also, it is not proper for the next generation switch oriented to the one hop switching but proper for a structure having a small number of the switch input/outputs and high speed input/output links because its switching delay characteristic is proportional to N, the number of the switch input/output. It substantially requires the packet buffer at the output of the spatial switch because signal paths in the spatial switch operating in high speed are different from each other to obtain packet synchronization at the output.

Therefore, new methods are developed to apply to the next generation switch in which the number of couplings, N, is from several thousands to several myriad and information throughput is from several Terabit/sec to several tens of Terabit/sec. Most of research results for such a large scale switch generally employ the packet buffer at its input/output. To overcome physical restrictions, the large scale switch is constructed by connecting a number of unit switches, each having small switching capability, which evidently induces usage of the input/output buffer to schedule or buffer internal blocking. Among the developed high capacity switches, there are the first generation structures such as StarLite, Moonlite, and SunLite from Bell Lab, of which operate by using algorithm Batcher-Banyan switch network. These structure had not been commercialized because they require huge interconnection network and a lack of QOS security resulted from a packet loss rate related to input traffic pattern.

As the second generation large scale switch structure following the first generation structure, there are Tandem Banyan, ReRouting Banyan, Knockout switch, Growable switch and MSM switch. They are characterized by their probabilistic internal blocking schedule control. They have not yet completely solved the conventional problems of huge interconnection network and a lack of QOS security resulted from probabilistic schedule control. Another second generation switch, a buffered Banyan structure switch of CLOS or BENES network structure schedules internal blocking by using packet buffers within the Babyan network, whose structure is simple, so that it has been used widely as a commercial switching structure. ACE class switches of HAN-BISDN and ATM switches of Alcatel are the buffered Banyan structure switches.

Recently, in large scale inpu /output buffering structures, some methods are developed for deterministic scheduling of the internal blocking. Among them, time reservation technique of Obara (H. Obara, et al., "Input and output queueing ATM switch architecture with spatial and temporal slot reservation control," Electronics Letters, vol. 28, No. 1, Jan. 1992) introduces a structure in which, after each input buffer module sends a request to a schedule scheduler, the schedule scheduler sets transmission grant time for each request and sends it to the input buffer module. This reduces the number of the request used for contention control by reducing the number of the queues of each input port by grouping the input ports. Also, statistical multiplexing gain due to the input port grouping improves the switch performance as a whole.

However, the study mention in the above uses time information for the contention control. Therefore, the amount of time information transmission increases to make it difficult to operate the large scale switch at a high speed. Furthermore, since only one cross bar is used as the switch fabric, the number of the input/output links of the cross bar increases as the number of the input/output ports increases, resulting in difficulties in implementing the large scale switch.

Comparing with the above structures, ATLANTA switch (Fabio M. Chiussi, et al., "The ATLANTA Architecture and Chipset: A Low-Cost Scalable Solution for ATM Networking," ISS'97, pp43-52, 1997) (US patent Nos . 5689500, 5689505, 5689506) has a known CLOS switch fabric structure. As well known, the CLOS switch fabric is non-blocking for circuit switched traffic under a particular condition. Also, for packet switched traffic, it may be non-blocking if packet unit path control is employed. The non-blocking characteristic described above for the CLOS or BEBES switch fabric is because it can be accomplished with minimum cross bar resources (Joseph Y. Hui, "Switching and traffic theory for integrated broadband networks , " Kluwer Academic Publishers, 1990), and this characteristic is widely well- known. Therefore, the ATLANTA switch structure is superior to the Obara structure in terms of extendibility.

An internal blocking schedule control technique of the ATLANTA switch is similar to the SLIP in respect that a packet which fails in the output contention for the cross bar output participates in the next output contention scheduling. An individual input buffer module has packet buffers for queueing for the output and each service class, and a two stage round robin scheduler in the input buffer module selects packets corresponding to the number of the links by connecting the input buffer module and the cross bar for every packet slot for the packets, stored at the buffers. Information of the final output and service class of the selected packets is sent to the scheduler in the cross bar through the corresponding link, and the scheduler in the cross bar selects one of the packets for each cross bar output and sends a transmission grant signal to the input buffer module connected to the selected link. Then, the packet for which transmission is not granted by the scheduler in the cross bar because of the cross bar output contention participates at the next contention scheduling. That is, a round robin pointer moving technique similar to the SLIP is used.

However, the internal blocking scheduling control technique of the ATLANTA switch is not disclosed in detail any more than the description as the above, but it is disclosed that non-blocking characteristic is remained when the internal links are extended by at least 8.6 times according to the references as described above. Therefore, the saturation throughput of the internal blocking scheduling control technique of the ATLANTA switch can reach about 75 %. Another scheduling control algorithm for the CLOS type input/output buffer switch structure is 2DRRMS (M. S. Han, et al, "Fast scheduling algorithm for input and output buffered ATM switch with multiple switching planes," Electrics Letters, vol. 35, No. 23, pp. 1999-2000, Nov. 1999).

As like 2DRR, the 2DRRMS uses a transmission request matrix and a search pattern matrix, and searches the transmission request matrix in order as defined in the search pattern matrix to determine a transmission request to be transmitted. The 2DRRMS performs contention scheduling control for only the HOL packet, and transmits the transmission grant and cross bar information to be used to the input buffer module. Therefore, a number of the cross bars are used to improve the switch throughput but not directly used to extend capability.

Consequently, there is an inevitable demand for one hop switching in the next generation packet network.

Disclosure of the Invention Therefore, it is an object of the present invention to provide a distribution/combining packet switching apparatus, capable of one hop switching with the use of brief scheduling information, and an internal blocking scheduling apparatus for use in a next generation packet network. In accordance with an aspect of the present invention, there is provided a distribution/combining packet switching apparatus for use in a next generation packet network, including: a distributing unit including a first predetermined number of distribution switches each having a second predetermined number of queues, for distributing packets; a queue controlling unit for controlling inputs and outputs of the packets to/from the second number of queues; a distribution scheduling unit for outputting the packets to an output link of the distributing unit based on cyclic link allocation priorities of the queues of the distributing unit; a combination scheduling unit for receiving the packets from the distributing unit and for outputting the packets without output link contention based on the cyclic link allocation priorities of the queues of the distributing unit; a switching unit having the third predetermined number of unit switch modules, for classifying and outputting the packets based on combination scheduling information from the combination scheduling unit; a combining unit having a fourth predetermined number of combination switches, for classifying and queuing the packets based on destination information of the packets and for outputting the packets classified based on the destination information to destination; and a connecting unit for connecting the distributing unit to the switching unit and for connecting the switching unit to the combining unit.

In accordance with another aspect of the present invention, there is provided to an apparatus for arbitrating internal blocking of a distribution/combining packet switching apparatus, including: a queue controlling unit for controlling input/output of a first predetermined number of queues in distribution switches of the distribution/combining packet switching apparatus; a distribution scheduling unit for distributing the packets stored in the first predetermined number of queues of the queue controlling unit to output links of the distribution switches/switches of switching unit; an encoding unit for encoding a second predetermined number of bit distribution information as a log(l) bit queue number assigned in a link; a decoding unit for decoding the encoded log(l) bit distribution information, thereby restoring the second predetermined bit distribution information; and a combination scheduling unit for scheduling input/output link contention of the switching unit/a combining unit from the distributed packets in the distribution scheduling unit. The present invention relates to a large packet switch that has capability of several Terabit/sec to several tens of Terabit/sec system information throughput and demonstrates a switching algorithm and structure proper for a large packet switch capable of accommodating thousands to ten thousands of end users. Also, the present invention can simultaneously accommodate end user interfacing apparatuses for thousands to hundred thousands of lines and several to tens of Gigabit/sec network interfacing apparatuses, and provides a switching algorithm and structure that is capable of one hop switching for use in a next generation packet communications .

Also, the present invention provides a switching algorithm and structure for use in a large scale packet switching, which has 100 % throughput without internal link extension nor speed increase.

Also, the present invention provides a switching algorithm and structure for use in a large scale packet switching, which has switching module unit scalability and modularity so as to cope efficiently with increased switching capability due to increases of subscribers.

The present invention is a large scale switching apparatus, i.e., a distribution/combining packet switch) capable of one hop switching in a next generation packet network. The large scale switching apparatus should accommodate physically in existing PSTN offices, considering that existing telephone subscribers are to be xDSL subscribers or IMT-2000 wireless subscribers. Also, a user-to-network interfacing (UNI) apparatus and a network- to-network interfacing (NNI) apparatus should be accommodated by a switching apparatus for one hop switching. Typically, considering the number of subscribers of a PSTN office reaches to about 50 thousands to 200 thousands lines, and service information speed that the xDSL and IMT-2000 can serve reaches to 2 Mbps to 20 Mbps, the large scale packet switching apparatus of the present invention should have capability of accommodating switching capability of several to tens of Terabit (10¹² bit/sec) and user-to- network interfacing capability of hundred thousands of lines and several hundreds of lines for network-to-network interfacing capability of tens of Gigabit (10⁹ bit/sec). To solve this fact, the internal structure of the present invention has conventional CLOS switch fabric structure and comprises a distribution stage, a switching stage, a combining stage, a distribution scheduler, a combining scheduler and a connection links. Especially, the present invention can use internal link resources efficiently because only log(l) bits corresponding to the number of queues, 1 bit representing schedule grant and schedule cycle synchronization identification signal per link are communicated during internal blocking schedule operation.

Processing delay time of the distribution/combining packet switching apparatus of the present invention is (ki +l)/Do/kι, Do being processing delay time of an ideal output buffer characteristic, ki being the number of the internal multi-link connections. It approaches to the ideal output buffer switching characteristic when kα is much larger than 1. It is at most 2 times the ideal output buffer switching characteristic when ki is 1. Switching saturation throughput is 100%, i.e., strictly speaking non- blocking. Also, by using conventional 0.2 um CMOS semiconductor technique, it is possible to implement a distribution/combining packet switch of 15 Terabit/sec.

Consequently, the present invention can satisfy requirements for the next generation switch which enables one hop switching in the next generation network. Brief Description of the Drawings

The above and other objects and features of the instant invention will become apparent from the following description of preferred embodiments taken in conjunction with the accompanying drawings, in which:

Fig. 1 shows a diagram of one embodiment of a distribution/combining packet switching apparatus in accordance with the present invention; Fig. 2 offers a diagram of one embodiment of an internal blocking scheduler for use in a distribution/combining packet switching apparatus in Fig. 1 in accordance with the present invention;

Fig. 3 provides a detailed diagram of one embodiment of a distribution scheduler for use in an internal blocking scheduler in Fig. 2 in accordance with the present invention;

Fig. 4 is a diagram of one embodiment of an element and operation of a distribution scheduler in Fig. 3 in accordance with the present invention;

Fig. 5 shows a detailed diagram of one embodiment of a combining scheduler for an internal blocking scheduler in Fig. 2 in accordance with the present invention;

Fig. 6 represents a diagram of one embodiment of an element and operation of a combining scheduler in Fig. 5 in accordance with the present invention; and

Fig. 7 offers a diagram for showing switching performance of a distribution/combining packet switching apparatus in accordance with the present invention.

Modes for Carry out the Invention

Hereinafter, preferred embodiments of the present invention and measurement results will be described in detail with reference to the accompanying drawings. Fig. 1 shows a diagram of one embodiment of a distribution/combining packet switching apparatus of the present invention.

Referring to Fig. 1, the distribution/combining packet switching apparatus 1000 of the present invention, whose internal structure is a typical CLOS switch fabric structure, comprises a distribution stage 1100 including i mil x ni unit switch modules 1110-1130, i being an arbitrary natural number, a switching stage 1200 including j m₂ x n₂ unit switch modules 1210-1230, j being an arbitrary natural number, a combining stage 1300 including 1 m₃ x n₃ι unit switch modules 1310-1330, 1 being an arbitrary natural number, and interconnection networks including connection links 1510, 1610 for connecting the distribution stage 1100 to the switching stage 1200 and the switching stage 1200 to the combining stage 1300. Since each of the i mu x i unit switch modules 1110- 1130 having 1 queues as same as the number of the m₃ x n_3i unit switch modules 1310-1330 accommodates directly multi speed rates of subscriber terminals or network interfacing apparatus depending on spatial priority based on each queue for internal link usage, the switching apparatus is capable of one hop switching.

The interconnection network, connecting the distribution stage 1100 to the switching stage 1200, is connected in a form of (ni x m₂) full shuffle by the multiple connection link 1510 having relations of (ki x j = ni) and (ki x i = m₂) introducing a multiple link connection factor ki.

Similarly, the interconnection network, connecting the switching stage 1200 to the combining stage 1300, is connected in a form of (n x m₃) full shuffle by the multiple connection link 1610 having relations of (k x 1 = n₂) and (k₂ x j = m₃) introducing a multiple link connection factor k₂.

Therefore, network topology of the distribution/combining packet switching apparatus 1000 is described by variables of (mu, n₃ι, i, j, 1, k_if k₂) . When

n₃), the distribution/combining switching apparatus 1000 is identical to the CLOS switch network in terms of the network topology. When (mn= mi, n₃ι= n₃), the size of the distribution/combining switching apparatus 1000 is described as (N_±= mi x i), (No= n₃ x 1) by using the network topology (mi, n₃, i, 1).

Hereinafter, the unit switch modules 1110-1130 in the distribution stage 1100 will be referred as distribution switches 1110-1130. The distribution switches 1110-1130 are output queueing switches. The distribution switches 1110-1130 have 1 queues 1111-1113 as same as the number of the unit switch modules 1310-1330 in the combining stage 1300.

Packets that are inputted through ma input links of the distribution switches 1110-1130 are multiplexed and then distributed, based on information of their destinations, into the queues 1111-1113 corresponding to the switch modules 1310-1330 of the combining stages 1300 to which the packets are to be outputted. The ni output stage 1510 and 1 queues 1111-1113 of the distribution switches 1110-1130 form ni x 1 bipartite matching graph. The packets, that are inputted to the distribution switches 1110-1130 and queued, are outputted to the unit switch modules 1210-1230 of the switching stage 1200 by using the output link 1510 determined by the internal blocking scheduler of the present invention as shown in Fig. 2.

The switching stage 1200 includes the switch modules 1210-1230 of typical output buffer switches or cross bar spatial division switches.

Each of the switch modules 1210-1230 discriminates the packets that are inputted through the m₂ input links, based on information of their destinations, and outputs the packets to n₂ output links 1610 connected to the unit switch modules 1310-1330 of the combining stage 1300 to which the packets are to be outputted. If ki = k₂ = 1, that is, the switch fabrics are connected by a single link, the unit switch modules 1210- 1230 act as simple cross bar spatial division switches.

On the other hand, If ki = a and k₂ = b, a and b are constant numbers except 1, that the switch fabrics are connected by multiple links, 'a' number of packets can be stored for each output and each output buffer should use a output buffer switch having ' ' number of output links.

The combining stage 1300 includes the combining switches 1310-1330.

The combining switches 1310-1330 are at least typical output buffer switches for queueing for each output stage or shared buffer switches.

The combining switches 1310-1330 discriminates the packets that are inputted through the m₃ input links, based on information of their destinations, and queues the packets at corresponding buffers 1331-1332 so as to output packets to the output stage 1710 to which the packets are to be outputted. As described above, the distribution/combining packet switching apparatus 1000 has multi-rate subscribers or capability of networks interfacing. That is, end subscribers having relatively low speed and high speed network interfacing apparatuses through large capability DWDM transmission lines can be directly connected to one switch fabric. This is an essential requirement for one hop switching required for the next generation network.

The distribution/combining packet switching apparatus 1000 uses links that are operated at physically various speeds or a group link technique that are uses a number of links operated at a particular speed as a group in order to support the multirate. The latter is better in terms of system module performance but requires a plenty of resources . The interconnection within the distribution/combining packet switching apparatus 1000 is relatively uniform. That is, the interconnection is accomplished in a form of full shuffle of (ni, m₂) or (n₂, m₃) by the multiple connection links 1510, 1610. Assuming that the speed of an arbitrary distribution switch input stage link 1410 is v_±, the speed of the output link 1510 of the distribution stage 1100 is Vj, and the speed of the output link 1610 of the switching stage 1200 is k, the distribution/combining packet switching apparatus 1000 is non-blocking when mu x

Fig. 2 offers a diagram of one embodiment of an internal blocking scheduler for use in a distribution/combining packet switching apparatus in Fig. 1 in accordance with the present invention.

As shown in Fig. 2, the internal blocking scheduler 2000 for use in the distribution/combining packet switching apparatus includes such devices as i queue controllers 2110-2130 for controlling packet input/output for the 1 queues 1111-1113 in the distribution switches 1110-1130 of the distribution stage 1100, distribution schedulers 2210- 2230 for distributing the packets that are stored at the 1 queues 1111-1113 in each of the queue controllers 2110-2130 to the output link 1510 of the distribution switches 1110- 1130 or the switches 1210-1230 of the switching stage 1200, encoders 22120-22113 for encoding each of the n₂ bits distribution information 22111-22113 as log(l) bit queue number that is assigned to the link, decoders 23120-23320 for decoding the encoded log(l) bit distribution information to the n₂ bit distribution information, and j combining schedulers 2310-2330 for scheduling input/output link contention of the switching stage 1200 or combining stage 1300 of the packets that are distributed at the distribution scheduler 2210-2230.

The internal blocking scheduler 2000 for the use in the distribution/combining packet switching apparatus includes i queue controller 2110-2130, i distribution schedulers 2210-2230, 1 combining schedulers 2310-2330, and signal lines 2111-21131, 21211, 21311 for connecting them. The topology of the signal lines is similar to that of the interconnection network as shown in Fig. 1, and includes two networks whose signal directions are opposite to each other.

Next, the operation of the queue controllers 2110-2130 and the distribution controllers will be described in detail, assuming the size of unit switch module is equally 3 x 3 for the sake of simplicity. When i=j=l=3, ι= k₂=l, i.e., size of the unit switch of each of the distribution stage, the switching stage and the combining stage is 3 x 3, the queue controller 2110 should control the packet queues that are discriminated for 3 combining switches 1310-1330 if single link is used. Packet output for the queue 21110 is accomplished through the 3 output links 1510 in the distribution switch 1110, the 3 output links are identified by 0, 1, 2. During packet output, the queue 21110 may use the output links in order of 0 -> 2 -> 1, the queue 21120 may use the output links in order of 1 -> 0 -> 2, and the queue 21130 may use the output links in order of 2 -> 1 -> 0, as shown in Fig. 2. If a number of queues 21110 - 21130 compete each other to use a particular output link, then the queue that has the highest priority can use the desired output link. For instance, in case of packets queueing in all queues 21110 ~ 21130, distribution of service occurs as the number 0 link is for the queue 21110; the number 1 link is for the queue 21120; the number 2 link is for the queue 21130.

That is, the distribution scheduler 22110 assigns cyclically the output links to be used by the individual queue of which requests output. The number of the output links that can be assigned to the individual queue is the number by which the packets , that are inputted to the distribution switch 1110 and stored, can be outputted within output link unit packet output time or a whole link number . Unit packet output time means the time taken for the distribution switch to output one packet by using the output link.

Also, when the output links are distributed cyclically to the queues, an identical output link should not be assigned to different queues with an identical priority during unifrom packet output time.

That is, the case in that the output links are assigned to one queue in order of 0 -> 2 -> 1 and to the other queue in order of 1 -> -> 0- is violated to the link assignment method as described above because a second link is duplicated in a second priority.

In general, when the number of the output links is smaller than the number of the queues of the distribution switch 1110, e.g., there are 4 queues but 2 links and the 2 links are represented by 0 and 1 and the 4 queues are represented by Ql, Q2 , Q3 and Q4, the links are assigned to each queue as in order of Q1:0 ->1, Q2 : 1 ->0, Q3:0 ->1, Q4 : 1 ->0,. Accordingly, for assignment as described above, two packet input/output cycles are required. That is, during the first cycle, the links are assigned in time and spatial priority of (Ql: 0->l, Q2:l->0), (Q3:0->1, Q4:l->0) and, during the second cycle, the links are assigned in time and spatial priority of (Q3:0->1, Q4:l->0), (Ql: 0->l, Q2:l->0). The parenthesis means identical spatial priority. The output links are cyclically assigned to the queues of different queue controllers 2110-2230 for preventing the queues corresponding to an identical combining switch 1310 from assigning an identical output link at identical packet output time with an identical priority. That is, the queues 21110, 21210, 21310 that stores the packets toward a first combining stage can have output link assignment priority such as 0->2->l, 2->l->0, l->0->2 as shown in Fig. 2.

The distribution schedulers 2210-2230 perform the output link assignment for each of the queues. That is, the queue controller sends information for a number of the packets that are stored at the corresponding queue to the distribution scheduler 2210 through the signal lines 21111- 21131. Then, the distribution scheduler 2210 controls to assign one output link at one output cycle to only one queue and assign output links with the spatial priority as described above to each individual queue.

As shown in Fig. 2, in the distribution scheduler 2210, there are 3 x 3 matrixes, whose rows correspond to queues and columns corresponds to the output links. Each element of the matrixes is classified as three patterns of black color, chessboard and inclined patterns, representing the spatial priority described.

The distribution schedulers 2210-2230 controls contention for distribution stage output links for the individual queue, and outputs the contention control result to the encoder 22120 by using the signal lines 22111-22113. The distribution information 22111-3, 22211, 22311 is n_x bits and depicts that a particular queue is assigned to a particular distribution switch output link. By encoding 22120-22310 the distribution information 22111-22113 as a total of 1 x ni bits for individual distribution scheduler to the queue number assigned to each output link with this characteristic, the distribution information 22114-22116 compressed to x log(l) bits is outputted to the combining scheduler 23110-23310. Therefore, the distribution contention control result from the distribution schedulers 2210-2230 are log(l) bits corresponding to the queue number assigned to each of the ni distribution stage output links, to which output cycle identification information for priority information is appended.

The distribution information 2211-3, 22211, 22311, whose contention is controlled to output the queued packets though the output stage of the distribution switch by each of the distribution schedulers 2210-2230, is discriminated for the unit switch modules 1210-1230 of an identical switching stage 1200 and their contention is controlled again for the output links of the switching stage 1200 by the combining schedulers 2310-2330. That is, since the signals, 22111, 22211, 22311, that are the results of distribution control for the queues 21110, 21210, 21310, are those of the distribution contention control result for the packets to the unit switch modules 1210-1230 of the identical switching stage 1200 in Fig. 2, they are applied to the combining scheduler 2310 where contention control is performed for the output link 1610 of the switching stage 1200.

The combining schedulers 2310-2330 control packet contention induced at the input link 1610 of the combining stage 1300 or output link 1610 of the switching stage 1200. Information 23110 that is generated by decoding the schedule information 22114-6, 22214, 22314 that have been compressed to log(l) bits means that the packet can be outputted to the combining stage 1300 through the output link corresponding to the distribution switch when a bit, corresponding to a particular queue number, is logic true. To the utmost i x ki packets can be inputted to the unit switch module of an identical switching stage from the different distribution switch and the packets that are inputted during a particular packet input cycle can be inputted to a particular combining switch 1310 through k₂ output link 1610 during subsequent packet output cycle.

The combining schedulers 2310-2330 select k₂ allowed to be outputted, among the i x k_x distribution schedule information that are produced for the unit switch modules 1210-1230 in one switching stage 1200 per 1 combining stage, for all of the unit switch modules 1210-1230.

Therefore, the combining schedulers 2310-2330 select k₂ elements per 1, whose logic value are true among the elements of (i x ki) x 1 distribution schedule signal matrix (23110-23310) that consists of the output signals of the distribution schedulers 2210-2230. This selection proceeds based on the spatial priority depending on the output link selection priority used by the queue for each destination as described above. When ki = k₂ = 1, this selection is as similar as simple round-robin matching procedure using fixed priority.

As shown in Fig. 2, the combining scheduler matrix 23110 shows the case of ki = k₂ = 1, that is 3 x 3 matrix, having three columns corresponding to the queues and three rows corresponding to the links. Each element of the matrix is represented by one of black color, chessboard and inclined patterns and has spatial priority as described above. Here, the combining scheduler 2310 performs contention control for the combining stage input links by the known round-robin matching procedure, proceeding in a direction from the black color row to the chessboard row for each column.

The schedule result in the matrixes 23110-23310 depicts whether or not the queue for each destination, whose distribution is scheduled through the corresponding link by internal blocking contention control performed by the distribution schedulers 2310-2330 for the output links of the distribution stage and the switching stage, can transmit the packet. The encoders 23120-23320 encode the schedule result to 1 bit result information 23112 to apply to the decoder 22120 of the distribution scheduler 2210. The decoder 22120 decodes the schedule result by comparing with combining schedule request signals 22111-22113 inputted at early stage of the corresponding schedule cycle and stored. The decoded result information is distributed to the queue of its destination by the queue controllers 2110-2130. The queue controllers 2110-2130 sequentially output and transmit to the distribution stage the packets that are stored at the HOL as the output links assigned to the corresponding queue as denoted by the schedule result information.

As described above, the internal blocking scheduler 2000 for use in the distribution/combining packet switch assigns fixed spatial priority at every schedule cycle for the links used by the unit switching modules. Such fixed spatial priority assignment at every schedule cycle means that the spatial priority assignment can be reset for every schedule cycle for fairness of switching performance for each link, for which input schedule cycle information should be supplied synchronously as a whole. Due to this characteristic, for one input schedule cycle, that is, even if the distribution scheduler and combining scheduler performs scheduling once, throughput higher than 90 % under all switch input load condition can be obtained in a simulation.

During high load operation in which the queues for all destinations store the packets, all queues have ki designated packet output link fixedly assigned based on the link assignment spatial priority. Therefore, under random fair packet input condition, they operate as M/D/l queues. Accordingly, processing delay time of such a distribution/combining packet switch 1000 has (kι+l)D₀/ ki , Do being the processing delay time of an ideal output buffer switch, and approaches to the ideal output buffer characteristic when ki is much larger than 1 and at most 2 times the ideal output buffer performance even when ki is 1 as in an economical state. Of course, switch saturation throughput is 100 %, i.e., strictly speaking it is non- blocking.

It will be described in detail for construction and operation of the distribution scheduler 2210 for use in the internal blocking scheduler referring to Fig. 3 and 4.

Fig. 4 shows elements and operation of a distribution scheduler, and Fig. 3 provides a distribution scheduler for the use in a distribution stage switch, which is constructed by 25 elements as shown in Fig. 4, has 5 queues and 5 output links .

As shown in Fig. 4, the element 4000 of the distribution scheduler has input/output signals such as an initialization signal rst, a synchronization signal tck, input information for the remaining number of the queues rqn_i, output information for the remaining number of the queues rqn_o, link reservation input information grh__i for representing that the corresponding link is reserved by another element having higher spatial priority or not, link reservation output information grh_o, and information odisel for representing that the queue and the link corresponding to the element is reserved for packet output.

The element 4000 of the distribution scheduler executes the following operation by using information for the remaining number of the queues rqn_i and information grh_i for representing that the packet is assigned to the corresponding output link by the previous element.

If rqn_i is not 0, i.e., there are remaining packets to be assigned, and grh_i is ' 0 ' , i.e., the corresponding output link is not reserved by the previous element having higher spatial priority, a value of rqn_i-l is assigned to rqn_o and a logic '1' value is assigned to grh_o. At this time, the odisel has logic ' 1 ' that means the packet is assigned to the corresponding queue and the corresponding output link.

However, if rqn_i is not 0, i.e., there are no remaining packets to be assigned, and grh_i is not 0, i.e., the corresponding output link is not reserved by the previous element having higher spatial priority, the rqn_o input value is assigned to the rqn_i and the grh_I input value is assigned to the grh_o. When both are identical, the odisel has a logic '0' value that means the packet is not assigned to the corresponding queue and the corresponding output link.

Also, even in the case of the information of remaining queues, rqn__I , is 0, i.e., there are no remaining packets to be assigned, the rqn_o input value is assigned to the rqn_i and the grh_I input value is assigned to the grh_o. Also, the odisel has a logic '0' value that means the packet is not assigned to the corresponding queue and the corresponding output link.

The operation as described above is similar to the operation algorithm of an element 4100 in Fig. 4. The rst and tck signals as shown in Fig. 4 are a synchronization clock and a construction element initialization signal for controlling every schedule cycle.

Fig. 3 offers a diagram of a distribution scheduler having the elements .

In Fig. 3, the distribution scheduler 3000 includes a spatial switch 3200, the elements 3800, 3810, 3900 as shown in Fig. 4, the connection signals 3700, 3600, distribution scheduler input/output signal stages 3100, 3500. The spatial switch 3200 assigns variably the output link spatial priority of the queues 1111-1113 based on the packet output cycle (unit packet output time) and the location of the distribution scheduler in the switch.

The input of the spatial switch 3200 are information signals 21111-21131, 3100 for the number of packets with released queueings and a signal 3400 for information added with the modulo algorithm of the packet output cycle and the location of the distribution scheduler in the switch. Based on the signal 3400, the input signal 3100 is circulated and outputted to the output stage 3300. Here, information on allocation of the distribution switch 1110- 1130 means the internal sequential location of the distribution switch module, assigning that of 1110 as 0, of 1120 as 1 and so on. That is, the spatial switch performs barrel shifter operation according to the signal 3400 cycled and output the input signal 3100.

A matrix part, critical prospective part of the distribution scheduler, consists of the elements as shown in Fig. 4. The columns of the matrix correspond to the queues and the rows of the matrix correspond to the output links of the distribution switch. The rqn_i of the element on a diagonal line receives the remaining packet information of the queue controller that is inputted in order of the spatial priority determined by the spatial switch 3200. Also, because the grh_i of the element on the diagonal line, representing link reservation information is fixed as the '0' 3810, this location is a starting point of the distribution schedule and has highest priority. The elements on the diagonal line block asynchronous feedback loop for hardware implementation. In the matrix that consists of the elements as shown in Fig. 4, the row signals grh_i and grh_o are connected by the signal line 3600 to form a loop. The row loop signal lines are disconnected while they go through the elements on the diagonal line. Also, the column signals rqn_I and rqn_o are connected by the signal line 3600 to form a loop. The column loop signal lines are disconnected while they go through the elements on the diagonal line.

For the sake of convenience, the rst, tck signals commonly inputted to the elements are not shown in Fig. 3. When the queue remaining packet information is inputted to the distribution scheduler in Fig. 3, the distribution scheduler distributes the packets to be outputted to the output links uniformly based on the link spatial priority of each of the queues. The distribution result, n₂ bit signal for each queue is inputted to the combining scheduler through the output stage 3500.

When the distribution scheduler is implemented by using 0.2 um CMOS semiconductor technique, approximately 250 Kgates logic elements are required in a 64 x 64 matrix scale and maximum operation speed is about 37 ns. Assuming that packet slot time is 4 times of the maximum operation speed, a distribution controller for use in a about 15 Terabit/sec class distribution/combining packet switch can be implemented by the conventional semiconductor technique. Now, referring to Figs. 5 and^' 6, it will be described in detail for construction and operation of the combining scheduler 2310 for use in the internal blocking scheduler.

Fig. 6 provides elements and operational algorithm of a combining scheduler, and Fig. 5 shows a combining scheduler consisting of 25 elements as shown in Fig. 6, for use in a distribution switch having 5 queues and a combining scheduler having 5 input links.

The combining scheduler element 6000 shown in Fig. 6 has input/output signals such as an initialization signal rst, information init_d, being the starting point of scheduling operation during initialization, for representing that it is located on a diagonal line 5300 of a element matrix, a operation synchronization signal tck, input information rqn_i for the remaining number of the combining stage input links that are not assigned, output information rqn_o for the remaining number of the combining stage input links that are not assigned, information grh_i for representing that the corresponding link is reserved by another element having higher spatial priority or not, link reservation output information grh_o, a pointer input signal po_i for depicting the starting point of the scheduling operation, i.e., the element having the highest priority, at every schedule cycle, a 1 bit schedule input information disel for the corresponding element among the n₂ bit input signals outputted from the distribution scheduler, and information odisel for representing that the queue and the link corresponding to the element is reserved for packet output by the combining scheduler. The element 6000 of the combining scheduler performs following operation by using the signals as described above. In Fig. 6, the reference number 6100 depicts operational initialization operation of the element 6000. That is, if the rst is true, the corresponding element has the highest priority when allocated on the diagonal line of the matrix. In the hardware, the signal po_o blocking feedback of the asynchronous loop signal within the scheduler 5000 is initialized as the logic value 1 to declare that the corresponding element is located 5300 on the diagonal line of the matrix. Also, since it is operational initialization operation while the rst is true, the schedule result signal, ocsel, is made to ^J 0 ' so as to declare unscheduled status.

In Fig. 6, the reference number 6200 describes main operation of the element 6000. That is, when the pointer output signal po_o is true, the element is located on the diagonal line of the matrix and has the highest priority. Therefore, because k₂ combining stage input links that can be assigned to the corresponding queue are not assigned yet, the rqn_o is assigned as k₂-l and the grh_o and the ocsel depicting that the corresponding element is reserved for the schedule are assigned as the logic 'true' if the schedule input information disel is true. However, if the disel is false, the corresponding element has the highest priority, but the rqn_o is assigned as k₂ and the grh_o and the ocsel depicting that the corresponding element is reserved for the schedule are assigned as the logic 'false' since there is no distribution schedule result.

On the other hand, if the po_o is false, i.e., the element is located on other than the diagonal line of the matrix, the disel is true, the grh_i is false, and the rqn_i is not 0, that is, the packet is transmitted to the corresponding queue and link and the corresponding link is not occupied by the higher priority element and there is the combining input link that can be assigned, the rqn_o is assigned as a value of the inputted rqn_i -1 and the grh_o and the ocsel depicting that the corresponding element is reserved for the schedule are assigned as logic true. However, if the disel is false, the grh_i is true, or the rqn_i is 0, the rqn_o is assigned as the inputted rqn_i and the grh_o and the ocsel depicting that the corresponding element is reserved are assigned as logic false since there is no distribution schedule result.

In Fig. 6, in the reference number 6000, the pointer signal po_o representing that it is located on the diagonal line of the matrix after the initialization operation is shifted to another element at right side or left side at every schedule cycle. In Fig. 5, the combining scheduler 5000 receives and distributes 1 x n₂ bit distribution schedule result input signal 5100 to the corresponding elements 5300, selects k₂ elements whose distribution schedule result disel is true among the elements that are located on each column based on the operation as described above, and notifies the queue controller that the corresponding packets can be transferred to the final combining switch without internal blocking by using the combining schedule result output signal 5200. Here, the row loop signal line 5600 is a path for connecting the po_i to po_o and rqn_i to rqn_o and the column loop signal line 5700 is a path for connecting the grh_o to grh_i signals.

Here, referring to Fig. 7, performance of a distribution/combining packet switching apparatus of the present invention will be discussed.

In Fig. 7, there is provided a computer simulation result of switching delay characteristic of the distribution/combining switch when the distribution switch, the unit switch of the switching stage and the combining switch are uniformly 64 x 64 and 4096 x 4096 distribution/combining packet switch in form of the CLOS switch network of single link connection using the above switches is loaded uniformly by random load.

In Fig. 7, the present invention shows 2 times delay of ideal output buffer switch characteristic as a whole as described above.

As described above, the present invention is capable of large multirate packet switching for the next generation packet network by using a scheduling technique of high throughput by using spatial priority assigned for each queue in internal link usage. While the present invention has been shown and described with respect to the particular embodiments, it will be apparent to those skilled in the art that many changes and modifications may be made without departing from the spirit and scope of the invention as defined in the appended claims.

Claims

1. A distribution/combining packet switching apparatus for use in a next generation packet network, comprising: a distributing means including a first predetermined number of distribution switches each having a second predetermined number of queues, for distributing packets; a queue controlling means for controlling inputs and outputs of the packets to/from the second number of queues; a distribution scheduling means for outputting the packets to an output link of the distributing means based on cyclic link allocation priorities of the queues of the distributing means; a combination scheduling means for receiving the packets from the distributing means and for outputting the packets without output link contention based on the cyclic link allocation priorities of the queues of the distributing means; a switching means having the third predetermined number of unit switch modules, for classifying and outputting the packets based on combination scheduling information from the combination scheduling means; a combining means having a fourth predetermined number of combination switches, for classifying and queuing the packets based on destination information of the packets and for outputting the packets classified based on the destination information to destination; and a connecting means for connecting the distributing means to the switching means and for connecting the switching means to the combining means.

2. The apparatus as recited in claim 1, wherein the second predetermined number is the same as the fourth predetermined number so as to accommodates multirate end subscriber/network interfacing apparatus enabling with one hop switching.

3. The apparatus as recited in claim 1, wherein the queue controlling means controls the packet queues classified by the fourth predetermined number of the combining means .

4. The apparatus as recited in claim 1, wherein the distribution scheduling means schedules the distribution of the output link based on a spatial priority in accordance with each queue as an identical output link is assigned to one queue in the same output cycle.

5. The apparatus as recited in claim 1, wherein the combination scheduling means controls packet contentions resulted from the input link of the combining means and the output link of the switching means .

6. The apparatus as recited in claim 1, wherein the distribution scheduling means includes a plurality of elements each having an operation initialization signal rst, an operation synchronization signal tck, input information for the remaining number of the queues rqn_i, output information for the remaining number of the queues rqn_o, link reservation input information grh_i for representing that the corresponding link is reserved by another element having higher spatial priority or not, link reservation output information grh_o, and information odisel for representing that the queue and the link corresponding to the element are reserved for packet output, wherein, based on information for the remaining number of the queues rqn_i and information grh_i for representing that the packet is assigned to the corresponding output link by the previous element, wherein the elements are formed to a square matrix, columns of the square matrix correspond to the queues and the rows of the square matrix correspond to the output links of the distribution switch, the rqn_i of the element on a diagonal line receives the remaining packet information of the queue controller that is inputted in order of the spatial priority determined by the spatial switch, the grh_i of the element on the diagonal line is fixed as the logic '0', this location is a starting point of the distribution schedule and has highest priority, and the elements on the diagonal line block asynchronous feedback loop for hardware implementation, by receiving the information for the remaining queues, the packets to be outputted to the output links are distributed uniformly based on the link spatial priority of each of the queues.

7. The apparatus as recited in 6, wherein if the rqn_i is not 0, and grh_i is '0', a value of rqn_i-l is assigned to rqn_o, a logic '1' value is assigned to grh_o, and the odisel of the element has a logic ^J l ' indicating that the packet is assigned to the corresponding queue and the corresponding output link, and, if otherwise, the input value of the rqn_i is assigned to the rqn_o, the input value of the grh__i is assigned to the grh_o, and the odisel of the element has a logic '0' value indicating that the packet is not assigned to the corresponding queue and the corresponding output link.

8. The apparatus as recited in claim 6, wherein the combination scheduling means includes a plurality of elements each having an operation initialization signal rst, information init_d, which is a starting point of scheduling operation during initialization, for representing that the element is located on a diagonal line of a square matrix, a synchronization signal tck, input information rqn_i for the remaining number of the combining stage input links that are not assigned, output information rqn_o for the remaining number of the combining stage input links that are not assigned, information grh_i for representing that the corresponding link is reserved by another element having higher spatial priority or not, link reservation output information grh_o, a pointer input signal po_i for depicting the starting point of the scheduling operation, i.e., the element having the highest priority, at every schedule cycle, a pointer output signal po_o, a schedule input information disel for the corresponding element among the bit input signals outputted from the distribution scheduling means, and information ocsel for representing that the queue and the link corresponding to the element is reserved for packet output by the combination scheduling means, and wherein the elements are formed to a square matrix for distributing input signals that are distribution schedule results to the corresponding elements, selecting the elements whose distribution schedule result disel is true among the elements that are located on each column and notifying the queue controlling means that the corresponding packets can be transferred to the final combination switch without internal blocking by using the combining schedule result output signal.

9. The apparatus as recited in claim 8, wherein if the synchronization clock rst that controls every scheduling cycle is true, the corresponding element has the highest priority, and in the hardware, the signal po_o blocking feedback of an asynchronous loop signal in the combination scheduling means is initialized as a logic value of 1 to declare that the corresponding element is located on the diagonal line of the square matrix, since it is in operation initialization stage when the rst is true, the schedule result signal ocsel is made to '0' so as to declare unscheduled status, wherein during operation performance of the combination scheduling means, when the po_o is true, the element is located on the diagonal line of the matrix and has the highest priority, and therefore, because the predetermined number of input links of the combining means that can be assigned to the corresponding queues are not assigned, the rqn_o is assigned with -1 in the predetermined number, if the distribution schedule result disel is true, and then grh_o and ocsel indicating that the corresponding element is reserved for scheduling are assigned as the logic 'true', if the disel is false, since the corresponding element has the highest priority but there is no distribution results, and then the rqn_o is assigned with the predetermined number and the grh_o and the ocsel depicting that the corresponding element is reserved are assigned as the logic 'false', if the po_o is false, the disel is true, the grh_i is false, and the rqn_i is not 0, the rqn_o is assigned as a value of the inputted rqn_i -1 and the grh_o and the ocsel depicting that the corresponding element is reserved are assigned as logic 'true', if the disel is false, the grh_i is true, or the rqn_i is 0, since there is no distribution schedule result, the rqn_o is assigned as the inputted rqn_i and the grh_o and the ocsel depicting that the corresponding element is reserved are assigned as logic 'false'.

10. An apparatus for arbitrating internal blocking of a distribution/combining packet switching apparatus, comprising: a queue controlling means for controlling input/output of a first predetermined number of queues in distribution switches of the distribution/combining packet switching apparatus ; a distribution scheduling means for distributing the packets stored in the first predetermined number of queues of the queue controlling means to output links of the distribution switches/switches of switching means; an encoding means for encoding a second predetermined number of bit distribution information as a log(l) bit queue number assigned in a link; a decoding means for decoding the encoded log(l) bit distribution information, thereby restoring the second predetermined bit distribution information; and a combination scheduling means for scheduling input/output link contention of the switching means/a combining means from the distributed packets in the distribution scheduling means.

11. The apparatus as recited in claim 10, wherein the queue controlling means controls the queues classified by the combining means.

12. The apparatus as recited in claim 10, wherein the distribution scheduling means controls that the output link is assigned to one of the queues at an output cycle and the output link is assigned based on the spatial priority.

13. The apparatus as recited in claim 10, wherein the combination scheduling means controls packet contentions occurred in the input link of the combining means and the output link of the switching means .

14. The apparatus as recited in any one of claims 10 to 13, wherein the distribution scheduling means includes a plurality of elements each having an operation initialization signal rst, an operation synchronization signal tck, input information for the remaining number of the queues rqn_i, output information for the remaining number of the queues rqn_o, link reservation input information grh_i for representing that the corresponding link is reserved by another element having higher spatial priority or not, link reservation output information grh_o, and information odisel for representing that the queue and the link corresponding to the element are reserved for packet output, wherein, based on information for the remaining number of the queues rqn_i and information grh_i for representing that the packet is assigned to the corresponding output link by the previous element, wherein the elements are formed to a square matrix, columns of the square matrix correspond to the queues and the rows of the square matrix correspond to the output links of the distribution switch, the rqn_i of the element on a diagonal line receives the remaining packet information of the queue controller that is inputted in order of the spatial priority determined by the spatial switch, the grh_i of the element on the diagonal line is fixed as the logic '0', this location is a starting point of the distribution schedule and has highest priority, and the elements on the diagonal line block asynchronous feedback loop for hardware implementation, by receiving the information for the remaining queues, the packets to be outputted to the output links are distributed uniformly based on the link spatial priority of each of the queues.

15. The apparatus as recited in claim 14, wherein if the rqn_i is not 0, and grh_i is '0', a value of rqn_i-l is assigned to rqn_o, a logic '1' value is assigned to grh_o, and the odisel of the element has a logic '1' indicating that the packet is assigned to the corresponding queue and the corresponding output link, and, if otherwise, the input value of the rqn_i is assigned to the rqn_o, the input value of the grh_i is assigned to the grh_o, and the odisel of the element has a logic '0' value indicating that the packet is not assigned to the corresponding queue and the corresponding output link.

16. The apparatus as recited in claim 14, wherein the combination scheduling means includes a plurality of elements each having an operation initialization signal rst, information init_d, which is a starting point of scheduling operation during initialization, for representing that the element is located on a diagonal line of a square matrix, a synchronization signal tck, input information rqn_i for the remaining number of the combining stage input links that are not assigned, output information rqn_o for the remaining number of the combining stage input links that are not assigned, information grh_i for representing that the corresponding link is reserved by another element having higher spatial priority or not, link reservation output information grh_o, a pointer input signal po_i for depicting the starting point of the scheduling operation, i.e., the element having the highest priority, at every schedule cycle, a pointer output signal ρo_o, a schedule input information disel for the corresponding element among the bit input signals outputted from the distribution scheduling means, and information ocsel for representing that the queue and the link corresponding to the element is reserved for packet output by the combination scheduling means , and wherein the elements are formed to a square matrix for distributing input signals that are distribution schedule results to the corresponding elements, selecting the elements whose distribution schedule result disel is true among the elements that are located on each column and notifying the queue controlling means that the corresponding packets can be transferred to the final combination switch without internal blocking by using the combining schedule result output signal.

17. The apparatus as recited in claim 16, wherein if the synchronization clock rst that controls every scheduling cycle is true, the corresponding element has the highest priority, and in the hardware, the signal po_o blocking feedback of an asynchronous loop signal in the combination scheduling means is initialized as a logic value of 1 to declare that the corresponding element is located on the diagonal line of the square matrix, since it is in operation initialization stage when the rst is true, the schedule result signal ocsel is made to '0' so as to declare unscheduled status, wherein during operation performance of the combination scheduling means, when the po_o is true, the element is located on the diagonal line of the matrix and has the highest priority, and therefore, because the predetermined number of input links of the combining means that can be assigned to the corresponding queues are not assigned, the rqn_o is assigned with -1 in the predetermined number, if the distribution schedule result disel is true, and then grh_o and ocsel indicating that the corresponding element is reserved for scheduling are assigned as the logic 'true', if the disel is false, since the corresponding element has the highest priority but there is no distribution results, and then the rqn_o is assigned with the predetermined number and the grh_o and the ocsel depicting that the corresponding element is reserved are assigned as the logic 'false', if the po_o is false, the disel is true, the grh_i is false, and the rqn_i is not 0, the rqn_o is assigned as a value of the inputted rqn_i -1 and the grh_o and the ocsel depicting that the corresponding element is reserved are assigned as logic 'true', if the disel is false, the grh_i is true, or the rqn_i is 0, since there is no distribution schedule result, the rqn_o is assigned as the inputted rqn_i and the grh_o and the ocsel depicting that the corresponding element is reserved are assigned as logic 'false'.

18. The apparatus as recited in claim 14, wherein the internal blocking scheduling means communicates only log(l) bits corresponding to the number of queues in the distribution switch, 1 bit representing schedule grant and schedule cycle synchronization identification signal per link during internal blocking schedule operation, there efficiently using internal link resources.