WO2002057908A3 - A superscalar processor having content addressable memory structures for determining dependencies - Google Patents

A superscalar processor having content addressable memory structures for determining dependencies Download PDF

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Publication number
WO2002057908A3
WO2002057908A3 PCT/US2002/000319 US0200319W WO02057908A3 WO 2002057908 A3 WO2002057908 A3 WO 2002057908A3 US 0200319 W US0200319 W US 0200319W WO 02057908 A3 WO02057908 A3 WO 02057908A3
Authority
WO
WIPO (PCT)
Prior art keywords
superscalar processor
addressable memory
content addressable
dependencies
memory structures
Prior art date
Application number
PCT/US2002/000319
Other languages
French (fr)
Other versions
WO2002057908A2 (en
Inventor
Micah C Knapp
Poonacha P Kongetira
Marc E Lamere
Julie M Staraitis
Original Assignee
Sun Microsystems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sun Microsystems Inc filed Critical Sun Microsystems Inc
Priority to JP2002558126A priority Critical patent/JP2004529405A/en
Priority to EP02701018A priority patent/EP1354267A2/en
Publication of WO2002057908A2 publication Critical patent/WO2002057908A2/en
Publication of WO2002057908A3 publication Critical patent/WO2002057908A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
    • G06F9/384—Register renaming
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
    • G06F9/3858—Result writeback, i.e. updating the architectural state or memory

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)

Abstract

A superscalar processor having a content addressable memory structure that transmits a first and second output signal is presented. The superscalar processor performs out of order processing on an instruction set. From the first output signal, the dependencies between currently fetched instructions of the instruction set and previous in-flight instructions can be determined and used to generate a dependency matrix for all in-flight instructions. From the second output signal, the physical register addresses of the data required to execute an instruction, once the dependencies have been removed, may be determined.
PCT/US2002/000319 2001-01-16 2002-01-02 A superscalar processor having content addressable memory structures for determining dependencies WO2002057908A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2002558126A JP2004529405A (en) 2001-01-16 2002-01-02 Superscalar processor implementing content addressable memory for determining dependencies
EP02701018A EP1354267A2 (en) 2001-01-16 2002-01-02 A superscalar processor having content addressable memory structures for determining dependencies

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/761,494 US6862676B1 (en) 2001-01-16 2001-01-16 Superscalar processor having content addressable memory structures for determining dependencies
US09/761,494 2001-01-16

Publications (2)

Publication Number Publication Date
WO2002057908A2 WO2002057908A2 (en) 2002-07-25
WO2002057908A3 true WO2002057908A3 (en) 2002-11-07

Family

ID=25062382

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2002/000319 WO2002057908A2 (en) 2001-01-16 2002-01-02 A superscalar processor having content addressable memory structures for determining dependencies

Country Status (4)

Country Link
US (1) US6862676B1 (en)
EP (1) EP1354267A2 (en)
JP (1) JP2004529405A (en)
WO (1) WO2002057908A2 (en)

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US7681018B2 (en) 2000-08-31 2010-03-16 Intel Corporation Method and apparatus for providing large register address space while maximizing cycletime performance for a multi-threaded register file set
US7437724B2 (en) * 2002-04-03 2008-10-14 Intel Corporation Registers for data transfers
JP3734032B2 (en) * 2002-07-25 2006-01-11 日本電気株式会社 Information processing apparatus and memory control method thereof
US7475232B2 (en) * 2005-07-19 2009-01-06 International Business Machines Corporation Performance of an in-order processor by no longer requiring a uniform completion point across different execution pipelines
US7958336B2 (en) * 2008-06-30 2011-06-07 Intel Corporation System and method for reservation station load dependency matrix
US8127116B2 (en) * 2009-04-03 2012-02-28 International Business Machines Corporation Dependency matrix with reduced area and power consumption
US20100257341A1 (en) * 2009-04-03 2010-10-07 International Business Machines Corporation Selective Execution Dependency Matrix
US20100257339A1 (en) * 2009-04-03 2010-10-07 International Business Machines Corporation Dependency Matrix with Improved Performance
EP2583879B1 (en) * 2010-06-18 2020-06-24 Hitachi Automotive Systems, Ltd. Electronic control device
US10942747B2 (en) 2017-11-30 2021-03-09 International Business Machines Corporation Head and tail pointer manipulation in a first-in-first-out issue queue
US10564979B2 (en) 2017-11-30 2020-02-18 International Business Machines Corporation Coalescing global completion table entries in an out-of-order processor
US10922087B2 (en) 2017-11-30 2021-02-16 International Business Machines Corporation Block based allocation and deallocation of issue queue entries
US10929140B2 (en) * 2017-11-30 2021-02-23 International Business Machines Corporation Scalable dependency matrix with a single summary bit in an out-of-order processor

Citations (5)

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US5761476A (en) * 1993-12-30 1998-06-02 Intel Corporation Non-clocked early read for back-to-back scheduling of instructions
WO2000011548A1 (en) * 1998-08-24 2000-03-02 Advanced Micro Devices, Inc. Mechanism for load block on store address generation and universal dependency vector

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US5553256A (en) * 1994-02-28 1996-09-03 Intel Corporation Apparatus for pipeline streamlining where resources are immediate or certainly retired
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Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5201057A (en) * 1987-01-22 1993-04-06 Uht Augustus K System for extracting low level concurrency from serial instruction streams
WO1993020505A2 (en) * 1992-03-31 1993-10-14 Seiko Epson Corporation Superscalar risc instruction scheduling
US5761476A (en) * 1993-12-30 1998-06-02 Intel Corporation Non-clocked early read for back-to-back scheduling of instructions
US5710902A (en) * 1995-09-06 1998-01-20 Intel Corporation Instruction dependency chain indentifier
WO2000011548A1 (en) * 1998-08-24 2000-03-02 Advanced Micro Devices, Inc. Mechanism for load block on store address generation and universal dependency vector

Also Published As

Publication number Publication date
WO2002057908A2 (en) 2002-07-25
US6862676B1 (en) 2005-03-01
EP1354267A2 (en) 2003-10-22
JP2004529405A (en) 2004-09-24

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