WO2002059968A2 - Integrated circuits protected against reverse engineering using an apparent metal contact line terminating on field oxide and method - Google Patents
Integrated circuits protected against reverse engineering using an apparent metal contact line terminating on field oxide and method Download PDFInfo
- Publication number
- WO2002059968A2 WO2002059968A2 PCT/US2002/000123 US0200123W WO02059968A2 WO 2002059968 A2 WO2002059968 A2 WO 2002059968A2 US 0200123 W US0200123 W US 0200123W WO 02059968 A2 WO02059968 A2 WO 02059968A2
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- integrated circuits
- field oxide
- metal
- oxide layer
- reverse engineering
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/57—Protection from inspection, reverse engineering or tampering
- H01L23/573—Protection from inspection, reverse engineering or tampering using passive means
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Definitions
- This invention relates to the field of the prevention of reverse engineering of integrated circuits and/or mal ng such reverse engineering so difficult and time-consuming as to make reverse engineering of integrated circuits non-feasible.
- this invention relates to using, in order to prevent and/or discourage such reverse engineering, apparent metal contact lines terminating on field oxide.
- CMOS complementary metal oxide- semiconductor
- the line conducts; if another kind of implant is used for the gap-filling, the line does not conduct.
- the reverse engineer must determine connectivity on the basis of resolving the "n" or "p" implant at the minimum feature size of the channel block.
- transistor sizes and metal connection routings are modified, in order to deprive the reverse engineer of using clues which can help him find inputs, outputs, gate lines and so on as keys to the circuit functionality.
- Practicing the inventions taught in the above-mentioned patents to secure an integrated circuit causes the reverse engineer to perform steps that are not always needed. These steps include: decomposing the circuit layer by layer, careful processing of each layer (which usually must include an etching step) followed by imaging of the layer with exact registration to other layers.
- the main objective of this invention is to make a reverse engineer to examine every connection of every CMOS transistor pair in an integrated circuit. If the reverse engineer is forced to do such detailed examination, he would have to spend so much time and money as to make the attempt of reverse engineering prohibitive and leading to de facto protection against reverse engineering.
- circuit techniques are used to make the pattern of a subsequent circuit section unpredictable and non-repeatable; in other words, these techniques make it incorrect to make a usual assumption that similar metal patterns encompass similar circuit functionality.
- the gist of this invention is to guide the reverse engineer to an erroneous assumption by having some metal traces terminate on field oxide located close to a contact region. He will assume, erroneously, that the presence of the plug is to make a real contact to a source or drains when, in fact, there is none.
- the field oxide that defines and borders on the contact area is offset so that it covers a portion of the contact area. Then, the dimple and the metal plug are aligned so that the metal plug ends on the field oxide adjacent to the source of drain.
- a first aspect of the invention provides a semiconducting device adapted to prevent and/or to thwart reverse engineering, comprising field oxide layer disposed on a semiconductor substrate, a metal plug contact disposed within a contact region and above said field oxide layer, and a metal connected to said metal plug contact.
- a second aspect of the invention provides a method for preventing and/or thwarting reverse engineering, comprising steps of providing a field oxide layer disposed on a semiconductor substrate, providing a metal plug contact disposed within a contact region and above said field oxide layer, and connecting a metal to said metal plug contact.
- a third aspect of the invention provides a semiconducting device adapted to prevent and/or to thwart reverse engineering, comprising field oxide layer disposed on a semiconductor substrate, a metal plug contact disposed outside a contact region and above said field oxide layer, and a metal connected to said metal plug contact.
- a fourth aspect of the invention provides method for preventing and/or thwarting reverse engineering, comprising steps of providing a field oxide layer disposed on a semiconductor substrate, providing a metal plug contact disposed outside a contact region and above said field oxide layer and co iecting a metal to said metal plug contact.
- FIG. 1 schematically shows a prior art field effect transistor that could be part of a CMOS integrated circuit.
- FIG. 1(a) schematically shows how a contact plug is usually located relative to field oxide in (also prior art).
- FIG. 1(b) schematically shows relative locations of the metal plug and the metallization layer.
- FIG. 2 is a schematic diagram showing a preferred embodiment of this invention.
- FIG. 3 is a schematic diagram showing an alternative embodiment of this invention.
- FIG. 1 shows general architecture of some elements of a typical field effect transistor within a CMOS integrated circuit 100.
- the circuit 100 comprises a source 1, a drain 2, gate oxide 3, an insulating field oxide A, preferably, silicon oxide. It further comprises a layer of polysilicon ("poly") 5, of suicide 6, and a contact plug 7.
- the circuit 100 is disposed on a semiconducting substrate 8.
- FIG 1(a) demonstrates how a contact plug 7 is positioned relative to field oxide 4 in prior art.
- the contact plug 7 is disposed over a layer of suicide 6 and over the active area 9. In FIG. 1, such a contact could be placed over both the source 1 and the drain 2.
- FIG. 1(b) shows that the contact plug 7 is disposed orthogonally to the plane of metallization layer 10. Such relative orientation of the contact plug 7 is present both in prior art and in this invention.
- FIG. 2 shows a contact plug 7 and the contact is meant to be to the right of field oxide 4.
- Field oxide 4 is deposited over a portion of the contact region, and the metal plug 7 which would have usually been placed to end on the contact region ends up on the field oxide 4 region instead.
- the plug 7 typically has a substantially smaller area than the contact region.
- L 10 is the overlap area between the oxide region, the normal contact region and the placing of the plug 7.
- the diameter of the plug 7 is preferably not larger than the size of the minimum feature.
- L 10 can be of any size, specified by the fabrication vendor, and is preferably 10% larger than the size of the minimum feature.
- a preferred contact dimension is up to about three times the via size.
- plug 7 could also end on an oxide layer 4 deposited somewhere in the circuit where there would not be a contact.
- FIG. 3 shows such embodiment. As can be seen from FIG. 3, contact plug 7 does not extend into active area 9. Instead it ends on oxide layer 4.
Abstract
Description
Claims
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB0316906A GB2393851B (en) | 2001-01-24 | 2002-01-03 | Integrated circuits protected against reverse engineering and method for fabricating the same using an apparent metal contact line terminating on field oxide |
JP2002560197A JP4920862B2 (en) | 2001-01-24 | 2002-01-03 | Integrated circuit protected against reverse engineering using apparent metal contact wires terminated on field oxide and method for manufacturing the same |
AU2002234203A AU2002234203A1 (en) | 2001-01-24 | 2002-01-03 | Integrated circuits protected against reverse engineering using an apparent metal contact line terminating on field oxide and method |
DE10295878T DE10295878T5 (en) | 2001-01-24 | 2002-01-03 | Reverse engineering protected integrated circuits and methods of making the same using a visible metal contact line ending in field oxide |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/768,904 | 2001-01-24 | ||
US09/768,904 US7294935B2 (en) | 2001-01-24 | 2001-01-24 | Integrated circuits protected against reverse engineering and method for fabricating the same using an apparent metal contact line terminating on field oxide |
Publications (3)
Publication Number | Publication Date |
---|---|
WO2002059968A2 true WO2002059968A2 (en) | 2002-08-01 |
WO2002059968A3 WO2002059968A3 (en) | 2002-11-14 |
WO2002059968B1 WO2002059968B1 (en) | 2003-05-22 |
Family
ID=25083828
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US2002/000123 WO2002059968A2 (en) | 2001-01-24 | 2002-01-03 | Integrated circuits protected against reverse engineering using an apparent metal contact line terminating on field oxide and method |
Country Status (7)
Country | Link |
---|---|
US (1) | US7294935B2 (en) |
JP (3) | JP4920862B2 (en) |
AU (1) | AU2002234203A1 (en) |
DE (1) | DE10295878T5 (en) |
GB (1) | GB2393851B (en) |
TW (1) | TW526608B (en) |
WO (1) | WO2002059968A2 (en) |
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US11695011B2 (en) | 2018-05-02 | 2023-07-04 | Nanyang Technological University | Integrated circuit layout cell, integrated circuit layout arrangement, and methods of forming the same |
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2001
- 2001-01-24 US US09/768,904 patent/US7294935B2/en not_active Expired - Lifetime
- 2001-12-28 TW TW090133032A patent/TW526608B/en not_active IP Right Cessation
-
2002
- 2002-01-03 WO PCT/US2002/000123 patent/WO2002059968A2/en active Application Filing
- 2002-01-03 JP JP2002560197A patent/JP4920862B2/en not_active Expired - Fee Related
- 2002-01-03 DE DE10295878T patent/DE10295878T5/en not_active Withdrawn
- 2002-01-03 GB GB0316906A patent/GB2393851B/en not_active Expired - Fee Related
- 2002-01-03 AU AU2002234203A patent/AU2002234203A1/en not_active Abandoned
-
2007
- 2007-09-04 JP JP2007229291A patent/JP2008010887A/en active Pending
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2009
- 2009-12-16 JP JP2009285209A patent/JP5134615B2/en not_active Expired - Fee Related
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Also Published As
Publication number | Publication date |
---|---|
GB2393851B (en) | 2005-07-13 |
GB0316906D0 (en) | 2003-08-20 |
JP2010103550A (en) | 2010-05-06 |
JP5134615B2 (en) | 2013-01-30 |
WO2002059968A3 (en) | 2002-11-14 |
JP2008010887A (en) | 2008-01-17 |
WO2002059968B1 (en) | 2003-05-22 |
JP4920862B2 (en) | 2012-04-18 |
US7294935B2 (en) | 2007-11-13 |
JP2004518295A (en) | 2004-06-17 |
TW526608B (en) | 2003-04-01 |
GB2393851A (en) | 2004-04-07 |
US20020096776A1 (en) | 2002-07-25 |
AU2002234203A1 (en) | 2002-08-06 |
DE10295878T5 (en) | 2004-07-22 |
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