WO2002061633A2 - System, method and article of manufacture for signal constructs in a programming language capable of programming hardware architectures - Google Patents
System, method and article of manufacture for signal constructs in a programming language capable of programming hardware architectures Download PDFInfo
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- WO2002061633A2 WO2002061633A2 PCT/GB2002/000384 GB0200384W WO02061633A2 WO 2002061633 A2 WO2002061633 A2 WO 2002061633A2 GB 0200384 W GB0200384 W GB 0200384W WO 02061633 A2 WO02061633 A2 WO 02061633A2
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- G06F30/30—Circuit design
Definitions
- the present invention relates to programmable hardware architectures and more particularly to programming field programmable gate arrays (FPGA's).
- FPGA's field programmable gate arrays
- a software-controlled processor is usually slower than hardware dedicated to that function.
- a way of overcoming this problem is to use a special software-controlled processor such as a RISC processor which can be made to function more quickly for limited purposes by having its parameters (for instance size, instruction set etc.) tailored to the desired functionality.
- a system, method and article of manufacture are provided for using a dynamic object in a programming language.
- an object is defined with an associated first value and second value.
- the first value is used in association with the object during a predetermined clock cycle.
- the second value is used in association with the object before or after the predetermined clock cycle.
- the object may be used to split up an expression into sub-expressions.
- the sub-expressions may be reused.
- the first value may be assigned to and read from the object during the predetermined clock cycle.
- the programming language may be adapted for programming a gate array.
- the programming language may include Handel-C.
- Figure 1 is a schematic diagram of a hardware implementation of one embodiment ofthe present invention
- Figure 2 illustrates a design flow overview, in accordance with one embodiment of the present invention
- Figures 3A and 3B illustrate a table showing various differences between Handel-C and the conventional C programming language, in accordance with one embodiment ofthe present invention
- Figure 4 illustrates the manner in which branches that complete early are forced to wait for the slowest branch before continuing
- FIG. 5 illustrates the link between parallel branches, in accordance with one embodiment ofthe present invention
- FIG. 6 illustrates the scope of variables, in accordance with one embodiment ofthe present invention
- Figure 7 illustrates a method for using a dynamic object in a programming language.
- a preferred embodiment of a system in accordance with the present invention is preferably practiced in the context of a personal computer such as an IBM compatible personal computer, Apple Macintosh computer or UNIX based workstation.
- a representative hardware environment is depicted in Figure 1, which illustrates a typical hardware configuration of a workstation in accordance with a preferred embodiment having a central processing unit 110, such as a microprocessor, and a number of other units interconnected via a system bus 112.
- the workstation shown in Figure 1 includes a Random Access Memory (RAM) 114, Read Only Memory (ROM) 116, an I/O adapter 118 for connecting peripheral devices such as disk storage units 120 to the bus 112, a user interface adapter 122 for connecting a keyboard 124, a mouse 126, a speaker 128, a microphone 132, and/or other user interface devices such as a touch screen (not shown) to the bus 112, communication adapter 134 for connecting the workstation to a communication network (e.g., a data processing network) and a display adapter 136 for connecting the bus 112 to a display device 138.
- a communication network e.g., a data processing network
- display adapter 136 for connecting the bus 112 to a display device 138.
- the workstation typically has resident thereon an operating system such as the Microsoft Windows NT or Windows/95 Operating System (OS), the IBM OS/2 operating system, the MAC OS, or UNIX operating system.
- OS Microsoft Windows NT or Windows/95 Operating System
- IBM OS/2 operating system the IBM OS/2 operating system
- MAC OS the MAC OS
- UNIX operating system the operating system
- the hardware environment of Figure 1 may include, at least in part, a field programmable gate array (FPGA) device.
- FPGA field programmable gate array
- the central processing unit 110 may be replaced or supplemented with an FPGA.
- FPGA devices include the XC2000TM and XC3000TM families of FPGA devices introduced by Xilinx, Inc. of San Jose, Calif. The architectures of these devices are exemplified in U.S. Pat. Nos. 4,642,487; 4,706,216; 4,713,557; and 4,758,985; each of which is originally assigned to Xilinx, Inc. and which are herein incorporated by reference for all purposes. It should be noted, however, that FPGA's of any type may be employed in the context ofthe present invention.
- Handel-C is a programming language marketed by Celoxica Limited. Handel-C is a programming language that enables a software or hardware engineer to target directly FPGAs (Field Programmable Gate Arrays) in a similar fashion to classical microprocessor cross- compiler development tools, without recourse to a Hardware Description Language. This allows the designer to directly realize the raw real-time computing capability of the FPGA.
- FPGAs Field Programmable Gate Arrays
- Handel-C allows one to use a high-level language to program FPGAs. It makes it as easy to implement complex algorithms by using a software-based language rather than a hardware architecture-based language. One can use all the power of reconfigurable computing in FPGAs without needing to know the details of the FPGAs themselves.
- a program may be written in Handel-C to generate all required state machines, while one can specify storage requirements down to the bit level.
- a clock and clock speed may be assigned for working with the simple but explicit model of one clock cycle per assignment.
- a Handel-C macro library may be used for bit manipulation and arithmetic operations.
- the program may be compiled and then simulated and debugged on a PC similar to that in Figure 1. This may be done while stepping through single or multiple clock cycles. When one has designed their chip, the code can be compiled directly to a netlist, ready to be used by manufacturers' place and route tools for a variety of different chips.
- Handel-C optimizes code, and uses efficient algorithms to generate the logic hardware from the program. Because of the speed of development and the ease of maintaining well-commented high-level code, it allows one to use reconfigurable computing easily and efficiently.
- Handel-C has the tight relationship between code and hardware generation required by hardware engineers, with the advantages of high-level language abstraction. Further features include:
- Handel-C is thus designed to enable the compilation of programs into synchronous hardware; it is aimed at compiling high level algorithms directly into gate level hardware.
- the Handel-C syntax is based on that of conventional C so programmers familiar with conventional C will recognize almost all the constructs in the Handel- C language. Sequential programs can be written in Handel-C just as in conventional C but to gain the most benefit in performance from the target hardware its inherent parallelism must be exploited. Handel-C includes parallel constructs that provide the means for the programmer to exploit this benefit in his applications.
- the compiler compiles and optimizes Handel-C source code into a file suitable for simulation or a net list which can be placed and routed on a real FPGA.
- Handel-C is a programming language designed to enable the compilation of programs into synchronous hardware.
- the Handel-C compiler and simulator will now be described.
- the Handel-C language will be described hereinafter in greater detail.
- Figure 2 illustrates a design flow overview 200, in accordance with one embodiment of the present invention.
- the dotted lines 202 show the extra steps 204 required if one wishes to integrate Handel-C with VHDL.
- Handel-C is halfway between RTL and a behavioral HDL. It is a high-level language that requires one to think in algorithms rather than circuits.
- Handel-C uses a zero-delay model and a synchronous design style.
- Handel-C is implicitly sequential. Parallel processes must be specified. • All code in Handel-C (apart from the simulator chanin and chanout commands) can be synthesized, so one must ensure that he or she disables debug code when he or she compiles to target real hardware.
- Handel-C Signals in Handel-C are different from signals in VHDL; they are assigned to immediately, and only hold their value for one clock cycle.
- Handel-C has abstract high-level concepts such as pointers.
- Figures 3 A and 3B illustrate a table showing various differences 3100 between Handel-C and the conventional C programming language, in accordance with one embodiment ofthe present invention.
- Handel-C uses the syntax of conventional C with the addition of inherent parallelism.
- One can write sequential programs in Handel-C but to gain maximum benefit in performance from the target hardware one must use its parallel constructs. These may be new to some users.
- Handel-C is designed to allow one to express the algorithm without worrying about how the underlying computation engine works. This philosophy makes Handel-C a programming language rather than a hardware description language. In some senses, Handel-C is to hardware what a conventional high-level language is to microprocessor assembly language.
- Handel-C produces is generated directly from the source program. There is no intermediate 'inte ⁇ reting' layer as exists in assembly language when targeting general pu ⁇ ose microprocessors.
- the logic gates that make up the final Handel-C circuit are the assembly instructions of the Handel-C system.
- Handel-C is based on the syntax of conventional C, programs written in Handel-C are implicitly sequential. Writing one command after another indicates that those instructions should be executed in that exact order.
- Handel-C provides constructs to control the flow of a program. For example, code can be executed conditionally depending on the value of some expression, or a block of code can be repeated a number of times using a loop construct.
- Handel-C parallelism is true parallelism - it is not the time-sliced parallelism familiar from general pu ⁇ ose computers.
- FIG. 4 illustrates the manner 4900 in which branches that complete early are forced to wait for the slowest branch before continuing.
- Figure 4 illustrates the branching and re-joining ofthe execution flow.
- the left hand branch 4902 and middle branch 4904 must wait to ensure that all branches have completed before the instruction following the parallel construct can be executed.
- FIG. 5 illustrates the link 5000 between parallel branches, in accordance with one embodiment of the present invention.
- Channels 5001 provide a link between parallel branches.
- One parallel branch 5002 outputs data onto the channel and the other branch 5004 reads data from the channel.
- Channels also provide synchronization between parallel branches because the data transfer can only complete when both parties are ready for it. If the transmitter is not ready for the communication then the receiver must wait for it to become ready and vice versa.
- the channel is shown transferring data from the left branch to the right branch. If the left branch reaches point a before the right branch reaches point b, the left branch waits at point a until the right branch reaches point b.
- Figure 6 illustrates the scope 6100 of variables, in accordance with one embodiment of the present invention.
- the scope of declarations is, as in conventional C, based around code blocks.
- a code block is denoted with ⁇ ... ⁇ brackets. This means that:
- a Handel-C program consists of a series of statements which execute sequentially. These statements are contained within a mainO function that tells the compiler where the program begins. The body of the main function may be split into a number of blocks using ⁇ ... ⁇ brackets to break the program into readable chunks and restrict the scope of variables and identifiers.
- Handel-C also has functions, variables and expressions similar to conventional C. There are restrictions where operations are not appropriate to hardware implementation and extensions where hardware implementation allows additional functionality.
- Handel-C programs can also have statements or functions that execute in parallel. This feature is crucial when targeting hardware because parallelism is the main way to increase performance by using hardware.
- Parallel processes can communicate using channels.
- a channel is a one-way point-to-point link between two processes.
- the overall program structure consists of one or more main functions, each associated with a clock. One would only use more than one main function if he or she needed parts of the program to run at different speeds (and so use different clocks).
- a main function is defined as follows:
- the main(3 function takes no arguments and returns no value. This is in line with a hardware implementation where there are no command line arguments and no environment to return values to.
- the argc, argv and envp parameters and the return value familiar from conventional C can be replaced with explicit communications with an external system (e.g. a host microprocessor) within the body ofthe program.
- the Handel-C source code is passed through a C preprocessor before compilation. Therefore, the usual #include and #def ⁇ ne constructs may be used to perform textual manipulation on the source code before compilation.
- Handel-C also supports macros that are more powerful than those handled by the preprocessor.
- Handel-C uses the standard /* ... */ delimiters for comments. These comments may not be nested. For example:
- Handel-C also provides the C++ style // comment marker which tells the compiler to ignore everything up to the next newline. For example:
- Types Handel-C uses two kinds of objects: logic types and architecture types.
- the logic types specify variables.
- the architecture types specify variables that require a particular sort of hardware architecture (e.g., ROMs, RAMs and channels). Both kinds are specified by their scope (static or extern), their size and their type.
- Architectural types are also specified by the logic type that uses them.
- Both types can be used in derived types (such as structures, arrays or functions) but there may be some restrictions on the use of architectural types.
- the type specifiers signed, unsigned and undefined define whether the variable is signed and whether it takes a default defined width.
- Functions can have the storage class inline to show that they are expanded in line, rather than being shared.
- Handel-C supports the type qualifiers const and volatile to increase compatibility with ISO-C. These can be used to further qualify logic types.
- Handel-C supports the extension o. This can be used to clarify complex declarations of architectural types.
- the basic logic type is an int. It may be qualified as signed or unsigned. Integers can be manually assigned a width by the programmer or the compiler may attempt to infer a width from use.
- Enumeration types allow one to define a specified set of values that a variable of this type may hold.
- There are derived types (types that are derived from the basic types). These are arrays, pointers, structs bit fields, and functions.
- the non-type void enables one to declare empty parameter lists or functions that do not return a value.
- the typeof type operator allows one to reference the type of a variable.
- the architectural types are channels (used to communicate between parallel processes), interfaces (used to connect to pins or provide signals to communicate with external code), memories (rom , ram , worn and mpram) and signal (declares a wire).
- the disambiguator ⁇ > has been provided to help clarify the definitions of memories, channels and signals.
- Handel-C provides channels for communicating between parallel branches of code. One branch writes to a channel and a second branch reads from it. The communication only occurs when both tasks are ready for the transfer at which point one item of data is transferred between the two branches.
- Channels are declared with the chan keyword. For example:
- the Handel-C compiler can infer the width of a channel from its usage if it is declared with the undefined keyword. Channels can also be declared with no explicit type. The compiler infers the type and width of the channel from its usage.
- Arrays of channels Handel-C allows arrays of channels to be declared. For example:
- An interface consists of data ports, together with information about each port.
- a port definition consists of the data type that uses it (either defined or inferred from its first use), an optional name and the specification for that port (e.g., input pins for a bus) if needed.
- RAMs and ROMs may be built from the logic provided in the FPGA using the ram and rom keywords. For example:
- Figure 7 illustrates a method 7040 for using a dynamic object, i.e. signal, in a programming language.
- an object is defined with an associated first value and second value.
- the first value is then used in association with the object during a predetermined clock cycle. See operation 7044.
- the second value is used in association with the object before or after the predetermined clock cycle, as indicated in operation 7046.
- the object may be used to split up an expression into sub-expressions.
- the sub-expressions may be reused.
- the first value may be assigned to and read from the object during the predetermined clock cycle.
- the programming language may be adapted for programming a gate array.
- the programming language may include Handel-C.
- a signal is an object that takes on the value assigned to it but only for that clock cycle. The value assigned to it can be read back during the same clock cycle. At all other times it takes on its initialisation value. The default initialisation value is 0.
- the optional disambiguator o can be used to clarify complex signal definitions. Syntax
- sig is assigned to and read from in the same clock cycle, so b is assigned the value of a. Since the signal only holds the value assigned to it for a single clock cycle, if it is read from just before or just after it is assigned to, one gets its initial value. For example:
- b is assigned the value of a through the signal, as before. Since there is a clock tick before the last line, a is finally assigned the signal's initial value of 690.
- Breaking up expressions also enables one to re-use sub-expressions:
- Type qualifiers Handel-C supports the type-qualifiers const and volatile to increase compatibility with ISO-C. These can be used to further qualify logic types.
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US09/772,616 US6691301B2 (en) | 2001-01-29 | 2001-01-29 | System, method and article of manufacture for signal constructs in a programming language capable of programming hardware architectures |
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Also Published As
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---|---|
US6691301B2 (en) | 2004-02-10 |
WO2002061633A3 (en) | 2003-12-11 |
US20030046671A1 (en) | 2003-03-06 |
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