WO2002067325A3 - High-density flip-chip interconnect - Google Patents

High-density flip-chip interconnect Download PDF

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Publication number
WO2002067325A3
WO2002067325A3 PCT/US2002/002836 US0202836W WO02067325A3 WO 2002067325 A3 WO2002067325 A3 WO 2002067325A3 US 0202836 W US0202836 W US 0202836W WO 02067325 A3 WO02067325 A3 WO 02067325A3
Authority
WO
WIPO (PCT)
Prior art keywords
layer
viad
signals
chip
chip interconnect
Prior art date
Application number
PCT/US2002/002836
Other languages
French (fr)
Other versions
WO2002067325A2 (en
Inventor
Mark P Jamieson
Original Assignee
Intel Corp
Mark P Jamieson
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp, Mark P Jamieson filed Critical Intel Corp
Priority to KR1020037010895A priority Critical patent/KR100732123B1/en
Priority to EP02703307A priority patent/EP1364403A2/en
Priority to AU2002236936A priority patent/AU2002236936A1/en
Priority to JP2002566550A priority patent/JP4156927B2/en
Publication of WO2002067325A2 publication Critical patent/WO2002067325A2/en
Publication of WO2002067325A3 publication Critical patent/WO2002067325A3/en

Links

Classifications

    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
    • H05K1/0218—Reduction of cross-talk, noise or electromagnetic interference by printed shielding conductors, ground planes or power plane
    • H05K1/0219—Printed shielding conductors for shielding around or between signal conductors, e.g. coplanar or coaxial printed shielding conductors
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09218—Conductive traces
    • H05K2201/09227—Layout details of a plurality of traces, e.g. escape layout for Ball Grid Array [BGA] mounting
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10674—Flip chip
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10734—Ball grid array [BGA]; Bump grid array

Abstract

An interconnect routing for a card or interposer or the like, including splines of traces on a first layer (66, 69, 70) and traces on a second layer (58, 60), with vias connecting between the layers. Outer rows of signals (40, 42, 44) are routed out from a chip on the first layer, while inner rows of signals (48, 50) are viad down to the second layer where they are routed out, then viad back up to the first layer. These outer vias are arranged in an arc, enabling the second layer trace segments to be of a more uniform length. The second layer may also include ground or power plane fingers extending between the splines and viad up to ground or power signals of the chip.
PCT/US2002/002836 2001-02-20 2002-02-01 High-density flip-chip interconnect WO2002067325A2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
KR1020037010895A KR100732123B1 (en) 2001-02-20 2002-02-01 High-density flip-chip interconnect
EP02703307A EP1364403A2 (en) 2001-02-20 2002-02-01 High-density flip-chip interconnect
AU2002236936A AU2002236936A1 (en) 2001-02-20 2002-02-01 High-density flip-chip interconnect
JP2002566550A JP4156927B2 (en) 2001-02-20 2002-02-01 Multi-layer board device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/789,401 US8125087B2 (en) 2001-02-20 2001-02-20 High-density flip-chip interconnect
US09/789,401 2001-02-20

Publications (2)

Publication Number Publication Date
WO2002067325A2 WO2002067325A2 (en) 2002-08-29
WO2002067325A3 true WO2002067325A3 (en) 2003-05-30

Family

ID=25147535

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2002/002836 WO2002067325A2 (en) 2001-02-20 2002-02-01 High-density flip-chip interconnect

Country Status (7)

Country Link
US (1) US8125087B2 (en)
EP (1) EP1364403A2 (en)
JP (1) JP4156927B2 (en)
KR (1) KR100732123B1 (en)
CN (1) CN1331222C (en)
AU (1) AU2002236936A1 (en)
WO (1) WO2002067325A2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100615606B1 (en) * 2005-03-15 2006-08-25 삼성전자주식회사 Memory module and signal line arrangement method of the same
JP2009175198A (en) 2008-01-21 2009-08-06 Sony Corp El display panel and electronic apparatus

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5424492A (en) * 1994-01-06 1995-06-13 Dell Usa, L.P. Optimal PCB routing methodology for high I/O density interconnect devices
US5812379A (en) * 1996-08-13 1998-09-22 Intel Corporation Small diameter ball grid array pad size for improved motherboard routing
US5986893A (en) * 1996-07-18 1999-11-16 Compaq Computer Corporation Apparatus for controlling the impedance of high speed signals on a printed circuit board
US6011695A (en) * 1998-11-02 2000-01-04 Intel Corporation External bus interface printed circuit board routing for a ball grid array integrated circuit package
US6121554A (en) * 1997-04-30 2000-09-19 Kabushiki Kaisha Toshiba Printed wiring board
EP1098555A2 (en) * 1999-11-02 2001-05-09 Canon Kabushiki Kaisha Printed-wiring board

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0563029A (en) * 1991-09-02 1993-03-12 Fujitsu Ltd Semiconductor device
JPH05129366A (en) * 1991-11-08 1993-05-25 Fujitsu Ltd Tab mounting structure for integrated circuit use
US5545923A (en) * 1993-10-22 1996-08-13 Lsi Logic Corporation Semiconductor device assembly with minimized bond finger connections
US5906042A (en) * 1995-10-04 1999-05-25 Prolinx Labs Corporation Method and structure to interconnect traces of two conductive layers in a printed circuit board
JP3386977B2 (en) * 1997-06-05 2003-03-17 新光電気工業株式会社 Multilayer circuit board
JP3152180B2 (en) * 1997-10-03 2001-04-03 日本電気株式会社 Semiconductor device and manufacturing method thereof
US6310398B1 (en) * 1998-12-03 2001-10-30 Walter M. Katz Routable high-density interfaces for integrated circuit devices

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5424492A (en) * 1994-01-06 1995-06-13 Dell Usa, L.P. Optimal PCB routing methodology for high I/O density interconnect devices
US5986893A (en) * 1996-07-18 1999-11-16 Compaq Computer Corporation Apparatus for controlling the impedance of high speed signals on a printed circuit board
US5812379A (en) * 1996-08-13 1998-09-22 Intel Corporation Small diameter ball grid array pad size for improved motherboard routing
US6121554A (en) * 1997-04-30 2000-09-19 Kabushiki Kaisha Toshiba Printed wiring board
US6011695A (en) * 1998-11-02 2000-01-04 Intel Corporation External bus interface printed circuit board routing for a ball grid array integrated circuit package
EP1098555A2 (en) * 1999-11-02 2001-05-09 Canon Kabushiki Kaisha Printed-wiring board

Also Published As

Publication number Publication date
EP1364403A2 (en) 2003-11-26
WO2002067325A2 (en) 2002-08-29
KR20040014460A (en) 2004-02-14
JP2005505910A (en) 2005-02-24
US20020113307A1 (en) 2002-08-22
US8125087B2 (en) 2012-02-28
CN1331222C (en) 2007-08-08
CN1568544A (en) 2005-01-19
JP4156927B2 (en) 2008-09-24
KR100732123B1 (en) 2007-06-25
AU2002236936A1 (en) 2002-09-04

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