WO2002071228A1 - A method for using ram buffers with multiple accesses in flash-based storage systems - Google Patents

A method for using ram buffers with multiple accesses in flash-based storage systems Download PDF

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Publication number
WO2002071228A1
WO2002071228A1 PCT/US2002/006454 US0206454W WO02071228A1 WO 2002071228 A1 WO2002071228 A1 WO 2002071228A1 US 0206454 W US0206454 W US 0206454W WO 02071228 A1 WO02071228 A1 WO 02071228A1
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Prior art keywords
memory
data
flash
host
buffer
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Application number
PCT/US2002/006454
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French (fr)
Inventor
Eugene Zilberman
Original Assignee
M-Systems Flash Disk Pioneers Ltd.
Friedman, Mark, M.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by M-Systems Flash Disk Pioneers Ltd., Friedman, Mark, M. filed Critical M-Systems Flash Disk Pioneers Ltd.
Priority to JP2002570084A priority Critical patent/JP2004523049A/en
Publication of WO2002071228A1 publication Critical patent/WO2002071228A1/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1673—Details of memory controller using buffers

Definitions

  • the present invention relates to a method for using RAM buffers with multiple accesses in flash-based storage systems.
  • RAM buffers enable improved read and write performance of flash-based storage systems, achieved by overlapping read and write operations to the RAM.
  • flash memory as a storage media commonly has the 2 following features:
  • EDC/ECC error detection codes and/or error correction codes
  • a write operation to the flash can also fail. However, this failure can be hidden from the host interface (such as SCSI or ATA) by writing data onto another location. In order to repeat the write operation, data arriving from the host interface should be placed into the RAM buffer prior to commencing the write operation.
  • These 2 features inhibit direct data transfer between the host interface and the flash media.
  • Using memory buffer as an intermediary normally takes two consecutive transfer operations: one to the memory and one from the memory. The necessity for these two consecutive data transfers is usually accepted as a necessary evil, and is therefore operative in most flash based storage systems.
  • the present invention describes a method of performing these two transfer operations simultaneously in a flash-based storage system, thus improving the read and write performances of the system.
  • the system of the present invention is differentiated from known alternative technologies and solutions due to the following factors: i) The synchronization of host-to-memory and memory-to-fiash transfers, and the correct recovery from different flash-related failure operations are complicated to implement, as described in present invention. ii) Using a RAM buffer as an intermediary for the read and write operations is common, whereas the specific described method of performing these transfer operations simultaneously with a plurality of RAM buffers is unique in flash- based systems, and is thus innovative. iii) The present invention enables the increase of sustained read and write performance practically twofold.
  • Figure 1 is an example of a system which receives new data from the host interface to one memory buffer and simultaneously writes the preceding portion of the new data from another memory buffer into flash memory.
  • Figure 2 is an example of a system which sends data to the host interface from one memory buffer and simultaneously receives the next portion of the data (to be sent) from the flash to another memory buffer.
  • Figure 3 is an example of a system which sends data to the disk interface from one memory module and simultaneously receives the next portion of the data (to be sent) from the flash to another memory module.
  • This system is similar to the system in Figures 1, with the distinction that memory modules are located inside the flash memory controller.
  • Figure 4 is an example of system which receives new data from the disk interface to one memory module and simultaneously writes the preceding portion of the new data from another memory module into flash memory. This system is similar to the system in
  • Figure 5 is similar to figure 1, except that the system illustrated has more than two memory buffers.
  • Figure 6 is similar to figure 2, except that the system illustrated has more than two memory buffers.
  • the present invention relates to a method and system for substantially improving read and write performance of flash-based storage systems, using a plurality of RAM buffers with multiple accesses.
  • the increase of read and write performance of flash-based storage system is achieved by performing "from RAM” and "to RAM” transfer operations simultaneously.
  • the invention provides a system for enabling simultaneous data transfer between host interface and intermediate RAM Buffer and between the intermediate RAM Buffer and the flash media, comprising:
  • a processing system for enabling interaction with a host system; 2. At least one flash memory device for data storage;
  • a system for synchronizing host-to-memory and memory-to-flash transfers during the host write operation.
  • a method for synchronizing memory-to-host and flash-to-memory transfers in a solid state storage system during the host read operation.
  • the present invention relates to a method and system for improving performance of flash-based storage system, by using a plurality of RAM buffers with multiple accesses. More specifically, the present invention relates to a system that performs "from
  • Figures 1 and 2 show the operation of such a system, according to the present invention.
  • Figure 1 is an example of a system which receives new data from the host interface 10 to one memory buffer 12 and simultaneously writes the preceding portion of the new data from another memory buffer 14 into the flash memory 16.
  • Figure 2 is an example of a system which sends data to the host interface 20 from one memory buffer 22 and simultaneously receives the next portion of the data (to be sent) from the flash 26 to another memory buffer 24.
  • the intermediate memory consists of either 2 or more (A, B, C.) logically independent memory buffers.
  • A, B, C. logically independent memory buffers.
  • these buffers can be either memory components with multiplexed buses, or dual-port-RAM components.
  • the memory components may be either separate chips, or parts of a larger integrated component.
  • memory buffers are designated non-overlapping regions of memory inside the dual-port- RAM.
  • the data of a system's logical block N is written ( Figure 1) onto the flash media from memory buffer A
  • the data of logical block N+l is being simultaneously received from the host interface to the memory buffer B.
  • the "logical block” stands for one or more host system transfer units (sectors).
  • the size of the "logical block” is determined by the convenience and performance of the flash operations. For example in the case of AND or NAND- technology flash, it could be set to the page size of the used flash array.
  • the stream of data transferred from the host is viewed by the storage system as a sequence of logical blocks N, N+l, N+2, etc.
  • memory buffer A can be considered empty and, two new simultaneous transfers can be initiated: block N+l from the memory buffer B to the flash media and block N+2 from the host interface to the memory buffer A.
  • new transfers into the memory can be started without waiting for completion of the flash write or retry operations.
  • the new data will be received to the available empty memory buffers, C 56, D 58, and so on, as can be seen in figure 5. If all the empty memory buffers have been used, the waiting for completion of the flash write or retry operations shall be performed, in order to empty another memory buffer, for reception of further new data.
  • the data which has not yet been written successfully to the flash media (i.e. which write status has not yet been received) should not be replaced, as it may be needed to retry the failed write operation.
  • the system should either record which part of the data has not been transferred from the host during the write procedure, or read this part from the flash media, possibly into the memory buffer prior to the transfer.
  • Figure 3 is an example of a system which sends data to the host interface 30 from one memory module 32 and simultaneously receives the next portion of the data (to be sent) from the flash 36 to another memory module 34.
  • This system is similar to the system in
  • Figure 1 with the distinction that memory modules are located inside the flash memory controller 38.
  • Figure 4 is an example of system which receives new data from the host interface 40 to one memory module 42 and simultaneously writes the preceding portion of the new data from another memory module 44 into flash memory 46. This system is similar to the system in Figure 2, with the distinction that memory modules are located inside the flash memory controller 48.
  • the preferred embodiment of the present invention incorporates a system for synchronizing memory-to-host and flash-to-memory transfers, during the host read operation.
  • This system comprises: i. Memory register or variable (the term “memory register” in this context may include use of the term “variable”) for each memory buffer, which indicates the status of the buffer, where the status can be 'empty', 'in process of data reception', 'contains data of the logical block N' and, 'contains corrupted data of the logical block N'. ii.
  • Memory-to-host control thread which, for each logical block N of data, part of which is to be transferred to the host, awaits for some memory buffer to acquire status of 'contains the data of the logical block N', and then initiates the data transfer of the user data to the host, upon the completion of the transfer, marks that memory buffer as 'empty'.
  • 'Control Thread' here and elsewhere, relates to the software or hardware control flow related to a particular task.
  • Flash-to-memory control thread which for each logical block N of data, part of which is to be transferred to the host, awaits for some memory buffer to acquire status of 'empty', optionally marks that memory buffer as 'in process of data reception', then issues read command to the flash memory device which contains the data.
  • the control thread initiates the data transfer of the user data from the flash to the memory buffer.
  • the thread examines the data correctness status calculated by the ECC/EDC mechanism (software or circuitry). If the data is corrupted but can be corrected, a correction algorithm can be employed.
  • the thread marks that memory buffer as 'contains data of the logical block N', otherwise it marks that memory buffer as 'contains corrupted data of the logical block N'.
  • the flash-to-memory control thread operates independently from the memory-to-host control thread, either truly simultaneously or with preemption of control.
  • the synchronization between the control threads is perfomed using the registers or variables of the RAM Buffer status.
  • the process of changing this memory register or variable by a thread should be atomic, in the sense that other threads will only see the whole result of the change, and can not see the partially changed status.
  • the preferred embodiment of the present invention further incorporates a system for synchronizing host-to-memory and memory-to-flash transfers, during the host write operation.
  • This system comprises: i. Memory register or variable for each memory buffer which indicates the status of the buffer, where status can be 'empty', 'in process of data reception' or 'contains data of the logical block N'. ii. Host-to-memory control thread which for each logical block N of data, part of which is to be transferred from the host, awaits for some memory buffer to acquire status of 'empty', optionally marks that memory buffer as 'in process of data reception', and then initiates the data transfer of the user data from the host, upon the completion of the transfer marks that memory buffer as
  • This memory-to-Flash control thread operates independently from the host- to-memory control thread, either truly simultaneously or with preemption of control.
  • the synchronization between the control threads is performed by the registers or variables of the RAM Buffer status.
  • the process of changing this memory register or variable by a thread should be atomic in the sense that other thread will only see the whole result of the change, and can not see the partially changed status.
  • the configuration for such a system includes the memory module inside each flash memory controller, as shown on Figures 3 and 4.
  • Figure 3 is an example of system which sends data to the disk interface from one memory module and simultaneously receives the next portion of the data (to be sent) from the flash to another memory module.
  • the system is similar to the system in Figure 1, with the distinction that memory modules are located inside the flash memory controller.
  • Figure 4 is an example of a system which receives new data from the disk interface to one memory module and simultaneously writes the preceding portion of the new data from another memory module into the flash memory.
  • This system is similar to the system in Figure 2, with the distinction that memory modules are located inside the flash memory controller. This can considerably simplify the design of the system. Of course, a combination of all mentioned configurations can also be implemented.
  • these memory buffers may also serve as part of a data cache system. For example, after the data has been transferred to the host during a Read operation or has been received from host during Write operation, and if the host during subsequent Read operation requests the same data, the same data left in the buffer may be transferred to the host without accessing the flash memory. Alternatively, after the data has been received from host during Write operation, it may be left in the buffer for some time without writing it onto the flash media. This is referred to as being transferred directly to/from the host.

Abstract

A method and system for increasing read and write performance of flash-based storage systems, by using RAM buffers with multiple accesses. The increase of read and write performance of flash-based storage system is achieved by performing 'from RAM' and 'to RAM' transfer operations simultaneously. According to the preferred embodiment of the present invention, the invention provides a system for enabling simultaneous data transfer from a host interface to flash media and from flash media to a host interface. It also provides for a system for synchronizing memory-to-host and flash-to memory transfers, during the host read operation. There is further provided a system of synchronizing host-to-memory and memory-to-flash transfers, during the host write operation.

Description

A METHOD FOR USING RAM BUFFERS WITH MULTIPLE
ACCESSES IN FLASH-BASED STORAGE SYSTEMS
Background of Invention
Introduction and field:
The present invention relates to a method for using RAM buffers with multiple accesses in flash-based storage systems. Such RAM buffers enable improved read and write performance of flash-based storage systems, achieved by overlapping read and write operations to the RAM.
Prior Art:
Using flash memory as a storage media commonly has the 2 following features:
1. Data written to flash generally should be protected by error detection codes and/or error correction codes (EDC/ECC). When the data is read from the flash, EDC/ECC allow the system to determine whether an error is present, and optionally to correct it. The correction can take place in any part of the EDC/ECC-protected data, and therefore should be done in random-access memory. Hence data cannot be sent directly to the host interface (such as SCSI or ATA bus), and should first be read into the RAM. Following this process the EDC/ECC status should be examined. In the case where the EDC/ECC status indicates no error, the data can be passed along. If the EDC/ECC mechanism indicates a correctable error, a corrective action should be taken before passing data further. If the EDC/ECC mechanism indicates an uncorrectable error, this error can optionally be passed to the host interface.
2. A write operation to the flash can also fail. However, this failure can be hidden from the host interface (such as SCSI or ATA) by writing data onto another location. In order to repeat the write operation, data arriving from the host interface should be placed into the RAM buffer prior to commencing the write operation. These 2 features inhibit direct data transfer between the host interface and the flash media. Using memory buffer as an intermediary normally takes two consecutive transfer operations: one to the memory and one from the memory. The necessity for these two consecutive data transfers is usually accepted as a necessary evil, and is therefore operative in most flash based storage systems.
There is thus a widely recognized need for, and it would be highly advantageous to have, a system that can enable both operations to and from the memory buffer simultaneously.
The present invention describes a method of performing these two transfer operations simultaneously in a flash-based storage system, thus improving the read and write performances of the system. The system of the present invention is differentiated from known alternative technologies and solutions due to the following factors: i) The synchronization of host-to-memory and memory-to-fiash transfers, and the correct recovery from different flash-related failure operations are complicated to implement, as described in present invention. ii) Using a RAM buffer as an intermediary for the read and write operations is common, whereas the specific described method of performing these transfer operations simultaneously with a plurality of RAM buffers is unique in flash- based systems, and is thus innovative. iii) The present invention enables the increase of sustained read and write performance practically twofold.
Brief description of the drawings
The invention is herein described, by way of example only, with reference to the accompanying drawings, wherein:
Figure 1 is an example of a system which receives new data from the host interface to one memory buffer and simultaneously writes the preceding portion of the new data from another memory buffer into flash memory. Figure 2 is an example of a system which sends data to the host interface from one memory buffer and simultaneously receives the next portion of the data (to be sent) from the flash to another memory buffer.
Figure 3 is an example of a system which sends data to the disk interface from one memory module and simultaneously receives the next portion of the data (to be sent) from the flash to another memory module. This system is similar to the system in Figures 1, with the distinction that memory modules are located inside the flash memory controller.
Figure 4 is an example of system which receives new data from the disk interface to one memory module and simultaneously writes the preceding portion of the new data from another memory module into flash memory. This system is similar to the system in
Figure 2, with the distinction that memory modules are located inside the flash memory controller.
Figure 5 is similar to figure 1, except that the system illustrated has more than two memory buffers.
Figure 6 is similar to figure 2, except that the system illustrated has more than two memory buffers.
SUMMARY OF THE PRESENT INVENTION
The present invention relates to a method and system for substantially improving read and write performance of flash-based storage systems, using a plurality of RAM buffers with multiple accesses. The increase of read and write performance of flash-based storage system is achieved by performing "from RAM" and "to RAM" transfer operations simultaneously.
According to a preferred embodiment of the present invention, the invention provides a system for enabling simultaneous data transfer between host interface and intermediate RAM Buffer and between the intermediate RAM Buffer and the flash media, comprising:
1. A processing system for enabling interaction with a host system; 2. At least one flash memory device for data storage;
3. Optional means for performing Error detection by calculating syndromes or checksum or CRC (Cyclical Redundancy Checking) of the data written into flash memory and data read from flash. 4. Optional means for performing Error correction of the data read from flash memory; and 5. At least two RAM components with separate data buses allowing simultaneous read and write operations on each RAM component
According to further features of the present invention, there is provided a system for synchronizing memory-to-host and flash-to-memory transfers, during the host read operation.
In addition there is provided a system for synchronizing host-to-memory and memory-to-flash transfers, during the host write operation. According to further features of the present invention, there is provided a method for synchronizing memory-to-host and flash-to-memory transfers in a solid state storage system, during the host read operation.
In addition there is provided a method for synchronizing host-to-memory and memory-to-flash transfers in a solid state storage system, during the host write operation.
It should be understood by someone who is skilled in the art of solid state storage system development, that the inventive methods and systems described herein may be used to develop further embodiments. The above mentioned embodiments are to be seen as examples, and are in no way meant to limit the technology described herein to these examples alone.
DETAILED DESCRIPTION OF THE PRESENT INVENTION
The present invention relates to a method and system for improving performance of flash-based storage system, by using a plurality of RAM buffers with multiple accesses. More specifically, the present invention relates to a system that performs "from
RAM" and "to RAM" transfer operations simultaneously.
The principles and operation of the system and a method according to the present invention may be better understood with reference to the drawings and the accompanying descriptions, it being understood that these drawings are given for illustrative purposes only and are not meant to be limiting, wherein:
Figures 1 and 2 show the operation of such a system, according to the present invention. Figure 1 is an example of a system which receives new data from the host interface 10 to one memory buffer 12 and simultaneously writes the preceding portion of the new data from another memory buffer 14 into the flash memory 16. Figure 2 is an example of a system which sends data to the host interface 20 from one memory buffer 22 and simultaneously receives the next portion of the data (to be sent) from the flash 26 to another memory buffer 24.
In reference to figures 1 and 2, the intermediate memory consists of either 2 or more (A, B, C.) logically independent memory buffers. By logical independence, it is intended that one buffer can be written into, while simultaneously, the other buffer can be read from. Physically, these buffers can be either memory components with multiplexed buses, or dual-port-RAM components. The memory components may be either separate chips, or parts of a larger integrated component. In the case of dual-port-RAM implementation, memory buffers are designated non-overlapping regions of memory inside the dual-port- RAM.
In the case where the data of a system's logical block N is written (Figure 1) onto the flash media from memory buffer A, the data of logical block N+l is being simultaneously received from the host interface to the memory buffer B. Here and in the following descriptions, the "logical block" stands for one or more host system transfer units (sectors). The size of the "logical block" is determined by the convenience and performance of the flash operations. For example in the case of AND or NAND- technology flash, it could be set to the page size of the used flash array. The stream of data transferred from the host is viewed by the storage system as a sequence of logical blocks N, N+l, N+2, etc.
If there are only 2 logically independent memory buffers, upon completion of the data transfer into B, software should wait for the completion of the flash write operation from A and inspect the flash write status. If the write operation has failed, it can be retried at another place of the flash media. When the write operation is successful, memory buffer A can be considered empty and, two new simultaneous transfers can be initiated: block N+l from the memory buffer B to the flash media and block N+2 from the host interface to the memory buffer A.
If there are more than 2 logically independent memory buffers, new transfers into the memory can be started without waiting for completion of the flash write or retry operations. The new data will be received to the available empty memory buffers, C 56, D 58, and so on, as can be seen in figure 5. If all the empty memory buffers have been used, the waiting for completion of the flash write or retry operations shall be performed, in order to empty another memory buffer, for reception of further new data.
The data which has not yet been written successfully to the flash media (i.e. which write status has not yet been received) should not be replaced, as it may be needed to retry the failed write operation.
It should also be noted that if the size of the host system transfer unit (sector) is different from the flash array's access unit size ('page' in some flash technologies), the system should either record which part of the data has not been transferred from the host during the write procedure, or read this part from the flash media, possibly into the memory buffer prior to the transfer.
In case when the data of a system's logical block N+l is read (Figure 2) from the flash media 26 to the memory buffer A 24, the data of logical block N is simultaneously sent to the host interface 20 from the memory buffer B 22. If there are only 2 logically independent memory buffers, upon completion of the data transfer from B, software should wait for completion of the read operation to the buffer A, then check the EDC/ECC status of the read data. If the EDC/ECC mechanism (be it software or circuitry) indicates a correctable error, a corrective action can be taken upon the data in memory buffer A, and if the EDC/ECC mechanism indicates an uncorrectable error, that error can optionally be passed to the host interface. If the correct data has been read or the corrupted data has been successfully corrected, a 'read' command should be issued to the flash media for the next logical block, and the flash system should wait for the new data, in order to be ready for transfer if needed. Then two new simultaneous transfers can be initiated: block N+l from the memory module A to the host interface and block N+2 from the flash media to the memory module B.
If there are more than 2 logically independent memory buffers, new transfers into the memory can be started without waiting for completion of the transfer to host. The new data will be placed into the available empty memory buffers C 66, D 68, and so on, as can be seen in figure 6. If all empty memory buffers have been used, the waiting for completion of the transfer to host operation shall be executed, in order to empty another memory buffer, for reading of the following user data. The data which has not yet been successfully transmitted to the host should not be replaced.
In order to improve the read and write performances of the system the two transfer operations (to and from the memory buffers) should be truly simultaneous, which means that two different data buses will be operational simultaneously. That is of course only possible if the number of logical blocks transferred to or from the host during a particular read or write operation is more than 1.
Figure 3 is an example of a system which sends data to the host interface 30 from one memory module 32 and simultaneously receives the next portion of the data (to be sent) from the flash 36 to another memory module 34. This system is similar to the system in
Figure 1, with the distinction that memory modules are located inside the flash memory controller 38. Figure 4 is an example of system which receives new data from the host interface 40 to one memory module 42 and simultaneously writes the preceding portion of the new data from another memory module 44 into flash memory 46. This system is similar to the system in Figure 2, with the distinction that memory modules are located inside the flash memory controller 48.
The preferred embodiment of the present invention incorporates a system for synchronizing memory-to-host and flash-to-memory transfers, during the host read operation. This system comprises: i. Memory register or variable (the term "memory register" in this context may include use of the term "variable") for each memory buffer, which indicates the status of the buffer, where the status can be 'empty', 'in process of data reception', 'contains data of the logical block N' and, 'contains corrupted data of the logical block N'. ii. Memory-to-host control thread which, for each logical block N of data, part of which is to be transferred to the host, awaits for some memory buffer to acquire status of 'contains the data of the logical block N', and then initiates the data transfer of the user data to the host, upon the completion of the transfer, marks that memory buffer as 'empty'. The term, 'Control Thread', here and elsewhere, relates to the software or hardware control flow related to a particular task. iii. Flash-to-memory control thread which for each logical block N of data, part of which is to be transferred to the host, awaits for some memory buffer to acquire status of 'empty', optionally marks that memory buffer as 'in process of data reception', then issues read command to the flash memory device which contains the data. When the flash device is ready to produce the data, the control thread initiates the data transfer of the user data from the flash to the memory buffer. Upon the completion of the transfer, the thread examines the data correctness status calculated by the ECC/EDC mechanism (software or circuitry). If the data is corrupted but can be corrected, a correction algorithm can be employed. If the data residing in the buffer is correct or has been corrected, the thread marks that memory buffer as 'contains data of the logical block N', otherwise it marks that memory buffer as 'contains corrupted data of the logical block N'. iv. The flash-to-memory control thread operates independently from the memory-to-host control thread, either truly simultaneously or with preemption of control. The synchronization between the control threads is perfomed using the registers or variables of the RAM Buffer status. The process of changing this memory register or variable by a thread should be atomic, in the sense that other threads will only see the whole result of the change, and can not see the partially changed status.
The preferred embodiment of the present invention further incorporates a system for synchronizing host-to-memory and memory-to-flash transfers, during the host write operation. This system comprises: i. Memory register or variable for each memory buffer which indicates the status of the buffer, where status can be 'empty', 'in process of data reception' or 'contains data of the logical block N'. ii. Host-to-memory control thread which for each logical block N of data, part of which is to be transferred from the host, awaits for some memory buffer to acquire status of 'empty', optionally marks that memory buffer as 'in process of data reception', and then initiates the data transfer of the user data from the host, upon the completion of the transfer marks that memory buffer as
'contains the data of the logical block N'. If the data transferred from host does not coincide with flash array's access unit size ('page' in some flash technologies) then the thread reads from the flash the contents of the parts of the page which have not been transferred from the host. iii. Memory-to-flash control thread which for each logical block N of data, part of which has been transferred from the host, awaits for some memory buffer to acquire status of 'contains the data of the logical block N', then issues write command(s) to the flash memory device(s) in accordance with the flash storage algorithm. If the write command fails, the data can be written again, possibly multiple times, possibly to different locations of the flash media, in accordance with the flash storage algorithm. If the user data has been successfully written on flash, the thread marks that memory buffer as 'empty', otherwise the host should be notified about the host write command failure, iv. This memory-to-Flash control thread operates independently from the host- to-memory control thread, either truly simultaneously or with preemption of control. The synchronization between the control threads is performed by the registers or variables of the RAM Buffer status. The process of changing this memory register or variable by a thread should be atomic in the sense that other thread will only see the whole result of the change, and can not see the partially changed status.
In a further preferred embodiment of the present invention, the configuration for such a system includes the memory module inside each flash memory controller, as shown on Figures 3 and 4. Figure 3 is an example of system which sends data to the disk interface from one memory module and simultaneously receives the next portion of the data (to be sent) from the flash to another memory module. The system is similar to the system in Figure 1, with the distinction that memory modules are located inside the flash memory controller. Figure 4 is an example of a system which receives new data from the disk interface to one memory module and simultaneously writes the preceding portion of the new data from another memory module into the flash memory. This system is similar to the system in Figure 2, with the distinction that memory modules are located inside the flash memory controller. This can considerably simplify the design of the system. Of course, a combination of all mentioned configurations can also be implemented.
According to an alternative preferred embodiment of the present invention, these memory buffers may also serve as part of a data cache system. For example, after the data has been transferred to the host during a Read operation or has been received from host during Write operation, and if the host during subsequent Read operation requests the same data, the same data left in the buffer may be transferred to the host without accessing the flash memory. Alternatively, after the data has been received from host during Write operation, it may be left in the buffer for some time without writing it onto the flash media. This is referred to as being transferred directly to/from the host.
While the invention has been described with respect to a limited number of embodiments, it will be appreciated that many variations, modifications and other applications of the invention may be made.

Claims

Claims
1. A system for enabling simultaneous data transfer between a host interface and flash media , comprising: i. A processing system for enabling interaction with a host; ii. At least one flash memory device for storing data of said processing system; and iii. At least two RAM components, each said RAM component with a seperate data bus, for enabling simultaneous read and write operations between said processing system and said flash memory device.
2. The system of claim 1, further comprising Error detection (EDC) circuitry for calculating syndromes of data written into said flash memory device and data read from said flash memory device.
3. The system of claim 1, further comprising Error correction (ECC) circuitry for correcting data read from said flash memory device.
4. The system of claim 1, including at least two flash memory controllers, such that at least one of said RAM components resides inside each said flash memory controller.
5. The system of claim 1, wherein said RAM components are substituted for at least one dual-port memory component.
6. The system of claim 1, wherein said RAM components are integral parts of a larger integrated circuit.
7. The system of claim 1, wherein said RAM components form at least a part of a data cache system, such that after said data has been transferred to a host during Read operation, and if said host during subsequent Read operation requests same said data, same said data left in said RAM components is transferred directly to said host system.
8. The system of claim 1, wherein said RAM components are at least a part of a data cache system, such that after said data has been received from a host during Write operation, and if said host during subsequent Read operation requests same said data, same said data left in said RAM components is transferred directly from said host system.
9. A system for synchronizing memory-to-host and flash device-to-memory data transfers in a solid state storage system, during the host read operation comprising: i. A plurality of memory buffers for storing data between the host system and the flash device; ii. A memory register for each said memory buffer, for indicating status of said buffer, such that said status is used for synchronization of memory-to- host and flash-to-memory control threads; iii. A memory-to-host data transfer control thread, for initiating data transfer of user data to a host, and, upon completion of said data transfer, for marking said memory buffer as empty; and iv. A flash-to-memory control thread for issuing a read command to the flash memory device which contains said data, following which, when the flash device is ready to produce said data, initiating said data transfer of user data from the flash to said memory buffer.
10. The system of claim 9, wherein said flash-to-memory control thread operates independently from said memory-to-host control thread.
11. The system of claim 9, wherein step iii. comprises the steps of: a) Upon completion of said transfer, examining data correctness status, calculated by an Error Detection Mechanism; b) If said data is corrupted and can be corrected, employing a correction algorithm; and c) If said data residing in said memory buffer is correct, marking that memory buffer as containing data of a particular logical block; and d) If said data residing in said memory buffer is incorrect, marking that memory buffer as containing corrupted data.
12. The memory register of claim 9, wherein said status indicates a current state of said each memory buffer, including:
(a) an empty state, which is available for reception of new data;
(b) a state whereby the system contains data of a particular logical block; and
(c) a state whereby the system contains corrupted data of said logical block.
13. A system of synchronizing host-to-memory and memory-to-flash device data transfers in a solid state storage system, during the host write operation, comprising: i. A plurality of memory buffers for storing data between the host system and the flash device; ii. A memory register for indicating status for each said memory buffer; such that said status is used for synchronization of host-to-memory and memory-to-flash control threads; iii. A host-to-memory data transfer control thread, which for each particular logical block of data, part of which is to be transferred from the host, awaits for some memory buffer to acquire an empty status, and then initiating a data transfer of user data from said host, such that on completion of said transfer, said data transfer control thread marks said memory buffer as containing the data of said particular logical block, iv. A memory- to-flash data transfer control thread which for each particular logical block of data, part of which has been transferred from said host, awaits for some memory buffer to acquire a status of containing the data of said particular logical block, issuing at least one write command to at least one of the flash memory device in accordance with a flash storage algorithm.
14. The system of claim 13, wherein said memory-to-Flash control thread operates independently from the host-to-memory control thread.
15. The memory register of claim 13, wherein said status indicates a current state of said each memory buffer, including:
(a) an empty state, which is available for reception of new data; and
(b) a state whereby the system contains data of a particular logical block.
16. The system of claim 13, wherein function of said host-to-memory data transfer control thread further comprises the step of: if the data transferred from said host does not coincide with access unit size of said flash array, reading from the flash part of said data contents which have not been transferred from said host.
17. A method for synchronizing a memory-to-host and a flash device-to-memory data transfer in a solid state storage system, during the host read operation, comprising the steps of: i. providing a plurality of memory buffers, for storing data between the host system and the flash device; ii. commanding a memory register for each said memory buffer, to indicate status of said memory buffer; iii. commanding a memory-to-host data transfer control thread, for each logical block being transferred, to wait for said memory buffer to acquire a status of whereby data of a logical block is contained, following which data transfer of said logical block to said host is initiated, upon the completion of which said control thread marks said memory buffer as empty; and iv. commanding a flash-to-memory data transfer control thread, for each logical block of data, to wait for some said memory buffer to acquire a status of being empty, then issuing a read command to the flash memory device which contains said data; v. when said read command is complete, and when the flash memory device is ready to produce said data, initiating a data transfer of said user data to said memory buffer, by said flash-to-memory data transfer control thread.
18. The method of claim 17, wherein commanding a memory register further entails commanding a variable for each said memory buffer.
19. The method of claim 17, further comprising the steps of: a) examining correctness status of said data; b) if said data is corrupted but can be corrected, employing a correction mechanism; c) if said data residing in said buffer is correct, marking said memory buffer as containing data of the logical block; and d) if said data is corrupted, marking said memory buffer as containing corrupted data of the logical block.
20. A method for synchronizing host-to-memory and memory-to-flash transfers in a solid state storage system, during the host write operation, comprise the steps of: i. providing a plurality of memory buffers, for storing data between the host system and the flash device; ii. commanding a memory register for each memory buffer, to indicate status of said memory buffer. iii. commanding host-to-memory data transfer control thread, for each logical block, to wait for some said memory buffer to acquire an empty status, and then initiating a data transfer of user data from said host, upon the completion of said data transfer marks that said memory buffer as containing the data of said logical block, whereafter if said data transferred from said host does not coincides with access unit size of the flash array, then said thread reads from the flash device contents of parts of a page which has not been transferred from said host; iv. commanding memory-to-flash data transfer control thread, for each logical block of data, to wait for some said memory buffer to acquire status of containings data of a particular logical block, then issuing at least one write command to the at least one flash memory device in accordance with a flash device storage algorithm, subsequently if a write command fails, said data can optionally be written again to a different location, in accordance with said flash device storage algorithm, such that if said user data has been successfully written on flash, said thread marks said memory buffer as being empty, otherwise notifies said host about write command failure.
21. The method of claim 20, wherein commanding a memory register further entails commanding a variable for each said memory buffer.
PCT/US2002/006454 2001-03-05 2002-03-04 A method for using ram buffers with multiple accesses in flash-based storage systems WO2002071228A1 (en)

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Families Citing this family (41)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6883109B2 (en) * 2001-07-30 2005-04-19 Hewlett-Packard Development Company, L.P. Method for accessing scan chains and updating EEPROM-resident FPGA code through a system management processor and JTAG bus
US6954929B2 (en) * 2001-07-30 2005-10-11 Hewlett-Packard Development Company, L.P. Method for just-in-time updating of programming parts
US20040225783A1 (en) * 2001-07-30 2004-11-11 Erickson Michael John Bus to multiple jtag bus bridge
US6918027B2 (en) * 2001-07-30 2005-07-12 Hewlett-Packard Development Company, L.P. System and method for in-system programming through an on-system JTAG bridge of programmable logic devices on multiple circuit boards of a system
KR100498508B1 (en) * 2003-09-16 2005-07-01 삼성전자주식회사 Dual buffering memory system for reducing data transmission time and control method thereof
EP1686482B1 (en) * 2003-11-18 2013-03-06 Panasonic Corporation File recording device
US7173863B2 (en) * 2004-03-08 2007-02-06 Sandisk Corporation Flash controller cache architecture
KR100606242B1 (en) * 2004-01-30 2006-07-31 삼성전자주식회사 Volatile Memory Device for buffering between non-Volatile Memory and host, Multi-chip packaged Semiconductor Device and Apparatus for processing data using the same
DE102004055013A1 (en) * 2004-11-15 2006-05-24 Infineon Technologies Ag computer equipment
JP4695385B2 (en) * 2004-11-30 2011-06-08 株式会社東芝 Memory card and card controller
DE102004058528B3 (en) 2004-12-04 2006-05-04 Hyperstone Ag Memory system for reading and writing logical sector, has logical sectors for communication with host system are buffered in sector buffers and assigned by direct-flash-access-units between sector buffers and flash memory chips
US7245527B2 (en) * 2005-05-16 2007-07-17 Freescale Semiconductor, Inc. Nonvolatile memory system using magneto-resistive random access memory (MRAM)
JP5130646B2 (en) * 2005-06-06 2013-01-30 ソニー株式会社 Storage device
US7441102B2 (en) * 2006-02-28 2008-10-21 Freescale Semiconductor, Inc. Integrated circuit with functional state configurable memory and method of configuring functional states of the integrated circuit memory
US7904639B2 (en) * 2006-08-22 2011-03-08 Mosaid Technologies Incorporated Modular command structure for memory and memory system
US8230154B2 (en) * 2007-01-19 2012-07-24 Spansion Llc Fully associative banking for memory
WO2008101316A1 (en) * 2007-02-22 2008-08-28 Mosaid Technologies Incorporated Apparatus and method for using a page buffer of a memory device as a temporary cache
US8086785B2 (en) * 2007-02-22 2011-12-27 Mosaid Technologies Incorporated System and method of page buffer operation for memory devices
US8694714B2 (en) * 2008-01-18 2014-04-08 Spansion Llc Retargeting of a write operation retry in the event of a write operation failure
US20090254705A1 (en) * 2008-04-07 2009-10-08 International Business Machines Corporation Bus attached compressed random access memory
US8423592B2 (en) 2008-04-11 2013-04-16 Sandisk Technologies Inc. Method and system for accessing a storage system with multiple file systems
US20090327535A1 (en) * 2008-06-30 2009-12-31 Liu Tz-Yi Adjustable read latency for memory device in page-mode access
US8468417B2 (en) * 2009-02-18 2013-06-18 Micron Technology, Inc. Data integrity in memory controllers and methods
KR101175250B1 (en) 2009-06-29 2012-08-21 에스케이하이닉스 주식회사 NAND Flash Memory device and controller thereof, Write operation method
US8683456B2 (en) * 2009-07-13 2014-03-25 Apple Inc. Test partitioning for a non-volatile memory
JP5209793B2 (en) * 2009-08-21 2013-06-12 パナソニック株式会社 Nonvolatile storage device, access device, and nonvolatile storage system
WO2011036230A2 (en) * 2009-09-23 2011-03-31 St-Ericsson Sa Data transfer method
US8725977B2 (en) 2010-02-17 2014-05-13 Seagate Technology Llc NVMHCI attached hybrid data storage
US8645776B2 (en) * 2010-03-24 2014-02-04 Apple Inc. Run-time testing of memory locations in a non-volatile memory
US8650446B2 (en) * 2010-03-24 2014-02-11 Apple Inc. Management of a non-volatile memory based on test quality
US8751903B2 (en) 2010-07-26 2014-06-10 Apple Inc. Methods and systems for monitoring write operations of non-volatile memory
EP2418584A1 (en) 2010-08-13 2012-02-15 Thomson Licensing Method and apparatus for storing at least two data streams into an array of memories, or for reading at least two data streams from an array of memories
KR101166803B1 (en) 2010-12-31 2012-07-26 세종대학교산학협력단 System including volatile memory and non-volatile memory and processing mehthod thereof
JP5547701B2 (en) * 2011-09-21 2014-07-16 日立オートモティブシステムズ株式会社 Electronic control unit for automobile
KR101934519B1 (en) * 2012-11-26 2019-01-02 삼성전자주식회사 Storage device and data transfering method thereof
WO2016054640A1 (en) * 2014-10-03 2016-04-07 Ezuniverse Inc. Data management system
KR102461453B1 (en) 2015-06-10 2022-11-02 삼성전자주식회사 Storage device
US10521118B2 (en) * 2016-07-13 2019-12-31 Sandisk Technologies Llc Methods, systems, and computer readable media for write classification and aggregation using host memory buffer (HMB)
US10216685B1 (en) * 2017-07-19 2019-02-26 Agiga Tech Inc. Memory modules with nonvolatile storage and rapid, sustained transfer rates
JP7155028B2 (en) * 2019-01-29 2022-10-18 キオクシア株式会社 Memory system and control method
CN116931842B (en) * 2023-09-12 2023-12-08 合肥康芯威存储技术有限公司 Memory, data processing method, electronic equipment and medium

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5339408A (en) * 1992-12-30 1994-08-16 Digital Equipment Corporation Method and apparatus for reducing checking costs in fault tolerant processors
US5588112A (en) * 1992-12-30 1996-12-24 Digital Equipment Corporation DMA controller for memory scrubbing
US5603001A (en) * 1994-05-09 1997-02-11 Kabushiki Kaisha Toshiba Semiconductor disk system having a plurality of flash memories
US5884055A (en) * 1996-11-27 1999-03-16 Emc Corporation Method and apparatus including a shared resource and multiple processors running a common control program accessing the shared resource

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6474649A (en) * 1987-09-16 1989-03-20 Nec Corp Sector buffer control system
US5359569A (en) * 1991-10-29 1994-10-25 Hitachi Ltd. Semiconductor memory
JPH06195258A (en) * 1992-07-08 1994-07-15 Nec Corp Semiconductor memory
JPH06332664A (en) * 1993-03-23 1994-12-02 Toshiba Corp Display control system
US5438549A (en) * 1994-02-28 1995-08-01 Intel Corporation Nonvolatile memory with volatile memory buffer and a backup power supply system
JPH08235852A (en) * 1995-02-28 1996-09-13 Mitsubishi Electric Corp Semiconductor storage device
US6418506B1 (en) * 1996-12-31 2002-07-09 Intel Corporation Integrated circuit memory and method for transferring data using a volatile memory to buffer data for a nonvolatile memory array
US5928370A (en) * 1997-02-05 1999-07-27 Lexar Media, Inc. Method and apparatus for verifying erasure of memory blocks within a non-volatile memory structure
US6016472A (en) * 1997-09-29 2000-01-18 Lucent Technologies Inc. System and method for interfacing a digital audio processor to a low-speed serially addressable storage device

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5339408A (en) * 1992-12-30 1994-08-16 Digital Equipment Corporation Method and apparatus for reducing checking costs in fault tolerant processors
US5347559A (en) * 1992-12-30 1994-09-13 Digital Equipment Corporation Apparatus and method of data transfer between systems using different clocks
US5588112A (en) * 1992-12-30 1996-12-24 Digital Equipment Corporation DMA controller for memory scrubbing
US5603001A (en) * 1994-05-09 1997-02-11 Kabushiki Kaisha Toshiba Semiconductor disk system having a plurality of flash memories
US5884055A (en) * 1996-11-27 1999-03-16 Emc Corporation Method and apparatus including a shared resource and multiple processors running a common control program accessing the shared resource

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