WO2002073661A2 - Extraction method of defect density and size distributions - Google Patents
Extraction method of defect density and size distributions Download PDFInfo
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- WO2002073661A2 WO2002073661A2 PCT/US2002/007409 US0207409W WO02073661A2 WO 2002073661 A2 WO2002073661 A2 WO 2002073661A2 US 0207409 W US0207409 W US 0207409W WO 02073661 A2 WO02073661 A2 WO 02073661A2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Definitions
- This invention relates to methods for measuring and evaluating the process and design related statistical variations of an integrated circuit manufacturing process in order to determine their sources and their effects on the yield and performance of the product.
- Defects e. g. particles
- faults e. g. particles
- defect density and size distributions are important for yield enhancement and to control quality of process steps and product chips, as described in Staper, C. H., Rosner, R. J., "Integrated Circuit Yield Management and Yield Analysis: Development and Implementation," IEEE Transactions on Semiconductor Manufacturing, pp. 95-102, Vol. 8, No. 2, 1995.
- Test structures are used to detect faults and to identify and localize defects.
- the double bridge test structure was proposed by Khare, et al., "Extraction of Defect Size Distributions in an IC Layer Using Test Structure Data," IEEE Transactions on Semiconductor Manufacturing, pp. 354-368, Vol. 7, No. 3, 1994, to extract size distributions based on electrical measurements.
- This test structure design requires two conducting layer having different resistivity. Thus, this design requires at least one polysilicon layer and one metal layer.
- the Ha ⁇ test structure was proposed by Hess, C, Weiland, L. H., "Harp Test Structure to Electrically Determine Size Distributions of Killer Defects," IEEE Transactions on Semiconductor Manufacturing, pp. 194-203, Vol. 11, No.
- Parallel lines - each connected to two pads - are implemented inside a test structure to electrically determine a defect size distribution. If a defect occurs and causes an electrically measurable fault, either two or more test structure lines are shorted or one or more test structure lines are opened. The greater the number of test structure lines involved, the larger the defect that caused this measured fault.
- FIG. 1 shows the principle design of such nested se ⁇ entine lines, which is based on a structure proposed by Glang, R., Defect Size Distribution in VLSI Chips, "IEEE Transactions on Semiconductor Manufacturing,” pp. 265-269, Vol. 4, No. 4, 1991.
- FIG. 1 shows a structure 100 having a plurality of nested se ⁇ entine lines 102a-102n, where n is the number of lines 102a-102n.
- Each line 102a-102n includes a pair of pads 104a-104n and 105a-105n, respectively.
- a pair of lines (e.g., 102a, 102b) requires four pads (e.g., 104a, 105a, 104b, 105b).
- Glang used 5 se ⁇ entine lines within two combs, and implemented several structures having different dimensions to determine a defect size distribution by comparing the number of detected defects dependent on the dimension of the structures. Having a high number of nested se ⁇ entine lines enables the direct extraction of defect size distribution by comparing the number of detected defects dependent on the number of involved lines.
- Each NEST structure is connected to a 2-by-N pad frame.
- FIG. 2 shows a complete NEST structure design, which was automatically generated in just a few seconds.
- This exemplary NEST structure 200 includes 3104 parallel lines in a single metal layer. [0008] In a 2-by-N pad frame the number of pads is very limited. To enable the detection of opens and shorts, each test structure line is connected to two pads. So, only N/2 lines may be implemented; that does not fill a relatively large chip area that is sufficient to detect random defects. For this reason, the lines are designed as se ⁇ entines to fill the complete test chip area. Nevertheless, an improved structure allowing a larger number of lines is desired.
- One aspect of the invention is a characterization vehicle, comprising a substrate having at least one layer, and a plurality of pairs of lines on a single surface of a single layer of the substrate, each pair of lines having a shared pad therebetween.
- Another aspect of the invention is a method of designing a characterization vehicle, comprising the steps of: arranging a plurality of pairs of lines on a single surface of a single layer of a substrate; and locating a respective shared pad between the lines of each pair of lines.
- Another aspect of the invention is a method of identifying defects, comprising the steps of: fabricating a characterization vehicle by forming a plurality of pairs of lines on a single surface of a single layer of a substrate, each pair of lines having a shared pad therebetween; and collecting defect data from the characterization vehicle.
- Yet another aspect of the invention is a method of determining defect size distributions, comprising the steps of: collecting defect size distributions from a characterization vehicle by forming a plurality of pairs of lines on a single surface of a single layer of a substrate, each pair of lines having a shared pad therebetween; and determining which one of a pair of sharing a pad therebetween has a defect by identifying a sequence of the that are shorted together.
- FIG. 1 is a diagram of an exemplary single layer NEST structure.
- FIG. 2 is a diagram showing an exemplary design for a NEST structure having a large number of parallel lines in a single layer.
- FIG. 3 is a diagram showing an exemplary placement of lines sharing pads in the center.
- FIG. 4 is a diagram showing the bottom lines routed according to an exemplary permutation procedure.
- FIG. 5 is a diagram showing a further exemplary type of NEST structure.
- FIG. 6 is a diagram showing a defect size distribution model.
- FIG. 7 is a flow chart diagram showing the method for fitting the parameters to the defect size distribution model of FIG. 6.
- FIG. 8 is a diagram showing critical areas for multiple line short events in a 16 line nest.
- FIG. 9 is a diagram showing critical area curves for a variety of types of short circuit defects.
- FIG. 10 shows the yield impact of various defect size distributions in a product chip.
- FIG. 11 is a histogram showing the distribution of defect sizes within an exemplary NEST structure.
- FIG. 12 is a photograph showing a detected defect causing a short circuit between two adjacent lines.
- FIG. 13 is a histogram showing the distribution of defect sizes within another exemplary NEST structure.
- FIG. 14 is a photograph showing a detected defect causing a short circuit among eleven lines.
- FIG. 15 is a flow chart diagram showing a method of determining in which side an identified defect occurred.
- an exemplary NEST structure has a plurality of nested se ⁇ entine lines.
- the plurality of nested se ⁇ entine lines are placed within a single layer.
- this mask can be used as a short flow to provide a short turn-around time for fast process data extraction.
- Data analysis procedures provide densities and size distributions of killer defects that have an impact on product chip yield.
- layer specific properties such as sheet resistance, and no requirement of any semiconductor devices to separate test structure lines or separate multiple faults, respectively.
- the NEST structure detects systematic problems as well as random defects to determine accurate defect densities and size distributions.
- FIG. 3 is a diagram in which the nested lines of the NEST structure are represented by straight lines, for easier visualization. It is understood that each line 301a-301h and 302a-302h represents a respective nested se ⁇ entine line. As shown in FIG. 3, two lines may be connected to three pads (instead of four in the regular NEST structure of FIG. 1), sharing a center pad between them.
- line 301a is connected to top pad 311a and center pad 312a
- line 302a is connected to bottom pad 313a and the same center pad 312a.
- each respective pair of lines including a top line 301a-301h and bottom line 302a-302h there is a respective top pad 311a-311h, a center pad 312a-312h and a bottom pad 313a-313h.
- 2*integer(M/3) lines can be implemented in a PD NEST structure instead of just N lines in a regular NEST structure.
- 16 lines can be implemented in a PD NEST.
- 20 lines may be implemented in a PD NEST structure, instead of just 15 lines in a regular NEST structure. In other words, 25% fewer pads are needed to hook up the same number of lines, which results in less test time due to less pad frame stepping time as well as significantly better usage of given chip area.
- a defect results in an open line, it can be clearly detected, either between a pad on the top and a center pad, or between a pad on the bottom and a center pad.
- a defect in one or more of lines 301a-301h that causes a short circuit on the top side is also measurable on the bottom side.
- the neighborhood relationship of the lines on the first (e.g., left) side and the second (e.g., right) side are changed using the Permutation Procedure described at Hess, C, Weiland, L. H., "Ha ⁇ Test Structure to Electrically Determine Size Distributions of Killer Defects," IEEE Transactions on Semiconductor Manufacturing, pp. 194-203, Vol.
- Parallel lines each connected to an isolated pad — are implemented inside a test structure to electrically determine a defect size distribution. If a defect occurs and causes an electrically measurable fault, two or more test structure lines are shorted. The more test structure lines are shorted together, the larger the defect is. But, if more than two se ⁇ entine lines are connected, it is difficult to say whether there is just one large defect or some small defects have caused a multiple fault. Short circuits will connect test structure lines if, and only if, the lines are placed as neighbors anywhere inside the test chip area. So, the more different neighbored test structure lines are implemented the more short circuits are distinguishable.
- the permutation procedure increases the number of differently neighbored test structure lines without increasing the number of pads.
- An undesigned short circuit defect is detectable between test structure lines connected to electrically distinguishable pads. For that, it is not necessary to give each test structure line an individual pad, but each pair of parallel test structure lines are connected to a unique set of pads. For this reason, all possible neighborhood relationships of adjacent lines are arranged inside a test chip no more than once.
- the bottom sequence of lines is 2-4-1-6-3-8-5-7.
- the first line has the index "2", indicating that the first bottom line shares a pad with (and is electrically connected to) the second line in the top set of lines.
- the second line has the index "4", indicating that the line shares a pad with the fourth line in the top set of lines.
- the third line has the index "1", indicating that the line shares a pad with the first line in the top set of lines.
- the fourth through eighth lines have the indices "6,” “3,” “8,” “5,” and “7", respectively, indicating that the lines share respective pads with the 6 th , 3 rd , 8 th , 5 th and 7 th lines, respectively, in the top set of lines.
- each bottom line with index a[2,j] has one or two neighboring lines with indices a[2,j-l] and/or a[2,j+l].
- the corresponding top line a[l,j] which shares a pad with line a[2,j] has one or two neighboring lines with indices a[lj-l] and/or a[l,j+l].
- the following inequalities hold for every value of j: [0042] a[2,j-l] ⁇ a[l,j-l]
- FIG. 4 shows an example for 2*8 lines. As in FIG. 3, there are top pads 411a-
- FIG. 4 adds a routing channel 420 with connecting lines 403a-403d and 404a-404d. Beside each line 401a-401h and 402a-402h, the "Permutation index" can be seen.
- the bottom lines 402a-402h are rearranged so that each line has a Permutation index next to it that is different from its ordinal position in the sequence of bottom lines, (i.e., the first line 402a does not have the permutation index "1," the second line 402b does not have the permutation index "2,” etc.) Also, the arrangement of the permutation indices is such that no bottom line 402a-402h is adjacent to a line having the closest greater or lesser permutation index.
- the top line 401c (permutation index “3") is adjacent to the top line 401b (permutation index “2") and top line 401d (permutation index "4"), but the bottom line 402e (permutation index "3") is adjacent to the bottom line 402d (permutation index "6") and bottom line 402f (permutation index "8").
- the different neighborhood relationships provide easy separation of defects that result in shorts in the top lines 401a-401h and bottom lines 402a-402h.
- a routing channel 420 can be provided, as seen in FIG. 4.
- the routing channel 420 as drawn in FIG. 4 includes crossings 403a-403d and 404a-404d that are not available on a single mask. The inventors have determined that the complete routing can be implemented without crossings, if broken apart into two groups - the set of all solid routing lines 403a-403d shown in FIG. 4 and the set of dashed routing lines 404a-404d. [0049] FIG.
- FIG. 5 is a diagram of a characterization vehicle 500 comprising a substrate 599 having at least one layer, and a plurality of pairs of nested se ⁇ entine lines 501-524 on a single surface of a single layer of the substrate, each pair of nested se ⁇ entine lines having a shared pad 1M-8M therebetween.
- FIG. 5 is an exemplary routing of the set of lines in FIG. 4, wherein the nested se ⁇ entine lines are drawn.
- the bottom set of lines are sequentially numbered "1" through “8”, and the top set of lines are numbered by the sequence 2-4-1-6-3-8-5-7.
- the top set of lines is the second set and bottom set of lines is the first set. This is the opposite of FIG.
- the characterization vehicle 500 comprises a substrate 599 having at least one layer with a first (top) side 519 above line 595 and a second (bottom) side 592 below line 595.
- a first row of pads 501-512 is on the first side 591 of the substrate 599.
- a second row of pads 513-524 is on the second side 592 of the substrate 599.
- a plurality of pairs of nested se ⁇ entine lines (551 and 562, 552 and 564, 553 and 561, 554 and 566, 555 and 563, 556 and 568, 557 and 565, 558 and 567) are on the substrate.
- the pairs of pads are designated IL and 1R, 2L and 2R, ..., 8L and 8R.
- the designations L and R signify “left” and “right,” but these designations are arbitrary, and do not require a particular orientation of the patterns or of the characterization vehicle 500. L could alternatively correspond to “right,” “bottom” or “top” and R could correspond to "left,” top” or “bottom,” so long as L and R correspond to two different sides.
- Each pair of nested se ⁇ entine lines has a shared pad 1M-8M (items 513, 512,
- Each pair (e.g., 551 and 562) of nested se ⁇ entine lines 501-524 includes a first line (e.g., 551) and a second line (e.g., 562), such that: the first line (e.g., 551) extends beyond the first row of pads 501-512 on the first side 591 of the substrate 599, and the second line (e.g., 562) extends beyond the second row of pads 513-524 on the second side 592 of the substrate 599.
- FIG. 5 is an example of one such routing.
- top, center and bottom of FIG. 4 are rearranged to fit in two rows of pads.
- One routing set is placed in one half of a 2-by-N pad frame (e.g. top row of pads 501-512 drawn 2-by-N in FIG. 5), while the other routing set is placed in the other part of a 2-by-N pad frame (e.g., the bottom row of pads 513-524 horizontally drawn 2-by-N in FIG. 5).
- the top row of pads 501- 512 includes "right” pads designated 1R to 8R, and “middle” pads designated 2M, 3M, 6M and 7M.
- the bottom row of pads 513-524 includes "left” pads designated IL to 8L, and "middle” pads designated 1M, 4M, 5M and 8M.
- the permutation indices 1R-8R, 1M-8M and 1L-8L indicate which pads are connected to each other. Pads having the same number in their respective indices are connected. No pad is positioned directly opposite a pad to which it is connected. For example, pad 512 (permutation index 2M) is connected to pad 501 (permutation index 2R) and pad 514 (permutation index 2L).
- the indices of the lines that are shorted together indicates whether the defect can be found in the upper or lower section of the PD NEST structure. For example, if only lines connected to pads having the permutation indices 2 and 4 are shorted together, then the short circuit must be on the top half of the configuration, between the lines 551 and 552 connected to pads 501 and 502, respectively. If, however, only lines connected to pads having the permutation indices 2, 3 and 4 are all shorted together, then the short circuit must be on the bottom half of the configuration, among lines 562, 563 and 564.
- FIG. 5 Although the preferred embodiment of FIG. 5 includes nested se ⁇ entine lines, one of ordinary skill could implement other test structures using the techniques described herein. For example, comb structures or any other test structures capable of measuring shorts, or combinations thereof (e.g., comb and nest) , may be implemented instead of nested se ⁇ entine lines.
- comb structures or any other test structures capable of measuring shorts, or combinations thereof e.g., comb and nest
- placing the lines 551-558, 561-568 and pads 501-524 on a single surface of a single layer of the characterization vehicle 599 does not prevent the characterization vehicle from having other layers.
- the configuration shown in FIG. 5 or another configuration of pads and nested se ⁇ entine lines can be included on one surface of a characterization vehicle having additional layers.
- the area per NEST structure should be limited such that on average no more than one defect is expected within two NEST structures.
- the resistance value per line should be within the limits given by the testing equipment.
- testing time should be within a given limit per wafer, which gives the maximum number of pad frames and NEST structures that may be implemented within a die.
- testing time usually is the main limitation for analog DC measurements using a parametric tester.
- the line resistance usually is the main limitation for the NEST structure design.
- Open circuits are tested by measuring the resistance between the two pads connected to a single line of a NEST or PD NEST structure.
- a given NEST or PD NEST structure of M lines will result in a vector with M values each standing for a detected open line.
- One open circuit is caused by a defect interrupting the lines 3 and 4.
- the second open circuit is caused by a defect interrupting the lines 10, 11, and 12.
- Short circuits are tested by measuring the resistance between two pads connected to adjacent lines.
- a given NEST structure of M lines results in a vector with M values each standing for a line being involved in a short circuit.
- One short circuit is caused by a defect connecting the lines 6, 7, and 8.
- FIG. 15 is a flow chart diagram of the method for localizing a single fault.
- a set of sides is selected containing the indices of all connected pads. To get a valid solution, each side within the set has at least one common pad index with at least one other side within the set. A set containing the smallest possible number of sides also indicates the minimum number of defects that have caused the measured multiple fault. [0083] Based on the testing procedure and defect detection method one can generate a histogram for open circuits as shown in FIG. 11, as well as a histogram for short circuits as can be seen in FIG. 13. [0084] Data Analysis Procedure for Defect Size Modeling [0085] Having briefly discussed the testing procedure of the NEST structure, the algorithms to extract the size distribution of such defects that have caused electrically measurable faults within NEST structures are now described.
- Equations (1) and (2) are the (statistically based) random defect modeling equations. Equation (1) provides the predicted yield result after DSD(x) is determined from the electrical test data. The critical areas in terms of the range of defect sizes are defined and extracted from the layout. This model has been found to accurately model random defects in many deep sub-micron technologies. Auxiliary terms can be added to the model to account for different defect distributions such as clustering and systematic lithography defects.
- FIG. 7 is a flow chart showing the overall algorithm for DSD fitting. The key inputs to the equations are:
- step 702 initial values for Do and p are chosen.
- the coefficients k, p are fitted to the electrical data (as described below) and/or monte carlo simulations where algorithms are used to unravel the size distributions from the various combinations of measured shorts and opens. Then the predicted yield of equation (1) will be consistent with the observed yield Y of the characterization vehicle when the right coefficients are determined for the DSD distribution function.
- step 704 the expected count of shorts for each measurement is calculated.
- the objective function is caluclated, where Si s the expected count of shorts.
- a convergence check is performed.
- the obj function provides a normalized measure of whether the currend values of Do and p provide an expected value of
- step 712 if the algorithm has not yet converged, then new values of Do and p are selected. These new values of Do and p can be calculated using a predetermined algorithm, or chosen manually using human judgment. Steps 704-712 are then repeated until convergence is achieved. [0097] Since the algorithm is based on the concept of critical area, it handles both extra material defects ("shorts") and missing material defects ("opens”) in the same manner. [0098] These input data are described below.
- An " -line short” event is a type of event in which i lines are shorted together in a given sample of test data. For a simple nest, there are 15 "/-line short” events (2 adjacent lines shorted, 3 adjacent lines shorted, and so on up to 16 adjacent lines shorted).
- An "i-line open” event is the an event in which an open test results in / adjacent lines. Sixteen such events are possible in a simple nest (1 line open up through 16 adjacent lines open).
- Microevent probabilities are calculated from the test data by counting the frequency with which electrical tests fail in adjacent lines.
- Microevent critical area extraction [0107] FIG. 8 is a diagram showing how critical area varies with the defect radius.
- FIG. 10 One example for a defect distribution proportional to 1/x 2'25 can be seen in FIG. 10.
- FIG. 10 Another example for a defect distribution proportional to 1/x 3 can be seen in FIG. 10.
- the yield impact on product chips was studied. For that, the cumulative critical area was determined for several typical product chips as one can be seen in FIG. 9.
- the different curves in this graph show the different cumulative critical area curves for 2 line shorts, 3-line shorts, 4-line shorts, 5-line shorts, and 6-line shorts. Only the 2-line shorts and the 3-line shorts have some critical areas in the small size region of interested.
- the yield impact is proportional to the integral of the critical area multiplied by the defect size distribution as can be seen in FIG. 6 for different defect size distributions. It can be seen that the yield impact for the smallest defect size interval is less than 5%. So, even a relatively large error in this region is acceptable if it comes to yield prediction.
- NEST structures have been manufactured in different fabrication shops world wide to control defect appearance in a deep submicron backend environment Glang, R., Defect Size Distribution in VLSI Chips, "IEEE Transactions on Semiconductor Manufacturing," referenced above, summarizes an example set of NEST structures used to extract defect size distributions.
- Using differently dimensioned NEST structures enables the separation of systematic and random defects. If defects occur and cause a fault, either test structure lines are connected to each other or test structure lines are interrupted. Because it is known which test structure lines are implemented as neighbors, the number and size of the defects can be determined. Based on the number of shorted lines, the algorithms above can be applied to determine a defect size distribution as can be seen in FIGS. 11 and 13. SEM pictures of two detected defects can be seen in FIGS. 12 and 14. The same principle could be applied for opens, but the observed defect density was too small to actually generate a significant defect size histogram.
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JP2002572613A JP3998577B2 (en) | 2001-03-12 | 2002-03-12 | Characterization Vehicle and Design Method, Defect Identification Method, and Defect Size Distribution Determination Method |
AU2002247317A AU2002247317A1 (en) | 2001-03-12 | 2002-03-12 | Extraction method of defect density and size distributions |
US10/471,775 US7024642B2 (en) | 2001-03-12 | 2002-03-12 | Extraction method of defect density and size distributions |
EP02715098A EP1379978A4 (en) | 2001-03-12 | 2002-03-12 | Extraction method of defect density and size distributions |
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2002
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- 2002-03-12 WO PCT/US2002/007409 patent/WO2002073661A2/en active Application Filing
- 2002-03-12 AU AU2002247317A patent/AU2002247317A1/en not_active Abandoned
- 2002-03-12 JP JP2002572613A patent/JP3998577B2/en not_active Expired - Fee Related
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- 2002-03-12 CN CN02806431.3A patent/CN1262960C/en not_active Expired - Fee Related
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Cited By (2)
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---|---|---|---|---|
JP2006515464A (en) * | 2002-12-11 | 2006-05-25 | ピー・デイ・エフ ソリユーシヨンズ インコーポレイテツド | System and method for fast positioning of electrical faults on integrated circuits |
DE112004001975B4 (en) * | 2003-10-15 | 2009-11-05 | PDF Solutions, Inc., San Jose | Method and arrangement for connecting test structures or line arrays for monitoring the production of integrated circuits |
Also Published As
Publication number | Publication date |
---|---|
CN1262960C (en) | 2006-07-05 |
EP1379978A2 (en) | 2004-01-14 |
CN1496526A (en) | 2004-05-12 |
US20040094762A1 (en) | 2004-05-20 |
WO2002073661A3 (en) | 2002-11-14 |
EP1379978A4 (en) | 2005-06-08 |
AU2002247317A1 (en) | 2002-09-24 |
JP3998577B2 (en) | 2007-10-31 |
JP2004526316A (en) | 2004-08-26 |
WO2002073661A9 (en) | 2003-01-09 |
US7024642B2 (en) | 2006-04-04 |
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CHIPS | 5 DEFECT MONITORING AND YIELD PROJECTION |
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