WO2002078227A3 - Communication of latencies in parallel networks - Google Patents

Communication of latencies in parallel networks Download PDF

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Publication number
WO2002078227A3
WO2002078227A3 PCT/GB2002/001291 GB0201291W WO02078227A3 WO 2002078227 A3 WO2002078227 A3 WO 2002078227A3 GB 0201291 W GB0201291 W GB 0201291W WO 02078227 A3 WO02078227 A3 WO 02078227A3
Authority
WO
WIPO (PCT)
Prior art keywords
processor
latencies
parallel networks
communication
channel adapter
Prior art date
Application number
PCT/GB2002/001291
Other languages
French (fr)
Other versions
WO2002078227A2 (en
Inventor
Gregory Mann
Original Assignee
Ibm
Ibm Uk
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm, Ibm Uk filed Critical Ibm
Priority to AU2002241132A priority Critical patent/AU2002241132A1/en
Priority to KR10-2003-7011778A priority patent/KR20030085141A/en
Publication of WO2002078227A2 publication Critical patent/WO2002078227A2/en
Publication of WO2002078227A3 publication Critical patent/WO2002078227A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/382—Information transfer, e.g. on bus using universal interface adapter
    • G06F13/387—Information transfer, e.g. on bus using universal interface adapter for adaptation of different data processing systems to different peripheral devices, e.g. protocol converters for incompatible systems, open system
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G06F5/065—Partitioned buffers, e.g. allowing multiple independent queues, bidirectional FIFO's
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/14—Channel dividing arrangements, i.e. in which a single bit stream is divided between several baseband channels and reassembled at the receiver
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/04—Speed or phase control by synchronisation signals
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/04—Speed or phase control by synchronisation signals
    • H04L7/10—Arrangements for initial synchronisation

Abstract

In parallel networks that include a transmission media and at least one I/O processor connected to the transmission media by a core, a buffering device is provided that compensates for different latencies from all physical lanes in data links so that data transmission occurs at the same time in the receive path of the I/O 'processor.' The processor can be an I/O device for a host channel adapter, a target channel adapter, or an interconnect switch in an InfiniBand-type network.
PCT/GB2002/001291 2001-03-23 2002-03-19 Communication of latencies in parallel networks WO2002078227A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
AU2002241132A AU2002241132A1 (en) 2001-03-23 2002-03-19 Communication of latencies in parallel networks
KR10-2003-7011778A KR20030085141A (en) 2001-03-23 2002-03-19 A communication system

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/816,969 US6625675B2 (en) 2001-03-23 2001-03-23 Processor for determining physical lane skew order
US09/816,969 2001-03-23

Publications (2)

Publication Number Publication Date
WO2002078227A2 WO2002078227A2 (en) 2002-10-03
WO2002078227A3 true WO2002078227A3 (en) 2003-05-15

Family

ID=25222048

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/GB2002/001291 WO2002078227A2 (en) 2001-03-23 2002-03-19 Communication of latencies in parallel networks

Country Status (5)

Country Link
US (1) US6625675B2 (en)
KR (1) KR20030085141A (en)
AU (1) AU2002241132A1 (en)
TW (1) TW581960B (en)
WO (1) WO2002078227A2 (en)

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US7012935B2 (en) * 2002-05-16 2006-03-14 Intel Corporation Alignment and deskew device, system and method
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US8190722B2 (en) * 2003-06-30 2012-05-29 Randy Oyadomari Synchronization of timestamps to compensate for communication latency between devices
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US7007115B2 (en) * 2003-07-18 2006-02-28 Intel Corporation Removing lane-to-lane skew
US20050024926A1 (en) * 2003-07-31 2005-02-03 Mitchell James A. Deskewing data in a buffer
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US7339995B2 (en) * 2003-12-31 2008-03-04 Intel Corporation Receiver symbol alignment for a serial point to point link
US7631118B2 (en) * 2003-12-31 2009-12-08 Intel Corporation Lane to lane deskewing via non-data symbol processing for a serial point to point link
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KR100788299B1 (en) 2006-12-19 2007-12-27 (재)대구경북과학기술연구원 Serial transmission system sharing differential lanes
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US10778765B2 (en) 2015-07-15 2020-09-15 Cisco Technology, Inc. Bid/ask protocol in scale-out NVMe storage
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Also Published As

Publication number Publication date
KR20030085141A (en) 2003-11-03
AU2002241132A1 (en) 2002-10-08
WO2002078227A2 (en) 2002-10-03
TW581960B (en) 2004-04-01
US20020138675A1 (en) 2002-09-26
US6625675B2 (en) 2003-09-23

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