WO2002080287A3 - Semiconductor structures and devices for detecting far-infrared light - Google Patents

Semiconductor structures and devices for detecting far-infrared light Download PDF

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Publication number
WO2002080287A3
WO2002080287A3 PCT/US2001/048088 US0148088W WO02080287A3 WO 2002080287 A3 WO2002080287 A3 WO 2002080287A3 US 0148088 W US0148088 W US 0148088W WO 02080287 A3 WO02080287 A3 WO 02080287A3
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WO
WIPO (PCT)
Prior art keywords
monocrystalline
oxide layer
layer
quality
silicon wafer
Prior art date
Application number
PCT/US2001/048088
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French (fr)
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WO2002080287A2 (en
Inventor
Ravindranath Droopad
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Motorola Inc
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Publication date
Application filed by Motorola Inc filed Critical Motorola Inc
Publication of WO2002080287A2 publication Critical patent/WO2002080287A2/en
Publication of WO2002080287A3 publication Critical patent/WO2002080287A3/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/184—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof the active layers comprising only AIIIBV compounds, e.g. GaAs, InP
    • H01L31/1852—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof the active layers comprising only AIIIBV compounds, e.g. GaAs, InP comprising a growth substrate not being an AIIIBV compound
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02488—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
    • H01L21/02496—Layer structure
    • H01L21/02505—Layer structure consisting of more than two layers
    • H01L21/02507—Alternating layers, e.g. superlattice
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
    • H01L21/02496—Layer structure
    • H01L21/0251—Graded layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/1828—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof the active layers comprising only AIIBVI compounds, e.g. CdS, ZnS, CdTe
    • H01L31/1836—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof the active layers comprising only AIIBVI compounds, e.g. CdS, ZnS, CdTe comprising a growth substrate not being an AIIBVI compound
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/544—Solar cells from Group III-V materials
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Abstract

High-quality epitaxial layers of narrow-bandgap monocrystalline semiconductor materials can be grown overlying monocrystalline substrates (22), such as large silicon wafers, by forming a compliant substrate for growing the monocrystalline layers. One way to achieve the formation of a compliant substrate includes first growing a monocrystalline oxide layer (24) on a silicon wafer. The oxide layer may be spaced apart from the silicon wafer by an amorphous interface layer (28) of silicon oxide. The amorphous interface layer (28) dissipates strain and permits the growth of a high-quality monocrystalline oxide layer. The oxide layer (24) is lattice-matched to both the underlying silicon wafer and the overlying monocrystalline semiconductor material layer (26). Any lattice mismatch between the oxide layer (24) and the underlying silicon substrate (22) is relieved by the amorphous interface layer (28). Optical structures, such as far-infrared detectors and emitters, can be grown on high-quality, epitaxial, narrow-bandgap compound semiconductor materials to create highly reliable devices at reduced costs.
PCT/US2001/048088 2001-03-30 2001-12-10 Semiconductor structures and devices for detecting far-infrared light WO2002080287A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/822,499 US20020140012A1 (en) 2001-03-30 2001-03-30 Semiconductor structures and devices for detecting far-infrared light and methods for fabricating same
US09/822,499 2001-03-30

Publications (2)

Publication Number Publication Date
WO2002080287A2 WO2002080287A2 (en) 2002-10-10
WO2002080287A3 true WO2002080287A3 (en) 2004-02-19

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2001/048088 WO2002080287A2 (en) 2001-03-30 2001-12-10 Semiconductor structures and devices for detecting far-infrared light

Country Status (2)

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US (1) US20020140012A1 (en)
WO (1) WO2002080287A2 (en)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020030246A1 (en) * 2000-06-28 2002-03-14 Motorola, Inc. Structure and method for fabricating semiconductor structures and devices not lattice matched to the substrate
US6709989B2 (en) 2001-06-21 2004-03-23 Motorola, Inc. Method for fabricating a semiconductor structure including a metal oxide interface with silicon
US6693298B2 (en) 2001-07-20 2004-02-17 Motorola, Inc. Structure and method for fabricating epitaxial semiconductor on insulator (SOI) structures and devices utilizing the formation of a compliant substrate for materials used to form same
US7019332B2 (en) * 2001-07-20 2006-03-28 Freescale Semiconductor, Inc. Fabrication of a wavelength locker within a semiconductor structure
US20040069991A1 (en) * 2002-10-10 2004-04-15 Motorola, Inc. Perovskite cuprate electronic device structure and process
US6806202B2 (en) 2002-12-03 2004-10-19 Motorola, Inc. Method of removing silicon oxide from a surface of a substrate
GB2396481A (en) * 2002-12-18 2004-06-23 Qinetiq Ltd Laser annealing method and device
EP1856721A2 (en) * 2005-03-11 2007-11-21 The Arizona Board of Regents, A Body Corporate Acting on Behalf of Arizona State University NOVEL GeSiSn-BASED COMPOUNDS, TEMPLATES, AND SEMICONDUCTOR STRUCTURES
US9466741B2 (en) * 2008-12-16 2016-10-11 California Institute Of Technology Digital alloy absorber for photodetectors
GB2469451A (en) * 2009-04-14 2010-10-20 Qinetiq Ltd P-Type Semiconductor Devices
US8686471B2 (en) 2011-04-28 2014-04-01 Drs Rsta, Inc. Minority carrier based HgCdTe infrared detectors and arrays
JP2014236067A (en) * 2013-05-31 2014-12-15 住友電気工業株式会社 Semiconductor element and manufacturing method of the same
US9324900B2 (en) * 2013-08-01 2016-04-26 Teledyne Scientific & Imaging, Llc Method of fabricating a superlattice structure
US10411146B1 (en) 2017-01-06 2019-09-10 United States Of America As Represented By The Secretary Of The Air Force High absorption infrared superlattices

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5838053A (en) * 1996-09-19 1998-11-17 Raytheon Ti Systems, Inc. Method of forming a cadmium telluride/silicon structure
US6023082A (en) * 1996-08-05 2000-02-08 Lockheed Martin Energy Research Corporation Strain-based control of crystal anisotropy for perovskite oxides on semiconductor-based material
US6045626A (en) * 1997-07-11 2000-04-04 Tdk Corporation Substrate structures for electronic devices
EP1043426A1 (en) * 1999-03-22 2000-10-11 Motorola, Inc. Method for fabricating a semiconductor structure having a single atomic layer with alkaline earth metal metal, oxygen and silicon at the interface between a silicon substrate and a single crystal oxide layer
WO2001059814A2 (en) * 2000-02-10 2001-08-16 Motorola, Inc. Semiconductor structure

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6023082A (en) * 1996-08-05 2000-02-08 Lockheed Martin Energy Research Corporation Strain-based control of crystal anisotropy for perovskite oxides on semiconductor-based material
US5838053A (en) * 1996-09-19 1998-11-17 Raytheon Ti Systems, Inc. Method of forming a cadmium telluride/silicon structure
US6045626A (en) * 1997-07-11 2000-04-04 Tdk Corporation Substrate structures for electronic devices
EP1043426A1 (en) * 1999-03-22 2000-10-11 Motorola, Inc. Method for fabricating a semiconductor structure having a single atomic layer with alkaline earth metal metal, oxygen and silicon at the interface between a silicon substrate and a single crystal oxide layer
WO2001059814A2 (en) * 2000-02-10 2001-08-16 Motorola, Inc. Semiconductor structure

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
R. DROOPAD ET AL: "Epitaxial oxide films on silicon: growth, modeling and device properties", MAT. RES. SOC. SYMP. PROC., vol. 619, pages 155 - 165, XP002235069 *

Also Published As

Publication number Publication date
US20020140012A1 (en) 2002-10-03
WO2002080287A2 (en) 2002-10-10

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