WO2002091437A3 - Tisin barrier formation with treatment in n2/h2 plasma and in silane - Google Patents
Tisin barrier formation with treatment in n2/h2 plasma and in silane Download PDFInfo
- Publication number
- WO2002091437A3 WO2002091437A3 PCT/US2002/014056 US0214056W WO02091437A3 WO 2002091437 A3 WO2002091437 A3 WO 2002091437A3 US 0214056 W US0214056 W US 0214056W WO 02091437 A3 WO02091437 A3 WO 02091437A3
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- titanium nitride
- plasma
- silicon
- nitride layer
- titanium
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
- H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76855—After-treatment introducing at least one additional element into the layer
- H01L21/76856—After-treatment introducing at least one additional element into the layer by treatment in plasmas or gaseous environments, e.g. nitriding a refractory metal liner
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76861—Post-treatment or after-treatment not introducing additional chemical elements into the layer
- H01L21/76862—Bombardment with particles, e.g. treatment in noble gas plasmas; UV irradiation
Abstract
The present invention provides a method of forming a titanium silicon nitride barrier layer on a semiconductor wafer, comprising the steps of depositing a titanium nitride layer on the semiconductor wafer; plasma-treating the titanium nitride layer in a N2/H2 plasma; and exposing the plasma-treated titanium nitride layer to a silane ambient, wherein silicon is incorporated into the titanium nitride layer as silicon nitride thereby forming a titanium silicon nitride barrier layer. Additionally, there is provided a method of improving the barrier performance of a titanium nitride layer comprising the step of introducing silicon into the titanium nitride layer such that the silicon is incorporated into the titanium nitride layer as silicon nitride. Also provided is a method of integrating copper into a semiconductor device and a method of improving copper wettability at a copper/titanium nitride interface in a semiconductor device.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/851,519 | 2001-05-07 | ||
US09/851,519 US6596643B2 (en) | 2001-05-07 | 2001-05-07 | CVD TiSiN barrier for copper integration |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2002091437A2 WO2002091437A2 (en) | 2002-11-14 |
WO2002091437A3 true WO2002091437A3 (en) | 2003-03-20 |
Family
ID=25310972
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US2002/014056 WO2002091437A2 (en) | 2001-05-07 | 2002-05-06 | Tisin barrier formation with treatment in n2/h2 plasma and in silane |
Country Status (2)
Country | Link |
---|---|
US (2) | US6596643B2 (en) |
WO (1) | WO2002091437A2 (en) |
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US20030022507A1 (en) | 2003-01-30 |
US20040197492A1 (en) | 2004-10-07 |
WO2002091437A2 (en) | 2002-11-14 |
US6596643B2 (en) | 2003-07-22 |
US6958296B2 (en) | 2005-10-25 |
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