WO2002093858A1 - Multiple bandwidth amplifier control systems for mobile stations and methods therefor - Google Patents
Multiple bandwidth amplifier control systems for mobile stations and methods therefor Download PDFInfo
- Publication number
- WO2002093858A1 WO2002093858A1 PCT/US2002/012247 US0212247W WO02093858A1 WO 2002093858 A1 WO2002093858 A1 WO 2002093858A1 US 0212247 W US0212247 W US 0212247W WO 02093858 A1 WO02093858 A1 WO 02093858A1
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- WO
- WIPO (PCT)
- Prior art keywords
- amplifier
- output
- control circuit
- input
- reference signal
- Prior art date
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Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/38—Dc amplifiers with modulator at input and demodulator at output; Modulators or demodulators specially adapted for use in such amplifiers
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03G—CONTROL OF AMPLIFICATION
- H03G3/00—Gain control in amplifiers or frequency changers without distortion of the input signal
- H03G3/20—Automatic control
- H03G3/30—Automatic control in amplifiers having semiconductor devices
- H03G3/3036—Automatic control in amplifiers having semiconductor devices in high-frequency amplifiers or in frequency-changers
- H03G3/3042—Automatic control in amplifiers having semiconductor devices in high-frequency amplifiers or in frequency-changers in modulators, frequency-changers, transmitters or power amplifiers
- H03G3/3047—Automatic control in amplifiers having semiconductor devices in high-frequency amplifiers or in frequency-changers in modulators, frequency-changers, transmitters or power amplifiers for intermittent signals, e.g. burst signals
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03G—CONTROL OF AMPLIFICATION
- H03G1/00—Details of arrangements for controlling amplification
- H03G1/0005—Circuits characterised by the type of controlling devices operated by a controlling current or voltage signal
- H03G1/0088—Circuits characterised by the type of controlling devices operated by a controlling current or voltage signal using discontinuously variable devices, e.g. switch-operated
Definitions
- the present inventions relate generally to control systems, and more particularly to control circuits for transmitters in mobile communication devices, combinations thereof and methods therefor.
- the peak detect circuit output is filtered and converted to a digital format before being input to a processor, which provides an output control signal based on a comparison of the digitized input signal with a reference signal.
- digital control circuits control the amplifier in a manner that tends to match the digitized peak-detect circuit signal with the reference signal.
- Digital processing runs generally at a slower rate than the modulation rate of the peak-detect circuit signal so that variation of the envelope is tracked poorly or not tracked at all.
- Another limitation of known digital control circuits is that a D/ A converter at the output of the processor is written initially with an estimated value, which requires knowledge of gain at the start of the transmit sequence for acceptable performance. The estimated value moreover is susceptible to variations in temperature, voltage, load and other conditions.
- FIG. 1 is an analog implementation of a control circuit according to a first exemplary embodiment of the invention.
- FIG. 2 is a look up table for storing estimation mode operation reference signals for different output power levels.
- FIG. 3 is an exemplary TDMA transmitter having a digital control circuit.
- FIG. 4 is a timing signal diagram illustrating TDMA burst operation according to an exemplary embodiment of the invention.
- FIG. 5 is an exemplary EDGE transmitter having a digital control circuit.
- FIG. 6 is a timing signal diagram illustrating EDGE burst operation according to an exemplary embodiment of the invention.
- FIG. 7 is an exemplary GSM transmitter having a digital control circuit.
- FIG. 8 is a timing signal diagram illustrating GSM burst operation according to an exemplary embodiment of the invention.
- FIG. 1 is an exemplary RF amplifier and control circuit 100 comprising generally an amplifier 110 and a vector modulator 120 having an output coupled to an input of the amplifier by an RF modulator 130, which converts vector modulation from the modulator to the RF operating frequency of the amplifier.
- the amplifier 110 includes generally a control input and may comprise a chain or several stages as is known in the art.
- the control circuit also comprises generally a proportional control circuit and an integral control circuit.
- the proportional control circuit includes an input coupled to a first reference signal source and an output coupled to the control input of the amplifier.
- the integral control circuit integrates an output of the amplifier relative to a reference signal and includes an integrator control signal output coupled to the control input of the amplifier.
- an op-amp 140 having an output coupled to the control input of the amplifier 110 is configurable as a unity gain buffer circuit and as an integrator circuit, which constitute the proportional and integral control circuits, respectively.
- the output of the amplifier is coupled generally to an input of the op-amp 140, for example by a non-linear device.
- a peak-detect circuit 150 interconnects the amplifier output to the op-amp input.
- the proportional control circuit applies an initial control signal to the control input of the amplifier by applying a first reference signal to the proportional gain control circuit.
- the reference signal applied to the proportional control circuit is an estimate of the value required at the integral control circuit output (or the control input of the amplifier) for the amplifier output to achieve its desired output power when the vector modulator is at its full output level.
- the actual power output during estimation is relatively low since the vector modulator output is low, as discussed below.
- estimation mode the vector modulator 120 is not at full output and may or may not be active. Depending on the modulation format, the vector modulator output may be zero or may be vacillating between zero and low level outputs. This latter condition is common of a root raised cosine response vector modulator in the time before the modulator output ramps up to full power.
- estimation mode reference signal values for corresponding amplifier power outputs are preprogrammed and stored in memory, for example in a look-up table or in a Radio Logic Unit as illustrated in FIG. 2. In some applications, the estimation mode reference signal levels are also obtained for particular output power levels by sampling the output of the integral control circuit after a subsequent ramping mode of operation, discussed below.
- the op-amp is configured as the unity gain buffer by closing switch SW1 so that the op-amp output will follow the reference signal applied to the positive input thereof.
- switches SW2, SW3 and SW4 are also closed.
- a magnitude block 160 of a base band processor generates the estimation mode reference signal Vref equal to Vest, which is input to the op-amp gain circuit.
- the switches SW1, SW2, SW3 and SW4 and the baseband processor are controlled by a processor 170.
- the filter is at the positive input of the op-amp 140 and comprises resistor Rpl and capacitance Cp.
- This typical estimation mode RC time constant value is exemplary only and is not intended to limit the invention.
- the estimation mode lasts generally for a sufficient time interval required for the proportional control circuit to reach steady state. In one embodiment, the estimation mode time period lasts for approximately 5 RC estimation mode time constants, although it may be more or less. After estimation mode, the output of the vector modulator 120 is ramped upwardly to its full output power in ramping mode.
- the initial control signal applied to the amplifier during estimation mode is corrected by integrating an output of the amplifier relative to a second reference signal.
- the second reference signal is generally proportional to the ramping output of the vector modulator and may be scaled for the desired output power.
- ramping mode begins by opening switches SW1 and SW2 and configuring the magnitude block 160 to generate a reference signal Vref proportional to the ramping output of the vector modulator.
- the op-amp 140 is configured as an integrator.
- the RC time constant during ramping mode is generally greater than the RC time constant during Estimation Mode. Generally, Ramping Mode lasts longer than Estimation Mode. In one embodiment, the feedback capacitance Cm is equal to Cp and Rml is equal to (Rpl + Rp2).
- the exemplary Ramping Mode RC time constant is approximately 0.7Ts, which is slower than the exemplary RC time constant, 0.2Ts, of the estimation mode. In one embodiment, the ramping mode lasts for approximately 3 to 3.5 Ts.
- the reference signal and the amplifier output are phase matched by delaying the reference signal applied to the integral control circuit with a delay means 162.
- the delay means 162 may be a delay circuit or software controlled delay of the signal.
- the reference signal, Vref increases in proportion to the ramping output of the vector modulator, scaled by whatever the desired output power should be as represented by the time average of the detected amplifier output signal.
- Ramping mode generally lasts long enough to allow transients to settle out by the end of the ramping mode. If the reference signal, Vest, during estimation mode is exactly correct and if the peak-detect signal is a perfect representation of the amplifier output power, the reference signal and peak detect output track each other perfectly. Under these circumstances, the inputs at the integrator op-amp 140 are the same throughout the ramping mode (Vref and the peak detect voltage are tracking perfectly and the time constants are the same) and the integrator output voltage remains the same as the estimation output applied to the amplifier control input. The control circuit will correct the amplifier output to the extent that the estimated output is incorrect without inducing transients.
- the transient out-of-band power spectrum is controlled by the bandwidth of the integral control circuit.
- the bandwidth of the integral control circuit during ramping mode is reduced relative to the bandwidth of the proportional control circuit during estimation mode. If the ramping mode bandwidth is too low, however, the integral control circuit will not be sufficiently responsive. Thus there is a trade off between transient out of band power spectrum control and integral control circuit responsiveness.
- the control circuit After ramping mode, the control circuit operates in a "Modulation Mode".
- modulation mode the corrected control signal, which may or may not have been corrected during ramping mode depending on the accuracy of the estimation value, applied to the amplifier is maintained by applying a third reference signal to the integral control circuit.
- the third reference signal is generally proportional to an averaged output of the amplifier.
- the integral control circuit in modulation mode, is configured to have a bandwidth that is less than the bandwidth thereof during ramping mode. In modulation mode, the integral control circuit corrects slow phenomenon such as supply line droop and thermal gain variations, but modulation variations are tracked poorly or at not all.
- the switches SW3 and SW4 are opened.
- the reference signal Vref generated by the magnitude block 160 and applied to the input of op-amp 140 is based on or proportional to the average peak detector output for the desired amplifier power output.
- the magnitude block ignores inputs from
- a typical integral gain circuit RC time constant for modulation mode is between approximately 40 and 400 Ts.
- the switches SW3 and SW4 are controlled by the processor 170.
- modulation ends periodically.
- the vector modulator is allowed to ramp down naturally when modulation ends.
- the relatively slow bandwidth of the integral control circuit in modulation mode will not react to the relatively rapid power reduction.
- the control circuit may be disabled upon ramping down the vector modulation without spectral considerations.
- the amplifier control circuits of the present invention may also be implemented with digital circuit elements.
- the exemplary embodiment of FIG. 3 is a portion of a mobile TDMA communications device having a transmitter 300 with a digital control system comprising generally an interface 310 that transmits digital vector modulation signals I/Q from a baseband processor to a digital I/Q processing circuit 312 coupled to an amplifier circuit 314 by analog reconstruction filters 313.
- a digital proportional control circuit comprising shift registers 320 provides stability.
- a digital integral control circuit comprises shift registers 330 and accumulator 332. In the digital implementation, during the estimation mode, the initial control signal is loaded directly into the register output of the accumulator.
- the output of the peak detect circuit 340 is processed with analog processing circuitry 350 and then digitized by an A/D converter 360.
- the interface 310 provides digital reference signals via a register 316 from the baseband processor to the proportional control circuit and the integral control circuit.
- the register 316 delays at least some of the reference signals to the proportional and integral control circuits.
- the digitized output of the peak detection circuit 340 is summed with the digital reference signals provided by the baseband processor to provide an error signal to the integral control circuit.
- the register 334 is not required for the TDMA format and provides a tolerable delay.
- the outputs of the proportional and integral control circuits are processed and converted by a processing and D/A circuit 370.
- the resulting analog control signal is processed by an analog processing circuit 380 before coupling to the control input of the amplifier circuit 314.
- FIG. 4 illustrates a timing diagram for an exemplary IS-136
- TDMA estimation mode operation begins with the rising edge of a DMCS signal. After a delay interval set by PAC_DLY, the detected RF output voltage is reduced by a residual offset. At this point there is no amplifier output.
- a RAMP_DLY signal is set to align the Ramp waveform with the modulated RF waveform.
- a delay INITJDLY sets the point at which the accumulator, and thus the AOC D/A of FIG. 3, are set at the estimated value of ACCJNIT.
- the control output to the amplifier is smoothed by the digital filter on the AOC D/A input 370 and the analog filter 380 on the AOC D/A output and thus does not contain discontinuities shown for the accumulator output.
- the amplifier output will be proportional to the detected voltage.
- the TDMA ramping mode begins and the input to the accumulator is switched to the error between the detected signal and the ramping waveform.
- the integral control circuit loop is closed and configured with a first bandwidth setting of ERRGainl.
- the digital filter on the D/A input is bypassed at this time, since it is no longer required for bandwidth control and may compromise loop stability.
- the value of the output register 334 is stored when CDETJDLY expires at or just before the end of the ramping mode for subsequent TDMA bursts.
- TDMA modulation mode begins upon expiration of time interval BW_DLY.
- the integral control circuit is configured with a bandwidth setting of ERRGain2.
- thaDMCS signal goes low to signify the end of the I/Q data.
- DN_DLY After a delay DN_DLY, the AOC section 370 in FIG. 3 is powered down. This example assumes zero delay, thus DN_DLY is shown as zero. In practice,
- DMCS will fall prior to DN_DLY expiring.
- FIG. 5 is a portion of a mobile EDGE communications device having a transmitter 500 with a digital control system comprising generally a phase map output 510 that transmits digital vector modulation signals from a baseband processor to a digital I/Q processing circuit 512 to the amplifier circuit 514 via analog reconstruction filters 513.
- a digital proportional control circuit comprising shift registers 520 provides stability.
- a digital integral control circuit comprises shift registers 530 and accumulator 532.
- the initial control signal is loaded directly into the register output of the accumulator.
- the output of the peak detect circuit 540 is processed with analog processing circuitry 550 and then digitized with an A/D converter 560.
- reference signals are provided to the proportional control circuit and the integral control circuit under control of a baseband processor.
- the ramping values are stored in a table 516 and are scaled by a factor, PWR, for the desired power output. This is possible because in the EDGE format, the ramping values are not data dependent. Each transmission may thus use the same ramp-up pattern.
- the digitized output of the peak detection circuit 540 is summed with the digital reference signals provided by the baseband processor to provide an error signal to the integral control circuit.
- the digital outputs of the proportional 'and integral control circuits are converted to analog form by a D/A circuit 570.
- the resulting analog control signal is also processed by an analog processing circuit 580 before coupling to the control input of the amplifier circuit 514.
- FIG. 6 illustrates a timing diagram for an exemplary EDGE application with the operating modes discussed above.
- EDGE estimation mode operation begins with the rising edge of a DMCS signal. After a delay interval set by PAC_DLY, the detected RF output voltage is reduced by a residual offset. At this point there is no amplifier output.
- a RAMP_DLY signal is set to align the Ramp waveform with the modulated RF waveform.
- a delay INIT_DLY sets the point at which the accumulator and thus the AOC D/A of FIG. 5 are set at the estimated value of ACCJNIT.
- the control output to the amplifier is smoothed by the analog filter
- the amplifier output will be proportional to the detected voltage.
- the EDGE ramping mode begins and the input to the accumulator is switched to the error signal between the detected signal and the ramping waveform.
- RAMP_DLY to permit suppression of leading low-resolution signals
- the Ramp signal begins.
- the integral control circuit loop configured with a first bandwidth setting of ERRGainl.
- EDGE modulation mode begins upon expiration of time intervals BW_DLY and DIV_DLY.
- the integral control circuit is configured with a bandwidth setting of ERRGain2, which is generally much lower than the TDMA modulation mode bandwidth.
- the value of the output register 534 is stored when CDET_DLY expires for subsequent bursts.
- an output register 534 is held at the expiration of DIV_DLY. This prevents the AOC control circuit from having a detrimental effect on EDGE modulation fidelity. This is equivalent to setting a low bandwidth with ERRGain2. Finally, after the amplifier output falls with I/Q modulation shaping to zero, the DMCS signal goes low to signify the end of the I/Q data. After a delay set by DN_DLY, the
- AOC section 570 in FIG. 5 is powered down. This example assumes zero delay.
- the exemplary embodiment of FIG. 7 is a portion of a mobile
- GSM communications device having a transmitter 700 with a digital control system comprising generally a differential encoder 710 coupled to a digital
- I/Q processing circuit 712 coupled to an amplifier circuit 714 via analog I/Q reconstruction filters 713.
- a digital proportional control circuit comprising shift registers 720 provides stability.
- a digital integral control circuit comprises shift registers 730 and an accumulator 732.
- the initial control signal is loaded directly into the register output of the accumulator.
- the peak detect circuit 740 output is processed with analog processing circuitry 750 and then digitized with an A/D converter 760.
- reference signals are provided to the proportional control circuit 720 and the integral control circuit 730 under control of a baseband processor.
- the ramping values are stored in a table 716 and are scaled by a factor, PWR, for the desired power output. This is possible because in the GSM format, a common ramping pattern is imposed on the modulation for each transmission. This eliminates the need to send the ramping values across the digital interface, as was required in the TDMA implementation of FIG. 3.
- the processed and digitized output of the peak detection circuit 740 is summed with the digital reference signals provided by the baseband processor to provide an error signal to the integral control circuit.
- the register 734 is not required for the GSM format and provides a tolerable delay.
- the outputs of the proportional and integral control circuits are processed and converted by a processor and D/A circuit 770.
- the analog control signal is also processed by an analog processing circuit 780 before coupling to the control input of the amplifier circuit 714.
- the data, which includes phase information in GSM format, loaded by the circuit 710 and the I/Q Ramp Up signal, which includes amplitude information, are synchronized with each other and with the AOC
- FIG. 8 illustrates a timing diagram for an exemplary GSM application with the operating modes discussed above.
- GSM estimation mode operation begins with the rising edge of a DMCS signal. After a delay interval set by PAC_DLY, the detected RF output voltage is reduced by a residual offset. At this point there is no amplifier output. Next, a delay
- INIT_DLY sets the point at which the accumulator and thus the AOC D/A of FIG. 8 are set at the estimated value of ACC NIT.
- control output to the amplifier is smoothed by the analog filter 780 on the AOC D/A output and thus does not contain discontinuities shown for the accumulator output.
- the amplifier output will be proportional to the detected voltage.
- the GSM ramping mode begins and the input to the accumulator is switched to the error between the detected signal and the ramping waveform.
- the Ramp signal begins.
- G_IQ_DLY expires at approximately the same time so that RF input rises with the ramping waveform, since both look-up tables are defined by the same function.
- the integral control circuit loop is closed and configured with a first bandwidth setting of ERRGainl.
- GSM modulation mode begins upon expiration of time interval BW_DLY.
- the integral control circuit is configured with a bandwidth setting of ERRGain2.
- the value of the output register is stored when CDET_DLY expires.
- DIV_DLY Upon expiration of a delay DIV_DLY, the integral control circuit enters a hold mode just before modulation ends.
- the DMCS signal goes low to signify the end of the I/Q data.
- RAMP_DN_DLY is shown as zero in the diagram since zero delay is assumed. In practice, it will occur somewhere after the falling edge of the DMCS because of system delays.
Abstract
Description
Claims
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN028099664A CN1509554B (en) | 2001-05-14 | 2002-04-18 | Amplifier control circuit and method, and wireless communication device |
KR1020037014836A KR100577652B1 (en) | 2001-05-14 | 2002-04-18 | Multiple bandwidth amplifier control system for mobile stations and methods therefor |
GB0327505A GB2396067B (en) | 2001-05-14 | 2002-04-18 | Multiple bandwith amplifier control systems for mobile stations and methods therefor |
JP2002590606A JP2004533764A (en) | 2001-05-14 | 2002-04-18 | Multi-bandwidth amplifier control system and method for mobile station |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/854,858 US6850574B2 (en) | 2001-05-14 | 2001-05-14 | Multiple bandwidth amplifier control systems for mobile stations and methods therefor |
US09/854,858 | 2001-05-14 |
Publications (1)
Publication Number | Publication Date |
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WO2002093858A1 true WO2002093858A1 (en) | 2002-11-21 |
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ID=25319705
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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PCT/US2002/012247 WO2002093858A1 (en) | 2001-05-14 | 2002-04-18 | Multiple bandwidth amplifier control systems for mobile stations and methods therefor |
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US (1) | US6850574B2 (en) |
JP (1) | JP2004533764A (en) |
KR (1) | KR100577652B1 (en) |
CN (1) | CN1509554B (en) |
GB (1) | GB2396067B (en) |
TW (1) | TW595125B (en) |
WO (1) | WO2002093858A1 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7706467B2 (en) | 2004-12-17 | 2010-04-27 | Andrew Llc | Transmitter with an envelope tracking power amplifier utilizing digital predistortion of the signal envelope |
Families Citing this family (33)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE10124179A1 (en) * | 2001-05-17 | 2002-07-25 | Infineon Technologies Ag | Controller for output power for mobile radio appts. with at least one HF component |
US6828859B2 (en) * | 2001-08-17 | 2004-12-07 | Silicon Laboratories, Inc. | Method and apparatus for protecting devices in an RF power amplifier |
US6741840B2 (en) * | 2002-03-13 | 2004-05-25 | Motorola, Inc. | RF transmitters with saturation detection and correction and methods therefor |
GB2412512B (en) * | 2002-05-31 | 2005-11-16 | Renesas Tech Corp | A communication semiconductor integrated circuit, a wireless communication apparatus, and a loop gain calibration method |
US7729668B2 (en) * | 2003-04-03 | 2010-06-01 | Andrew Llc | Independence between paths that predistort for memory and memory-less distortion in power amplifiers |
US7010057B2 (en) * | 2003-09-04 | 2006-03-07 | Nokia Corporation | Dual mode multi-slot EGPRS transmitter |
US7327803B2 (en) | 2004-10-22 | 2008-02-05 | Parkervision, Inc. | Systems and methods for vector power amplification |
US7355470B2 (en) | 2006-04-24 | 2008-04-08 | Parkervision, Inc. | Systems and methods of RF power transmission, modulation, and amplification, including embodiments for amplifier class transitioning |
US7148749B2 (en) * | 2005-01-31 | 2006-12-12 | Freescale Semiconductor, Inc. | Closed loop power control with high dynamic range |
FR2884659B1 (en) * | 2005-04-18 | 2007-07-13 | Siemens Vdo Automotive Sas | DEVICE FOR AUTOMATICALLY CONTROLLING THE GAIN OF A SIGNAL AMPLIFIER AND AMPLIFIER PROVIDED WITH SUCH A DEVICE |
US7911272B2 (en) | 2007-06-19 | 2011-03-22 | Parkervision, Inc. | Systems and methods of RF power transmission, modulation, and amplification, including blended control embodiments |
US8334722B2 (en) | 2007-06-28 | 2012-12-18 | Parkervision, Inc. | Systems and methods of RF power transmission, modulation and amplification |
US9106316B2 (en) | 2005-10-24 | 2015-08-11 | Parkervision, Inc. | Systems and methods of RF power transmission, modulation, and amplification |
US20070223621A1 (en) * | 2006-03-21 | 2007-09-27 | M/A-Com, Inc. | Method and apparatus for signal power ramp-up in a communication transmission |
US8031804B2 (en) | 2006-04-24 | 2011-10-04 | Parkervision, Inc. | Systems and methods of RF tower transmission, modulation, and amplification, including embodiments for compensating for waveform distortion |
US7937106B2 (en) | 2006-04-24 | 2011-05-03 | ParkerVision, Inc, | Systems and methods of RF power transmission, modulation, and amplification, including architectural embodiments of same |
US7570931B2 (en) * | 2006-06-02 | 2009-08-04 | Crestcom, Inc. | RF transmitter with variably biased RF power amplifier and method therefor |
JP4791271B2 (en) * | 2006-06-28 | 2011-10-12 | 富士通株式会社 | Amplifier control device |
US7889810B2 (en) * | 2006-12-15 | 2011-02-15 | Pine Valley Investments, Inc. | Method and apparatus for a nonlinear feedback control system |
US8009765B2 (en) * | 2007-03-13 | 2011-08-30 | Pine Valley Investments, Inc. | Digital polar transmitter |
US7869543B2 (en) * | 2007-03-13 | 2011-01-11 | Pine Valley Investments, Inc. | System and method for synchronization, power control, calibration, and modulation in communication transmitters |
WO2008144017A1 (en) | 2007-05-18 | 2008-11-27 | Parkervision, Inc. | Systems and methods of rf power transmission, modulation, and amplification |
WO2008156800A1 (en) | 2007-06-19 | 2008-12-24 | Parkervision, Inc. | Combiner-less multiple input single output (miso) amplification with blended control |
US8081710B2 (en) * | 2007-11-08 | 2011-12-20 | Pine Valley Investments, Inc. | System and method for corrected modulation with nonlinear power amplification |
US7983359B2 (en) * | 2008-02-07 | 2011-07-19 | Pine Valley Investments, Inc. | Synchronization techniques for polar transmitters |
US8064851B2 (en) * | 2008-03-06 | 2011-11-22 | Crestcom, Inc. | RF transmitter with bias-signal-induced distortion compensation and method therefor |
US8233852B2 (en) * | 2008-04-04 | 2012-07-31 | Pine Valley Investments, Inc. | Calibration techniques for non-linear devices |
KR101486075B1 (en) * | 2008-06-30 | 2015-01-23 | 삼성전자주식회사 | Mobile telecommunication device having shrink memory and ramping data sending method therefore |
EP2695294A1 (en) | 2011-04-08 | 2014-02-12 | Parkervision, Inc. | Systems and methods of rf power transmission, modulation, and amplification |
WO2012167111A2 (en) | 2011-06-02 | 2012-12-06 | Parkervision, Inc. | Antenna control |
KR20160058855A (en) | 2013-09-17 | 2016-05-25 | 파커비전, 인크. | Method, apparatus and system for rendering an information bearing function of time |
CN110417366A (en) * | 2019-08-20 | 2019-11-05 | 上海联影医疗科技有限公司 | Radio-frequency power amplifier control device and radio-frequency power amplifier |
CN110888481B (en) * | 2019-11-07 | 2022-04-12 | 深南电路股份有限公司 | Output voltage adjustable circuit, control method of output voltage adjustable circuit and chip |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5838210A (en) * | 1997-12-01 | 1998-11-17 | Motorola, Inc. | Method and apparatus for generating a modulated signal |
US6225864B1 (en) * | 1999-11-02 | 2001-05-01 | Harris Corporation | RF amplifier having a dual slope phase modulator |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4458209A (en) | 1981-02-03 | 1984-07-03 | Motorola, Inc. | Adaptive power control circuit |
US5287555A (en) * | 1991-07-22 | 1994-02-15 | Motorola, Inc. | Power control circuitry for a TDMA radio frequency transmitter |
JP2966226B2 (en) | 1993-02-17 | 1999-10-25 | 三菱電機株式会社 | Automatic power amplifier control circuit |
JP2924644B2 (en) | 1994-06-15 | 1999-07-26 | 三菱電機株式会社 | Transmission power control circuit, base station, mobile station, and mobile communication system |
US5697074A (en) * | 1995-03-30 | 1997-12-09 | Nokia Mobile Phones Limited | Dual rate power control loop for a transmitter |
US6078216A (en) * | 1998-03-31 | 2000-06-20 | Spectrian Corporation | Aliased wide band performance monitor for adjusting predistortion and vector modulator control parameters of RF amplifier |
US6295442B1 (en) * | 1998-12-07 | 2001-09-25 | Ericsson Inc. | Amplitude modulation to phase modulation cancellation method in an RF amplifier |
-
2001
- 2001-05-14 US US09/854,858 patent/US6850574B2/en not_active Expired - Lifetime
-
2002
- 2002-04-18 JP JP2002590606A patent/JP2004533764A/en not_active Ceased
- 2002-04-18 GB GB0327505A patent/GB2396067B/en not_active Expired - Lifetime
- 2002-04-18 WO PCT/US2002/012247 patent/WO2002093858A1/en active Application Filing
- 2002-04-18 KR KR1020037014836A patent/KR100577652B1/en active IP Right Grant
- 2002-04-18 CN CN028099664A patent/CN1509554B/en not_active Expired - Lifetime
- 2002-05-07 TW TW091109455A patent/TW595125B/en not_active IP Right Cessation
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5838210A (en) * | 1997-12-01 | 1998-11-17 | Motorola, Inc. | Method and apparatus for generating a modulated signal |
US6225864B1 (en) * | 1999-11-02 | 2001-05-01 | Harris Corporation | RF amplifier having a dual slope phase modulator |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7706467B2 (en) | 2004-12-17 | 2010-04-27 | Andrew Llc | Transmitter with an envelope tracking power amplifier utilizing digital predistortion of the signal envelope |
Also Published As
Publication number | Publication date |
---|---|
TW595125B (en) | 2004-06-21 |
KR20040004625A (en) | 2004-01-13 |
US20020168025A1 (en) | 2002-11-14 |
JP2004533764A (en) | 2004-11-04 |
CN1509554A (en) | 2004-06-30 |
US6850574B2 (en) | 2005-02-01 |
GB2396067B (en) | 2005-04-20 |
GB2396067A (en) | 2004-06-09 |
KR100577652B1 (en) | 2006-05-10 |
GB0327505D0 (en) | 2003-12-31 |
CN1509554B (en) | 2012-06-06 |
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