WO2002097891A3 - Dram-zellenanordnung mit vertikalen mos-transistoren und verfahren zu deren herstellung - Google Patents

Dram-zellenanordnung mit vertikalen mos-transistoren und verfahren zu deren herstellung Download PDF

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Publication number
WO2002097891A3
WO2002097891A3 PCT/EP2002/005651 EP0205651W WO02097891A3 WO 2002097891 A3 WO2002097891 A3 WO 2002097891A3 EP 0205651 W EP0205651 W EP 0205651W WO 02097891 A3 WO02097891 A3 WO 02097891A3
Authority
WO
WIPO (PCT)
Prior art keywords
mos transistors
production
cell arrangement
dram cell
vertical mos
Prior art date
Application number
PCT/EP2002/005651
Other languages
English (en)
French (fr)
Other versions
WO2002097891A2 (de
Inventor
Brian Lee
Till Schloesser
Original Assignee
Infineon Technologies Ag
Brian Lee
Till Schloesser
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies Ag, Brian Lee, Till Schloesser filed Critical Infineon Technologies Ag
Priority to KR1020037015568A priority Critical patent/KR100567495B1/ko
Priority to JP2003500975A priority patent/JP2004527920A/ja
Priority to EP02740639A priority patent/EP1396026A2/de
Publication of WO2002097891A2 publication Critical patent/WO2002097891A2/de
Publication of WO2002097891A3 publication Critical patent/WO2002097891A3/de
Priority to US10/720,730 priority patent/US6939763B2/en
Priority to US11/158,439 priority patent/US7329916B2/en

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/036—Making the capacitor or connections thereto the capacitor extending under the transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor
    • H10B12/053—Making the transistor the transistor being at least partially in a trench in the substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor

Abstract

Die entlang einer der Spalten der Speicherzellenmatrix angeordneten Kanalgebiete sind Teile eines Steges, der von einer Gatedielektrikumschicht umgeben ist. Die Gateelektroden der MOS-Transistoren einer Reihe sind Teile einer streifenförmigen Wortleitung, so dass an jedem Kreuzungspunkt der Speicherzellenmatrix ein vertikaler Doppel-Gate-MOS-Transistor mit auf beiden Seiten des zugehörigen Steges in den Gräben gebildeten Gateelektroden der zugehörigen Wortleitung vorgesehen ist.
PCT/EP2002/005651 2001-05-29 2002-05-23 Dram-zellenanordnung mit vertikalen mos-transistoren und verfahren zu deren herstellung WO2002097891A2 (de)

Priority Applications (5)

Application Number Priority Date Filing Date Title
KR1020037015568A KR100567495B1 (ko) 2001-05-29 2002-05-23 종형 ｍｏｓ 트랜지스터를 구비한 ｄｒａｍ 셀 장치 및제조 방법
JP2003500975A JP2004527920A (ja) 2001-05-29 2002-05-23 垂直ｍｏｓトランジスタを有するｄｒａｍセル構成、およびこの構成を製作する方法
EP02740639A EP1396026A2 (de) 2001-05-29 2002-05-23 Dram-zellenanordnung mit vertikalen mos-transistoren und verfahren zu deren herstellung
US10/720,730 US6939763B2 (en) 2001-05-29 2003-11-24 DRAM cell arrangement with vertical MOS transistors, and method for its fabrication
US11/158,439 US7329916B2 (en) 2001-05-29 2005-06-22 DRAM cell arrangement with vertical MOS transistors

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE10125967.0 2001-05-29
DE10125967A DE10125967C1 (de) 2001-05-29 2001-05-29 DRAM-Zellanordnung mit vertikalen MOS-Transistoren und Verfahren zu deren Herstellung

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US10/720,730 Continuation US6939763B2 (en) 2001-05-29 2003-11-24 DRAM cell arrangement with vertical MOS transistors, and method for its fabrication

Publications (2)

Publication Number Publication Date
WO2002097891A2 WO2002097891A2 (de) 2002-12-05
WO2002097891A3 true WO2002097891A3 (de) 2003-10-09

Family

ID=7686407

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/EP2002/005651 WO2002097891A2 (de) 2001-05-29 2002-05-23 Dram-zellenanordnung mit vertikalen mos-transistoren und verfahren zu deren herstellung

Country Status (8)

Country Link
US (2) US6939763B2 (de)
EP (1) EP1396026A2 (de)
JP (1) JP2004527920A (de)
KR (1) KR100567495B1 (de)
CN (1) CN1290198C (de)
DE (1) DE10125967C1 (de)
TW (1) TW569397B (de)
WO (1) WO2002097891A2 (de)

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