WO2002098066A3 - Cell-based switch fabric architecture on a single chip - Google Patents

Cell-based switch fabric architecture on a single chip Download PDF

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Publication number
WO2002098066A3
WO2002098066A3 PCT/CA2002/000810 CA0200810W WO02098066A3 WO 2002098066 A3 WO2002098066 A3 WO 2002098066A3 CA 0200810 W CA0200810 W CA 0200810W WO 02098066 A3 WO02098066 A3 WO 02098066A3
Authority
WO
WIPO (PCT)
Prior art keywords
cell
communication
cells
interface
array
Prior art date
Application number
PCT/CA2002/000810
Other languages
French (fr)
Other versions
WO2002098066A2 (en
Inventor
Richard S Norman
Maria Marcelo De
Sebastien Cote
Carl Langlois
John Haughey
Yves Boudreault
Original Assignee
Hyperchip Inc
Richard S Norman
Maria Marcelo De
Sebastien Cote
Carl Langlois
John Haughey
Yves Boudreault
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US09/870,841 external-priority patent/US7197042B2/en
Priority claimed from US09/870,767 external-priority patent/US6990097B2/en
Priority claimed from US09/870,766 external-priority patent/US6990096B2/en
Priority claimed from US09/870,703 external-priority patent/US20020181453A1/en
Priority claimed from US09/870,800 external-priority patent/US7277429B2/en
Application filed by Hyperchip Inc, Richard S Norman, Maria Marcelo De, Sebastien Cote, Carl Langlois, John Haughey, Yves Boudreault filed Critical Hyperchip Inc
Priority to AU2002302279A priority Critical patent/AU2002302279A1/en
Priority to CA2448978A priority patent/CA2448978C/en
Priority to EP02729739A priority patent/EP1396117A2/en
Publication of WO2002098066A2 publication Critical patent/WO2002098066A2/en
Publication of WO2002098066A3 publication Critical patent/WO2002098066A3/en

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/15—Interconnection of switching modules
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/20—Support for services
    • H04L49/201—Multicast operation; Broadcast operation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/25—Routing or path finding in a switch fabric
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/30—Peripheral units, e.g. input or output ports
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/30—Peripheral units, e.g. input or output ports
    • H04L49/3036—Shared queuing
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/45—Arrangements for providing or supporting expansion

Abstract

A switch fabric implemented on a chip includes an array of cells and an I/O interface in communication with the cells for permitting exchange of data packet between the cells and components external thereto. Each cell includes a transmitter in communication with the I/O interface and in communication with every other cell of the array, the transmitter being operative to process a data packet received from the I/O interface to determine a destination of the packet and forward it to at least one cell of the array selected on a basis of the determined destination. Each cell further includes plural receivers associated with respective cells from the array, each receiver being in communication with a respective cell allowing the respective cell to forward data packets to the receiver, where the receivers are in communication with the I/O interface for releasing data packets thereto. In this way, the transmitter in a given cell functionally extends into those cells where dedicated receivers are located, reducing transmitter memory requirements and allowing the switch fabric to be implemented on a single chip.
PCT/CA2002/000810 2001-06-01 2002-05-31 Cell-based switch fabric architecture on a single chip WO2002098066A2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
AU2002302279A AU2002302279A1 (en) 2001-06-01 2002-05-31 Cell-based switch fabric architecture on a single chip
CA2448978A CA2448978C (en) 2001-06-01 2002-05-31 Cell-based switch fabric architecture
EP02729739A EP1396117A2 (en) 2001-06-01 2002-05-31 Cell-based switch fabric architecture on a single chip

Applications Claiming Priority (10)

Application Number Priority Date Filing Date Title
US09/870,841 US7197042B2 (en) 2001-06-01 2001-06-01 Cell-based switch fabric with cell-to-line-card control for regulating injection of packets
US09/870,767 US6990097B2 (en) 2001-06-01 2001-06-01 Cell-based switch fabric with inter-cell control for regulating packet flow
US09/870,800 2001-06-01
US09/870,766 2001-06-01
US09/870,766 US6990096B2 (en) 2001-06-01 2001-06-01 Cell-based switch fabric architecture implemented on a single chip
US09/870,703 US20020181453A1 (en) 2001-06-01 2001-06-01 Cell-based switch fabric with distributed arbitration
US09/870,767 2001-06-01
US09/870,800 US7277429B2 (en) 2001-06-01 2001-06-01 Cell-based switch fabric with distributed scheduling
US09/870,703 2001-06-01
US09/870,841 2001-06-01

Publications (2)

Publication Number Publication Date
WO2002098066A2 WO2002098066A2 (en) 2002-12-05
WO2002098066A3 true WO2002098066A3 (en) 2003-09-25

Family

ID=27542275

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CA2002/000810 WO2002098066A2 (en) 2001-06-01 2002-05-31 Cell-based switch fabric architecture on a single chip

Country Status (5)

Country Link
EP (1) EP1396117A2 (en)
CN (1) CN100579057C (en)
AU (1) AU2002302279A1 (en)
CA (1) CA2448978C (en)
WO (1) WO2002098066A2 (en)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9755907B2 (en) 2011-09-28 2017-09-05 Hewlett Packard Enterprise Development Lp Managing a switch fabric
EP2893678B1 (en) * 2012-09-10 2019-11-06 Marvell World Trade Ltd. Apparatus for transferring packets between interface control modules of line cards
KR101519743B1 (en) * 2013-11-29 2015-05-12 엘에스산전 주식회사 Bi-directional Packet Transfer Fail-over Switch for Serial Communication
US10841246B2 (en) 2017-08-30 2020-11-17 Arista Networks, Inc. Distributed core switching with orthogonal fabric card and line cards
US10986423B2 (en) 2019-04-11 2021-04-20 Arista Networks, Inc. Network device with compact chassis
US11266007B2 (en) 2019-09-18 2022-03-01 Arista Networks, Inc. Linecard system using riser printed circuit boards (PCBS)
CN112044081B (en) * 2020-08-26 2023-11-10 杭州电魂网络科技股份有限公司 Method and system for updating and inquiring player list
CN113868172A (en) * 2021-09-28 2021-12-31 上海兆芯集成电路有限公司 Interconnection interface

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0241152A2 (en) * 1986-04-10 1987-10-14 Stc Plc Automatic telecommunication switching system
WO1998026539A2 (en) * 1996-12-12 1998-06-18 Integrated Telecom Technology, Inc. Method and apparatus for high-speed, scalable communication system
US5790539A (en) * 1995-01-26 1998-08-04 Chao; Hung-Hsiang Jonathan ASIC chip for implementing a scaleable multicast ATM switch
US5831980A (en) * 1996-09-13 1998-11-03 Lsi Logic Corporation Shared memory fabric architecture for very high speed ATM switches
US6069895A (en) * 1997-08-29 2000-05-30 Nortel Networks Corporation Distributed route server
EP1051001A2 (en) * 1993-01-29 2000-11-08 Telefonaktiebolaget Lm Ericsson Controlled access ATM switch

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0241152A2 (en) * 1986-04-10 1987-10-14 Stc Plc Automatic telecommunication switching system
EP1051001A2 (en) * 1993-01-29 2000-11-08 Telefonaktiebolaget Lm Ericsson Controlled access ATM switch
US5790539A (en) * 1995-01-26 1998-08-04 Chao; Hung-Hsiang Jonathan ASIC chip for implementing a scaleable multicast ATM switch
US5831980A (en) * 1996-09-13 1998-11-03 Lsi Logic Corporation Shared memory fabric architecture for very high speed ATM switches
WO1998026539A2 (en) * 1996-12-12 1998-06-18 Integrated Telecom Technology, Inc. Method and apparatus for high-speed, scalable communication system
US6069895A (en) * 1997-08-29 2000-05-30 Nortel Networks Corporation Distributed route server

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
NOTANI H ET AL: "An 8*8 ATM switch LSI with shared multi-buffer architecture", PROCEEDINGS OF THE SYMPOSIUM ON VLSI CIRCUITS. SEATTLE, JUNE 4 - 6, 1992, SYMPOSIUM ON VLSI CIRCUITS, NEW YORK, IEEE, US, 4 June 1992 (1992-06-04), pages 74 - 75, XP010064987, ISBN: 0-7803-0701-1 *

Also Published As

Publication number Publication date
CN1533655A (en) 2004-09-29
EP1396117A2 (en) 2004-03-10
CA2448978C (en) 2011-08-09
CN100579057C (en) 2010-01-06
WO2002098066A2 (en) 2002-12-05
AU2002302279A1 (en) 2002-12-09
CA2448978A1 (en) 2002-12-05

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