WO2002101601A3 - Representing the design of a sub-module in a hierarchical integrated circuit design and analysis system - Google Patents

Representing the design of a sub-module in a hierarchical integrated circuit design and analysis system Download PDF

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Publication number
WO2002101601A3
WO2002101601A3 PCT/US2002/018424 US0218424W WO02101601A3 WO 2002101601 A3 WO2002101601 A3 WO 2002101601A3 US 0218424 W US0218424 W US 0218424W WO 02101601 A3 WO02101601 A3 WO 02101601A3
Authority
WO
WIPO (PCT)
Prior art keywords
design
integrated circuit
representing
sub
module
Prior art date
Application number
PCT/US2002/018424
Other languages
French (fr)
Other versions
WO2002101601A2 (en
Inventor
Timothy M Burks
Michael A Riepe
Hamid Savoj
Robert M Swanson
Karen E Vahtra
Ginneken Lukas Van
Original Assignee
Magma Design Automation Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Magma Design Automation Inc filed Critical Magma Design Automation Inc
Priority to JP2003504290A priority Critical patent/JP2005518002A/en
Priority to EP02739817A priority patent/EP1407391A2/en
Priority to IL15922402A priority patent/IL159224A0/en
Priority to CA002450143A priority patent/CA2450143A1/en
Priority to KR10-2003-7016097A priority patent/KR20040032109A/en
Publication of WO2002101601A2 publication Critical patent/WO2002101601A2/en
Publication of WO2002101601A3 publication Critical patent/WO2002101601A3/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G06F30/3315—Design verification, e.g. functional simulation or model checking using static timing analysis [STA]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/36—Circuit design at the analogue level
    • G06F30/367—Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

A method for modeling integrated circuit designs in a hierarchical design automation system which utilizes a block abstraction including therein set of all database objects (cells, nets, wires, vias, and blockages) that are necessary to achieve accurate placement, routing, extraction, simulation, and verification of the block's ancestors in the hierarchy.
PCT/US2002/018424 2001-06-08 2002-06-10 Representing the design of a sub-module in a hierarchical integrated circuit design and analysis system WO2002101601A2 (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP2003504290A JP2005518002A (en) 2001-06-08 2002-06-10 Display of submodule design in a hierarchical integrated circuit design and analysis system.
EP02739817A EP1407391A2 (en) 2001-06-08 2002-06-10 Representing the design of a sub-module in a hierarchical integrated circuit design and analysis system
IL15922402A IL159224A0 (en) 2001-06-08 2002-06-10 Representing the design of a sub-module in a hierarchical integrated circuit design and analysis system
CA002450143A CA2450143A1 (en) 2001-06-08 2002-06-10 Representing the design of a sub-module in a hierarchical integrated circuit design and analysis system
KR10-2003-7016097A KR20040032109A (en) 2001-06-08 2002-06-10 Representing the design of a sub-module in a hierarchical integrated circuit design and analysis system

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US29679701P 2001-06-08 2001-06-08
US60/296,797 2001-06-08

Publications (2)

Publication Number Publication Date
WO2002101601A2 WO2002101601A2 (en) 2002-12-19
WO2002101601A3 true WO2002101601A3 (en) 2003-12-11

Family

ID=23143594

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2002/018424 WO2002101601A2 (en) 2001-06-08 2002-06-10 Representing the design of a sub-module in a hierarchical integrated circuit design and analysis system

Country Status (7)

Country Link
EP (1) EP1407391A2 (en)
JP (1) JP2005518002A (en)
KR (1) KR20040032109A (en)
CN (1) CN1539113A (en)
CA (1) CA2450143A1 (en)
IL (1) IL159224A0 (en)
WO (1) WO2002101601A2 (en)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100382085C (en) * 2004-07-07 2008-04-16 华为技术有限公司 Board pattern designing method of integrated designing element in printed circuit board and its device
US7228514B2 (en) * 2005-01-21 2007-06-05 International Business Machines Corporation Method, system and computer program product for automatically estimating pin locations and interconnect parasitics of a circuit layout
WO2007002799A1 (en) 2005-06-29 2007-01-04 Lightspeed Logic, Inc. Methods and systems for placement
US7752588B2 (en) 2005-06-29 2010-07-06 Subhasis Bose Timing driven force directed placement flow
US8332793B2 (en) 2006-05-18 2012-12-11 Otrsotech, Llc Methods and systems for placement and routing
US7840927B1 (en) 2006-12-08 2010-11-23 Harold Wallace Dozier Mutable cells for use in integrated circuits
US8463587B2 (en) * 2009-07-28 2013-06-11 Synopsys, Inc. Hierarchical order ranked simulation of electronic circuits
CN102339342B (en) * 2010-07-27 2013-06-05 中国科学院微电子研究所 Method for fast materializing of parameterization device unit
US9111245B2 (en) * 2012-09-21 2015-08-18 The Boeing Company Displaying modeling data and logical data
CN105612520A (en) * 2013-08-06 2016-05-25 Ess技术有限公司 Constrained placement of connected elements
CN106777441B (en) * 2015-11-24 2020-04-21 龙芯中科技术有限公司 Timing constraint management method and device
US20180060472A1 (en) * 2016-08-30 2018-03-01 Mediatek Inc. Efficient cell-aware fault modeling by switch-level test generation
CN113642280A (en) * 2020-04-27 2021-11-12 中国科学院上海微系统与信息技术研究所 Layout method of superconducting integrated circuit
CN112395431B (en) * 2021-01-18 2021-04-30 北京晶未科技有限公司 Method for constructing behavior model, electronic device and electronic equipment
CN117436379B (en) * 2023-12-21 2024-04-09 成都行芯科技有限公司 Through hole compression method and device, electronic equipment and storage medium

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1996023263A1 (en) * 1995-01-25 1996-08-01 Lsi Logic Corporation Timing shell generation through netlist reduction
EP0806736A1 (en) * 1996-05-10 1997-11-12 Lsi Logic Corporation Method for creating and using design shells for integrated circuit designs
US5878053A (en) * 1997-06-09 1999-03-02 Synopsys, Inc. Hierarchial power network simulation and analysis tool for reliability testing of deep submicron IC designs
US5920484A (en) * 1996-12-02 1999-07-06 Motorola Inc. Method for generating a reduced order model of an electronic circuit
US6072945A (en) * 1997-06-26 2000-06-06 Sun Microsystems Inc. System for automated electromigration verification
WO2000039717A2 (en) * 1998-12-29 2000-07-06 Cadence Design Systems, Inc. Functional timing analysis for characterization of virtual component blocks
US6216252B1 (en) * 1990-04-06 2001-04-10 Lsi Logic Corporation Method and system for creating, validating, and scaling structural description of electronic device

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6216252B1 (en) * 1990-04-06 2001-04-10 Lsi Logic Corporation Method and system for creating, validating, and scaling structural description of electronic device
WO1996023263A1 (en) * 1995-01-25 1996-08-01 Lsi Logic Corporation Timing shell generation through netlist reduction
EP0806736A1 (en) * 1996-05-10 1997-11-12 Lsi Logic Corporation Method for creating and using design shells for integrated circuit designs
US5920484A (en) * 1996-12-02 1999-07-06 Motorola Inc. Method for generating a reduced order model of an electronic circuit
US5878053A (en) * 1997-06-09 1999-03-02 Synopsys, Inc. Hierarchial power network simulation and analysis tool for reliability testing of deep submicron IC designs
US6072945A (en) * 1997-06-26 2000-06-06 Sun Microsystems Inc. System for automated electromigration verification
WO2000039717A2 (en) * 1998-12-29 2000-07-06 Cadence Design Systems, Inc. Functional timing analysis for characterization of virtual component blocks

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
KAMON M ET AL: "Interconnect parasitic extraction in the digital IC design methodology", COMPUTER-AIDED DESIGN, 1999. DIGEST OF TECHNICAL PAPERS. 1999 IEEE/ACM INTERNATIONAL CONFERENCE ON SAN JOSE, CA, USA 7-11 NOV. 1999, PISCATAWAY, NJ, USA,IEEE, US, 7 November 1999 (1999-11-07), pages 223 - 230, XP010363806, ISBN: 0-7803-5832-5 *

Also Published As

Publication number Publication date
KR20040032109A (en) 2004-04-14
WO2002101601A2 (en) 2002-12-19
CN1539113A (en) 2004-10-20
CA2450143A1 (en) 2002-12-19
EP1407391A2 (en) 2004-04-14
JP2005518002A (en) 2005-06-16
IL159224A0 (en) 2004-06-01

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