WO2002103483A3 - Optimizing mergeability and datapath widths of data-flow-graphs - Google Patents

Optimizing mergeability and datapath widths of data-flow-graphs Download PDF

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Publication number
WO2002103483A3
WO2002103483A3 PCT/US2002/019138 US0219138W WO02103483A3 WO 2002103483 A3 WO2002103483 A3 WO 2002103483A3 US 0219138 W US0219138 W US 0219138W WO 02103483 A3 WO02103483 A3 WO 02103483A3
Authority
WO
WIPO (PCT)
Prior art keywords
operator
output
mergeability
graphs
optimizing
Prior art date
Application number
PCT/US2002/019138
Other languages
French (fr)
Other versions
WO2002103483A2 (en
Inventor
Sanjeev Saluja
Anmol Mathur
Original Assignee
Cadence Design Systems Inc
Sanjeev Saluja
Anmol Mathur
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Cadence Design Systems Inc, Sanjeev Saluja, Anmol Mathur filed Critical Cadence Design Systems Inc
Priority to AU2002306172A priority Critical patent/AU2002306172A1/en
Priority to EP02734805A priority patent/EP1412832A4/en
Publication of WO2002103483A2 publication Critical patent/WO2002103483A2/en
Publication of WO2002103483A3 publication Critical patent/WO2002103483A3/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/40—Transformation of program code
    • G06F8/41—Compilation
    • G06F8/44—Encoding
    • G06F8/443—Optimisation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs

Abstract

A DFG (100) has inputs A and B linked by edges (140) and (150), respectively, to an operator NI illustrated at (125). DFG (100) has inputs C and D linked by edges (145) and (160), respectively, to an operator N2 illustrated at (130). Operators NI and N2 (125) and (130) are illustrated as addition operators but could any of a variety of types of operators. The bitwidths of edges (140, 145, 150 and 160) are equal to 8. The widths of operators N1 and N2 (125) and (130) are equal to 9. While an output edge (155) has a bitwidth of 9. Which corresponds to the operator N2 (130), that of an output corresponds to the output of operator N2 (130) that of an output edge (165) which corresponds to the output of operator N1 (125), is equal to 7 so the output of node N1 (125) is obtained by truncating a 9 bit result to 7 bits by the operator N1 (125).
PCT/US2002/019138 2001-06-15 2002-06-17 Optimizing mergeability and datapath widths of data-flow-graphs WO2002103483A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
AU2002306172A AU2002306172A1 (en) 2001-06-15 2002-06-17 Optimizing mergeability and datapath widths of data-flow-graphs
EP02734805A EP1412832A4 (en) 2001-06-15 2002-06-17 Procedure for optimizing mergeability and datapath widths of data flow graphs

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US29853601P 2001-06-15 2001-06-15
US60/298,536 2001-06-15

Publications (2)

Publication Number Publication Date
WO2002103483A2 WO2002103483A2 (en) 2002-12-27
WO2002103483A3 true WO2002103483A3 (en) 2004-02-12

Family

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Family Applications (4)

Application Number Title Priority Date Filing Date
PCT/US2002/019138 WO2002103483A2 (en) 2001-06-15 2002-06-17 Optimizing mergeability and datapath widths of data-flow-graphs
PCT/US2002/019139 WO2002103515A1 (en) 2001-06-15 2002-06-17 Enhancing mergeability of datapaths and reducing datapath widths responsively to required precision
PCT/US2002/019127 WO2002103551A1 (en) 2001-06-15 2002-06-17 Enhancing mergeability of datapaths and reducing datapath widths by rebalancing data flow topology
PCT/US2002/019207 WO2002103585A1 (en) 2001-06-15 2002-06-17 Enhancing mergeability of datapaths and reducing datapath widths responsively to upper bound on information content

Family Applications After (3)

Application Number Title Priority Date Filing Date
PCT/US2002/019139 WO2002103515A1 (en) 2001-06-15 2002-06-17 Enhancing mergeability of datapaths and reducing datapath widths responsively to required precision
PCT/US2002/019127 WO2002103551A1 (en) 2001-06-15 2002-06-17 Enhancing mergeability of datapaths and reducing datapath widths by rebalancing data flow topology
PCT/US2002/019207 WO2002103585A1 (en) 2001-06-15 2002-06-17 Enhancing mergeability of datapaths and reducing datapath widths responsively to upper bound on information content

Country Status (4)

Country Link
US (4) US6772398B2 (en)
EP (4) EP1402401A4 (en)
AU (1) AU2002306172A1 (en)
WO (4) WO2002103483A2 (en)

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Also Published As

Publication number Publication date
EP1405179A1 (en) 2004-04-07
WO2002103515A1 (en) 2002-12-27
EP1402401A1 (en) 2004-03-31
WO2002103585A1 (en) 2002-12-27
EP1412832A4 (en) 2007-10-03
WO2002103483A2 (en) 2002-12-27
EP1405179A4 (en) 2007-10-03
US6832357B2 (en) 2004-12-14
US20030061577A1 (en) 2003-03-27
EP1402401A4 (en) 2007-10-03
WO2002103551A1 (en) 2002-12-27
US20030061574A1 (en) 2003-03-27
AU2002306172A1 (en) 2003-01-02
US6772398B2 (en) 2004-08-03
US6772399B2 (en) 2004-08-03
US20030061576A1 (en) 2003-03-27
US6807651B2 (en) 2004-10-19
US20030061575A1 (en) 2003-03-27
EP1405225A1 (en) 2004-04-07
EP1405225A4 (en) 2007-10-03
EP1412832A2 (en) 2004-04-28

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