WO2002103518A1

WO2002103518A1 - Efficient high performance data operation element for use in a reconfigurable logic environment

Info

Publication number: WO2002103518A1
Application number: PCT/US2002/011870
Authority: WO
Inventors: Joshua Lindner; Gary Lai; Peter Lam; Mark Edward Rollins; Vladimir Dinkevich; Craig Bradley Greenberg; Christopher E. Phillips; Hsin Wang; Bradley L. Taylor
Original assignee: Intel Corporation
Priority date: 2001-05-02
Filing date: 2002-05-02
Publication date: 2002-12-27
Also published as: JP2004531149A; DE10296742T5; GB2398653A; GB0327399D0; KR100628448B1; CN1860441A; US20030088757A1; KR20040005944A

Abstract

A reconfigurable chip (20) is taught having reconfigurable functional units including a shift register, arithmetic logic, and multiplexers. The data paths are interconnected to other data path units. Interconnection is provided by transferring word length data. The shifter allows for the word length data to be adjusted for use in the arithmetic logic unit. Reconfigurable functional units are controlled by reconfigurable functional unit instructions. The reconfigurable unit instructions are stored in a reconfigurable functional unit instruction memory, which is addressed by a state machine on the chip.

Description

EFFICIENT HIGH PERFORMANCE DATA OPERATION ELEMENT FOR USE IN A RECONFIGURABLE LOGIC

ENVIRONMENT

Related Application/Priority

[0001] The present application claims the priority of Provisional Application

No. 60/288,298, filed May 2, 2001.

Background of the Invention [0002] The present invention relates to reconfigurable logic chips, especially reconfigurable logic chips used for reconfigurable computing. [0003] Field programmable gate arrays (FPGAs) are programmable chips that can implement different configurations. Typically a design is created using design tools and a FPGA is configured for a specific design. Although designs can be changed, typically the FPGA uses a single configuration due to the relatively long time required to change a configuration compared to the operation time of the chip.

[0004] Recently reconfigurable chips designed to quickly switch portions of an algorithm on to a reconfigurable chip have been created. These reconfigurable chips are designed to use the reconfigurable elements of the chip so as to provide resources for the implementation portions of an algorithm. [0005] It is desired to have a data operation element or reconfigurable functional unit for use in a reconfigurable chip that implements an improved design to more effectively implement algorithms on a reconfigurable chip. Summary of the Invention

[0006] The present invention concerns a reconfigurable chip, including multiple reconfigurable functional units (such as a data path unit) adapted to implement different functions. The reconfigurable function units preferably include multiplexers, at least one shifting unit and at least one arithmetic logic unit (ALU). The reconfigurable functional units are configured by reconfigurable functional unit instructions. The instructions control the configuration of the multiplexer and shifting unit and the ALU. The reconfigurable chip also includes interconnect adapted to connect together the reconfigurable functional units. In this way data can be passed between the reconfigurable functional units.

[0007] The reconfigurable functional unit instruction preferably includes a number of fields for the multiplexers, the shifter unit and the arithmetic logic unit. These fields configure these elements in the reconfigurable functional unit in a desired way. [0008] In a preferred embodiment, there is an associated instruction memory for each reconfigurable functional unit has an associated instruction memory. The instruction memory stores multiple instructions for the reconfigurable functional unit. In a preferred embodiment, the state machine addresses the instruction memory to determine the next instruction to be loaded into the reconfigurable functional unit. In one preferred embodiment, the reconfigurable functional units provide feedback to the state machine indicating when a function is finished and thus when the next function can be loaded into the reconfigurable functional unit. [0009] In one embodiment, the shifter unit is configurable with a number of different modes. These modes are preferably selectable by a field of the reconfigurable functional unit instruction.

[0010] In one embodiment, interconnect elements are adapted to selectively connect some of the reconfigurable functional units to transfer word length data. The transferred data preferably has a fixed data length of 32 bits or greater. The fixed length data transfer allows interconnect system to be simplified at the loss of flexibility in the data transfer. The shifting unit in the reconfigurable functional unit allows the arithmetic logic unit to operate on different bits in the word length input data of the reconfigurable functional unit compensating for the fixed structure of the interconnect elements. Thus, if needed data is in a certain location within a word, the shifter can move that bit location to the proper position for manipulation by the arithmetic logic unit.

[0011] Another embodiment of the present invention comprises using a multiplexer with a delay unit input and an input that bypasses the delay unit. In this manner the reconfigurable functional unit can implement a variable delay increasing the flexibility of the system.

Brief Description of the Drawing Figures

[0012] Fig. 1 is an overview of the reconfigurable chip of one embodiment of the present invention; [0013] Fig. 2 is a simplified diagram of a reconfigurable functional unit of one embodiment of the present invention;

[0014] Fig. 3 is a diagram of a reconfigurable functional unit of one embodiment of the present invention;

[0015] Fig. 4 is a diagram of a multiplier unit which can be used with the embodiment of the present invention;

[0016] Fig. 5 is a diagram of one slice of the reconfigurable functional unit shown in Fig. 1 illustrating the interconnection between the data path units;

[0017] Fig. 6 is a diagram illustrating the connections between the data path unit and the horizontal and vertical bus lines; [0018] Fig. 7 is a diagram illustrating the interconnection of a data path unit in one tile to a data path unit in another tile; [0019] Fig. 8 is a diagram illustrating the interconnection of the data path units and a local system memory of one embodiment of the present invention;

[0020] Fig. 9 is a diagram illustrating a state machine and functional block configuration memory producing the instruction of configuration information for the functional block data unit;

[0021] Fig. 10A is a diagram illustrating the interconnection of a state machine, configuration state memory and data path unit of the present invention, showing the instruction and instruction fields for the data path unit;

[0022] Fig. 10B is a diagram illustrating a data path unit using a decoder for at least part of the instruction;

[0023] Fig. 11 is a diagram illustrating the control system configuration memory at data path unit as one embodiment of the present invention;

[0024] Fig. 12 is a diagram of an interconnection logic unit for use in one embodiment of the present invention; [0025] Figs. 13A and 13B are charts illustrating the portions of the instructions for the ALU;

[0026] Fig. 14 is a diagram illustrating the flags for the system of one embodiment of the present invention;

[0027] Fig. 15 is a diagram illustrating the shifting mode for shifter; [0028] Fig. 16 is a diagram of the instruction of one embodiment of the shifter;

[0029] Fig. 17 is a diagram illustrating the operation of the shifter of Fig. 16;

[0030] Fig. 18 is a diagram of a logic system using a multiple master latches of one embodiment of the present invention;

[0031] Fig. 19 is a diagram illustrating the background and foreground plane latches of one embodiment of the present invention;

[0032] Fig. 20 is a diagram of one embodiment of a reconfigurable functional unit for a data path in one embodiment of the present invention;

[0033] Fig. 21 is a diagram of the input multiplexers for the system of Fig. 20; [0034] Fig. 22 is a diagram of the shifting mode for the shifter of one embodiment of the present invention;

[0035] Fig. 23 is a diagram illustrating some shifting modes for the shifter of one embodiment of the present invention; and [0036] Fig. 24 is a diagram illustrating the implementation of a turbo look up table of one embodiment of the present invention.

Detailed Description of the Invention

[0037] Fig. 1 illustrates a reconfigurable chip 20. The reconfigurable chip 20 includes a central processing unit (CPU) 22, preferably a reduced instruction set (RISC) CPU. Data from the external memory (not shown) is transferred using memory controller 24. Bus 26, called the roadrunner bus, is used to transfer data from the memory controller to the reconfigurable fabric 28. The reconfigurable fabric 28 is divided into a number of slices. Each slice is broken down into a number of tiles. Each tile includes a data path unit (reconfigurable functional unit), control units and local system memory units. The local system memory units interact with the data path units as described below. In a preferred embodiment, each tile also has a number of multiplier units. [0038] Fig. 2 illustrates a simplified diagram of a reconfigurable functional unit of one embodiment of the present invention. The reconfigurable functional unit includes input multipliers 30 and 32. As will be described below, the input multipliers allow the data path unit to receive inputs from a number of different locations, including nearby data path units as well as data buses. The selected output of the input multipliers are sent on to registers 36 and 38. Additionally, the output of the multiplier 32 goes to shifter unit 34. As described below, the shifter unit 34 allows for the selection of different bits to be operated on by the ALU 40. Since the interconnections between the data path units use fixed word length connections to simplify the interconnection system, the use of a shifter unit in the data path unit allows access to bits packed within the interior of a word. [0039] As will be described below, the shifter unit 34 preferably has a number of modes which implement more than just logical and arithmetic shifts left and right. These different modes allow the system to operate in a more efficient manner. The arithmetic logic unit 40 described below, preferably uses a field of the instruction for the data path unit to implement a function. The output of the ALU 40 preferably goes to an output register 42. The output can also actually be sent to an optional bit shifter 44 to produce a shifted value. [0040] In one embodiment, a bypassing ALU feedback output on line 46 is also used. This allows portions of the data path unit to operate while the output register 42 controls what outputs are sent from the data path unit. This is useful when the output register 42 is used to address a local system memory unit. [0041] The bit shifter 44 is used to implement the linear feedback shift register as described in the patent application, "Modifications to Reconfigurable Functional Unit in a Reconfigurable Chip to Perform Linear Feedback Shift Register Function, " by Peter Lam, Attorney Docket No. 032001-060. [0042] Note that the multiplexers, shifter unit 34 and ALU 40 are preferably controlled by an instruction for the data path unit. This instruction is preferably divided into a number of different fields, including multiplexer instruction fields for the multiplexers, shifter unit fields for the shifter 34 and ALU instruction field for the ALU 40. In one embodiment, a decoder is used for at least part of the instruction. [0043] Fig. 3 is a detailed diagram of one embodiment of the present invention. The input multiplexers 50 and 52 receive as inputs data from nearby units. In one example, data words from 16 units, including data path units and multiplier units, are used as inputs. Global vertical and horizontal interconnections are used. In one embodiment a connection for the linear feedback shift register feedback, a logical zero constant input and an input for a local system memory unit. Another input is the carry input from the prior data path unit which is provided to the ALU 54 directly. The multiplexer 50 is connected to the shifter 56, including a number of different modes of operation. The shifter 56 is connected to another multiplexer 58 so that the output of the multiplexer 50 can either avoid or use shifter unit 56. The shifter unit 56 can also use the A input from the input multiplexer 52 for some of the modes. The output of the multiplexer 58 and the output of multiplexer 52 can be sent to registers 60 and 62, respectively. The registers 60 and 62 can also be loaded from off the chip. This logic 64 and 66 allows for the register values to act as a mask register for the system. The multiplexers 68 and 70 select the inputs to the ALU 54. Outputs to the ALU are sent to a number of different possible paths. Note that the data path output out of multiplexer 72 can be the value from the output register 74, or the value from the multiplexer 76 (which can be the ALU value or the local system memory re-data on line 78). The flag values from the ALU are sent to multiplexers 80 and 82 which select the desired flag value. This flag value can be stored in registers 88 and 90 and the value of the registers 88 or 90 is sent to the multiplexers 92 and 94 or the selected value from multiplier 80 or 82 is used. The CONF value is a field in the instruction that indicates which flag to select. [0044] In one embodiment, the registers 60, 62 and 74 can be implemented by using multiple master slave latches, shown in Fig. 18, to allow the loading of background configuration data into the register. In one embodiment, the operation of these registers can be controlled by the field of the reconfigurable functional unit instruction. [0045] Fig. 4 is a diagram of a multiplier unit. The multiplier unit is oriented somewhat similar to the reconfigurable functional unit shown in Fig. 3. However, the multiplier unit has a dedicated multiplier rather than an ALU. [0046] As shown in Fig. 5, in one embodiment for every seven data path units or reconfigurable functional units in a tile, there are two multiplier units. [0047] Fig. 6 illustrates the connections of adjacent data path units and multipliers into the data path unit inputs. Note looking at Fig. 5, the data path unit 100 can receive as an input, outputs from eight previous data path units (and multipliers) above and seven of the next data path units (and multipliers) below. The output of the data path unit 100 is also fed back to itself. The outputs of any of these units can be selected using the input multiplexers of the system for either the A or B inputs. [0048] Fig. 6 is a diagram that illustrates the connection of the one tile reconfigurable functional units (data path units) to horizontal and vertical connection lines. By using multiplexers, the outputs, and inputs, of the data path units can be interconnected to both the vertical routing lines and the horizontal routing lines. [0049] Fig. 7 illustrates an example of interconnecting a data path unit in one tile to a data path unit in another tile using vertical interconnected lines. Note that the system of the present invention for the interconnections preferably uses word- based interconnections. In one embodiment, the interconnection lines allow the connection of 32 bit wide data. The shifter unit in the data path unit allows for the alignment of the data once it is received into a data path unit from the interconnection system. Because the system sends data in a 32 bit word, the complexity of the interconnect system is reduced and simplified, reducing somewhat the flexibility of the interconnect. [0050] Fig. 8 illustrates the connection between the data path units and the local system memory. In a preferred environment, alternate data path units are used to implement the Writes and Reads of the local system memory. For example, data path unit 102 provides Read Addresses to and receives read data from the local system memory 104. Data path unit 106 provides the Write Address and Write data for the local system memory 104. Note that by using the pass gates such as pass gates 106, 108, 110 and 112, the data path units 102 and 106 can connect to other local system memories, such as local system memory 114 and the data path units 116 and 118 can connect to the local system memory 104. In another embodiment, a data path unit can both read from and write to a local system memory. One of the uses of a data path unit is to provide an address to a local system memory to obtain data from a local system memory, which can then be put upon the horizontal and vertical interconnection buses. The connections shown in Fig. 8 are the direct connections to read and write data in and out of the local system memory. In a preferred environment, the local system memory is globally read from and written to using the memory control system. This general memory control system is used for configuration of the system and for obtaining the data operated on by the data path units. Note that as described above, in a preferred embodiment, the data path units include structures that allow addresses and data to be provided to the local system memory while the data path unit does some other function.

[0051] Fig. 9 is a disclosure of a control fabric unit 132 for the reconfigurable functional unit 130. In this embodiment, the control fabric unit 132 produces a control or instruction line for the reconfigurable functional unit 130. In this embodiment, the control fabric unit 132 is preferably composed of a state machine unit 134 and a functional block configuration memory unit 136. The state machine 134 produces the addresses into the instruction memory 136. One implementation of the state machine 134 uses a reconfigurable programmable sum-of-products unit 136. [0052] Fig. 10A illustrates a system with the state machine configuration unit 136, the configuration state memory 138' and the data path unit 130' . Note that the configuration from the configuration state memory 138' can be considered to be an instruction for the data path unit 130' . The instruction preferably includes fields such as an ALU configuration field, shift register configuration field, and a multiplexer configuration field. In one embodiment, some of the flags from the data path unit 130' are sent to the state machine 136' in order to switch configurations for the data path unit after the data path unit is done operating on a set of data. The configuration state machine 138' can also be loaded from an external configuration from external memory or from the processor. [0053] Fig. 10B is a diagram illustrating a data path unit using a decoder to decode at least part of an instruction. [0054] Fig. 11 shows the control system, including the state machines for the different configuration state memories. The data path unit flags are sent to the control system as described above.

[0055] Fig. 12 is a diagram that illustrates one example of an arithmetic logic unit. This arithmetic logic unit includes an arithmetic unit 142, a parallel logic unit 140 and a flag unit 144. Also shown is a carry selection unit 146. The ALU instruction field from the instruction is sent to select the operations of the ALU. The arithmetic unit 142 uses a carry input. In a preferred embodiment, this carry value is either the carry from the previous data path unit or the control signal or a carry which is part of the instruction. [0056] Figs. 13 A and 13B illustrate a list of some of the Opcodes used in one embodiment of an ALU of the reconfigurable functional unit of the present invention. Details of these Opcodes are described in the Appendix I, incorporated herein by reference.

[0057] Fig. 14 is a diagram of the flag system for the present invention. The flag unit is inside the data path unit and used for producing the flags which go to the control unit as well as to the next data path unit. The selection of the flags which are used the control of a field of the reconfigurable functional instruction and are preferred by the present invention. A description of the some of the flags is given below. [0058] ROXR is driven every cycle. It is selected by conf = = 1.

The operation is: case opcode[7] = =0 flag[l] = = "(B[31:0]) flag[0] = = ^A(B[15:0]) case opcode[7] = = 1 flag[l] = = ^A(B[31:16]) flag[0] = = ^A(B[15:0])

Abbreviations:

CO - Carry Out (of the addition/subtraction operation)

OV - Overflow (of the addition/subtraction operation) EQ - Equal (A= = B)

GT - Greater Than

LT - Less than

SN - Sign (sign bit of result)

Previous Flag Cin - Carry in pevious row

Ctrl - Carry in from control

Max - Ox7fff[ffffJ (for 16/32 bits)

Min - 0x8000[0000] (for 16/32 bits)

[0059] Fig. 15 illustrates the shift mode and the operation of some of the modes of the shifter unit of one embodiment of the present invention. Since the shifter unit has a number of different modes, the flexibility of the system of the present invention is increased.

[0060] Figs. 16 and 17 illustrate one implementation of the shifter unit using multiple rows of multiplexers. Additional logic is also of use to produce a special output. Fig. 17 illustrates the operation of some of the implementations of the shift register.

[0061] This shifter used in the Datapath unit performs more than right/left shift operations. The shifter includes an array of multiplexers which are controlled via mux select signals. In one 4x6 multiplexer array shifter embodiment, a 32-bit operand which is divided into four groups of 8 signals is coupled to a first row of four multiplexers. Other than the last row, the outputs of the multiplexers in a previous row are coupled to the inputs of the next row of multiplexers. Each multiplexer in the array is controlled independently. The control signals determine how the signals are routed in the array and hence the type of operation performed on the operand. In one embodiment, examples of operations include: 32-bit logical right/left shift, 32 bit arithmetic right/left shift, lower 16-bit sign extend to 32-bit, constant generation, duplicate lower 16 bit to upper 16 bit, duplicate upper 16 bit to lower 16-bit, swap lower and upper 16- bit, 16-bit arithmetic right shift, and byte swap. [0062] Fig. 18 illustrates a multiple master latch system used in one embodiment of the system of the present invention. In this example, two master latches are used. One of the master latches is used for the background configuration of the system. The other master latch receives data from the pipeline in the data path unit or from the processor. The inputs to the latch 150 are provided through the multiplexer 152. The latch 154 is connected to the configuration bus to receive data from background configuration. The multiplexer 156 can be used to select the input to the slave latch 158. The use of a background configuration memory to the system allows the quick operation of the system in the present invention.

[0063] The storage element of Fig. 18 has multiple master latches which share a single slave latch via a multiplexer which provides a multi-function storage element. In addition, by sharing a slave latch a significant space savings is realized (approximately 25%). This is particularly true in a system utilizing numerous storage elements. The storage element design relies on the fact that configuration bits are infrequently loaded into storage elements. So instead of having a separate slave latch for each master latch coupled to a configuration bitstream signal, according to the invention the master latch coupled to the configuration bitstream signal shares its slave latch with another master latch. Hence, two or more master latches share a single slave latch. A multiplexer is coupled between the master latches and the single slave latch for selecting which master latch is coupled to the slave latch.

[0064] In one embodiment, one master latch's input is coupled to a signal that frequently requires the storage element functionality and the other master latch's input is coupled to a signal that requires the storage element functionality on an infrequent basis. In the first master latch is coupled to the data path signal and the second master latch is coupled to the configuration bit signal. When the data path signal is passed to the slave latch, the storage element functions to divide the data path pipeline into stages. When the configuration bitstream signal is passed to the slave latch, the storage element functions to store the configuration bits. In another embodiment, one master latch is coupled to the data path signal and more than one master latch is coupled to a configuration bit signal and all of the master latch outputs are coupled to the multiplexer which is used to select and pass one of the signals from the master latches to the shared slave latch. [0065] For Fig. 18:

• master latches are reset upon 'RESET' or 'INIT' • slave latches are reset upon 'RESET' only

• mux A selects config path whenever configuration is activating, (further qualified by the particular slice being selected)

• mux B selects arc bus when arc is writing (further qualified by decoding corresponding arc address. Please refer to ARC ext spec for address map)

• master latches are transparent only during clock low

• slave latches are transparent only during clock high • master latch 0 is transparent when the latpipe 0 is enabled or arc write to that register is happening

• master latch 1 is transparent when config loading is activate and the corresponded config address is decoded • slave latch is transparent when 1. config activate to this slice or

2. arc write to this register or

3. latpipe signal from control is high

• This setup is under the assumption that configuration and arc write will not happen at the same time. If it does happen, the configuration has higher priority.

[0066] Another embodiment of the present invention concerns the variable delay units of the present invention. Variable delay units are comprised of a multiplexer which receives first unit sent into a register and the second input which bypasses the register. In this way a variable delay can be implemented. In the reconfigurable functional unit of Fig. 3 the register 60, connected to the multiplexer 68 and the register 62 connected from multiplexer 70 and register 88 connected to the multiplexer 92, the register 90 connected to the multiplexer 94 and the register 74 connected to the multiplexer 72, can implement such a variable delay. A multiplexer can select a delayed or a bypass signal; the delay signal going through a delay element like a flip-flop.

[0067] The flexible adaptive delay element includes a storage device (e.g., flip-flop, latch) having its input coupled to an input signal and its output coupled to a first input of a multiplexer. The other input of the multiplexer is coupled to the input signal. As a result, the first input of the multiplexer is coupled to the input signal and a second input of the multiplexer is couple to the input signal delayed by the amount provided from the storage device. The select signal can then be used to select either the delayed signal or the undelayed signal. [0068] Fig. 19 shows an alternate embodiment of a background foreground plane arrangement

[0069] The present invention incorporates by reference the prior patent applications, including "A HIGH PERFORMANCE DATA PATH UNIT FOR BEHAVIORAL DATA TRANSMISSION AND RECEPTION, " Inventor Hsinshih Wang, Serial No. 09/307,072 filed May 7, 1999 (Attorney Docket No. 032001-014), "CONTROL FABRIC FOR ENABLING DATA PATH FLOW," Inventors Shaila Hanrahan, et al., Serial No. 09/401,194 filed September 23, 1999 (Attorney Docket No. 032001-016), as well as "CONFIGURATION STATE MEMORY FOR FUNCTIONAL BLOCKS ON A RECONFIGURABLE CHIP, " Inventors Shaila Hanrahan and Christopher E. Phillips, Serial No. 09/401,312, and filed on September 23, 1999 (Attorney Docket No. 032001-035). [0070] Vermont Embodiments. ₍ [0071] Fig. 20 illustrates a ultimate embodiment of the reconfigurable functional unit or data path unit. In this embodiment an additional register and multiplexer are added to the B input path before the shifter. Additionally, the input multiplexer is slightly modified. The input multiplexer is shown with respect to Fig. 21. [0072] Fig. 22 illustrates the shifter mode table for the new embodiment of Fig. 19.

[0073] Fig. 23 illustrates the implementation of the new modes of Fig. 22. [0074] Fig. 24 illustrates a turbo look up table for use with the system of the present invention. The turbo look up table is useful in the addition of data stored in a logarithmic format. This is useful for many communication systems. In one prior embodiment in order to do the multiplication of data stored in logarithmic format, the data must be converted to the normal format by doing an exponential expansion of the data. The exponentially expanded data is added together and then the combined information is converted back to the logarithmic format. In the preferred embodiment, the turbo look up table is used in the production of an estimate of the addition of a correction factor. This estimate uses the value of the greatest value of A and B as a first estimate of the value of addition of A plus B. The absolute value of this difference of A minus B is used as an input to a look up table to provide a correction factor to add to the greatest value of A or B. By adding this correction factor to the greatest value of A or B a relatively accurate estimation is produced. Note that the look up table need not have the same number of input bits of A. In a preferred embodiment, only a few bits of precision are used. If the magnitude of A minus B is relatively large, the combined value does not significantly differ from the greatest value of A or B. For example, the addition of 1,000,000 to 0.1 is approximately 1,000,000. The addition of 1,000,000 to 1,000,000 is effectively doubling the maximum value. [0075] Appendixes II and III further illustrate the Vermont embodiment of the reconfigurable functional unit. [0076] It will be appreciated by those of ordinary skill in the art that the invention can be implemented in other specific forms without departing from the spirit or character thereof. The presently disclosed embodiments are therefore considered in all respects to be illustrative and not restrictive. The scope of the invention is illustrated by the appended claims rather than the foregoing description, and all changes that come within the meaning and range of equivalents thereof are intended to be embraced herein. Appenαix i

-17-

1.9 Opcode Details

Name ADD

Pseudocode result = A+B Description A plus B Flags Affected CO carry out of the operation OV if the operation overflow EQ if a==b SN result[31]

Name ADD16

Pseudocode result = {(AH+BH),(AL+BL)} Description Parallel A plus B Flags Affected CO.OV.EQ.SN similar to ADD except the flag[0] is also valid

Name ADDC

Pseudocode result = A+B+Cin

Description A plus B with carry in for 32 bit operation.

Cin is the CO of the lower 16bits.

Flags Affected CO OV EQ SN similar to ADD

Name ADDCNT

Pseudocode result = A+B+Ctrl Description A plus B with control carry in Flags Affected CO,OV,EQ,SN similar to ADD

Name SUB

Pseudocode result = A-B Description A minus B Flags Affected COcarry out of the operation (A+-B+1)

OVif the operation overflow

GTif A>B LTif A<B EQif A==B SNsign of result

Name SUB16

Pseudocode result = {(AH-BH),(AL-BL)} Description Parallel A minus B Flags Affected CO,OV_IGT_lLT_lEQ_>SN similar to SUB

Name SUBC

Pseudocode result = A+~B+Cin Description A minus B with carry in for 32 bit operation Flags Affected CO.OV.GT.LT.EQ.SN

similar to SUB

Name SUBCNT

Pseudocode result = A+~B+Ctrl Description A minus B with control carry in Flags Affected CO.OV.GT.LT.EQ.SN similar to SUB

Name SADD Pseudocode if (overflow) result = max else if (underflow) result = min else result = A+B

Description A plus B with saturation Flags Affected COcarry out of A+B OVoverflow of A+B EQA==B SN sign of result Name SADD16

Pseudocode Parallel 16 bit version of SADD Description A plus B with saturation Flags Affected CO,OV,EQ,SN similar to SADD, flag[0j is valid

Name SADDCNT Pseudocode if (overflow) result = max else if (underflow) result = min else result = A+B+Ctrl

Description A plus B with control carry in and saturation Flags Affected CO.OV.EQ.SN similar to SADD

Name SSUB Pseudocode if (overflow) result •= max else if (underflow) result = min else result = A-B

Description A minus B with saturation Flags Affected CO carry out of A+-B+1 OV overflow of A-B GT A>B LT A<B EQ A==B SN sign of result

Name SSUB16 Pseudocode Parallel 16 bit version of SSUB Description A minus B with saturation Flags Affected CO.OV.GT.LT.EQ.SN similar to ssub, flag[0] valid

Name SSUBCNT Pseudocode if (overflow) result = max else if (undeflow) result = min else result = A+~B+Ctrl

Description A minus B with control carry in and saturation Flags Affected CO.OV.GT.LT.EQ.SN similar to ssub

Name INC

Pseudocode result = B+1 Description Increment B Flags Affected CO carry out of B+1

OV overflow of B+1

SN sign of B+1

Name DEC

Pseudocode result = B-1 Description Decrement B Flags Affected CO.carry out of B+Oxfrffffff OV.overflow of B-1

SN sign of B-1

Name NEG

Pseudocode result = ~B+1 Description Negate B Flag Affected

SNsign of ~B+1

Name ABS

Pseudocode if (B is negative) result = ~B+1 else result = B

Description Absolute value of B

Flags Affected

Name ABS 16

Pseudocode Parallel 16 bit version of ABS

Description Absolute value of B, for 32 bit operation

Flags Affected

Name CSUB

Pseudocode if (A-B >= 0) result = A-B else result = A

Description Conditional subtraction

Flags Affected CO, carry out of A+-B+1

OV, overflow of A-B

GT,A>B

LT,A<B

EQ,A==B

SNsign of result

Name AND

Pseudocode result = A&B

Description Bitwise AND

Flags Affected EQ A==B

SN bit[31] of result Name OR

Pseudocode result = A|B Description Bitwise OR Flags Affected EQ,SN same as AND

Name NAND

Pseudocode result = ~(A&B) Description Bitwise NAND Flags Affected EQ.SN same as AND

Name NOR

Pseudocode result = ~(A|B) Description Bitwise NOR Flags Affected EQ.SN same as AND

Name XOR

Pseudocode result = A^ΛB Description Bitwise XOR Flags Affected EQ,SN same as AND

Name XNOR

Pseudocode result = ~(A^ΛB) Description Bitwise XNOR Flags Affected EQ,SN same as AND

Name PASSA

Pseudocode result ^*= A Description Pass A Flags Affected EQ,SN same as AND Name PASSB

Pseudocode result = B Description Pass B Flags Affected EQ.SN same as AND

Name NOTA

Pseudocode result = ~A Description Invert A Flags Affected EQ.SN same as AND

Name NOTB

Pseudocode result = ~B Description Invert B Flags Affected EQ,SN same as AND

Name MIN Pseudocode if (A<B) result = A else result = B

Description Return smaller of A and B Flags Affected GT A>B LT A<B EQ A==B SN bit[31] of result CO carry out of A+-B+1 OV overflow of A-B

Name MIN16 Pseudocode Parallel 16 bit version of MIN Description Return smaller of A and B, for 32 bit operation Flags Affected same as min, valid for flag[0] as well

Name MAX Pseudocode if (A>B) result = A else result = B

Description Return larger of A and B Flags Affected

GT A>B

LT A<B

EQ A==B

SN bit[31] of result

CO carry out of A+-B+1

OV overflow of A-B

Name MAX16

Pseudocode Parallel 16 bit version of MAX Description Return larger of A and B, for 32 bit operation Flags Affected same as min, valid for flag[0] as well

Name PENC Pseudocode result = 0; for( i = 31;i >= 0;i -;){ if (B(i) == 1) { result = i+1 ; break;

} }

Description Leading One Detection, Flags Affected none

Name MUXBBA Pseudocode result = in[A[4:0]j Description Use the 4 Isb of input A to multiplex the 16 inputs of B Flags Affected

SN bit[31] of result

Name SHIFTBBA Pseudocode ■f <A[5]) result = B « A[4:0]; else result = B « A[4:0];

Description Shift B by A. The 16/32 bit is decided by con32 bit in config memory. In either case, the shifted out bit will be passed to the flag.

Flags Affected bit[31] of result

1.11 DPU Functions - After the shifter/Mask

16 bit 32 bit

Arithmetic Add Add

Sub Sub

Saturation Add Saturation Add

Saturation Sub Saturation Sub

Inc Inc

Dec Dec

Neg Neg

Logic AND AND

OR OR

XOR XOR

NAND NAND

NOR NOR

XNOR XNOR

NOT NOT

PASS(NOP) PASS(NOP)

Special Func. ABS ABS

MIN MIN

MAX MAX

Rxor Rxor

N/A DIY

N/A LFSR

N/A PENC

N/A MUXB by A¹

N/A SHFTB by A²

NOTE: We can build a 896 bit (28*32) operator per slice.

¹ To implement N:l multiplexers where 2<=N<=8

² A[4:0] is the shift amount, A[5] is the direction of the shift CS2212 ALU Opcode Additions

The following opcodes will be added to the CS2212:

ADD8 SUB8

ADDSUB16 SUBADD16

Operation ADD8: 8 bit addition Out[7:0] = A[7:0] + B[7:0] Out[15:8] = A[15:8] + B[15:8] Out[23:16] = A[23:16] + B[23:16] Out[31 :24] = A[31 :24] + B[31 :24]

Opcode

Bit Granularity 8 bit operation

Flags Affected No flags are available

Operation SUB8: 8 bit addition Out[7:0] = A[7:0] + ~B[7:0] + 1 Out[15:8] = A[15:8] + ~B[15:8] + 1 Out[23:16] = A[23:16] + ~B[23:16] + 1 Out[31:24] = A[31:24] + ~B[31:24] + 1

Opcode

Bit Granularity 8 bit operation

Flags Affected No flags are available

Operation ADDSTJB16: 16 bit addition and subtraction Out[31:16] = A[31:16] + B[31:16] Out[15:0] = A[15:Q] f ~B[15:01 + 1

Opcode

Bit Granularity 16 bit operation

Flags Affected CO, OV, EQ, SN

Operation SUB DD16: 16 bit addition and subtraction Out[31:16] = A[31:16] + ~B[31:16] + 1 Out[15:0] = A[15:0] + B[15:0]

Opcode

Bit Granularity 16 bit operation

Flags Affected CO, OV, EQ, SN CS2212 Multiplier Output Mux Specification

The output mux for the Multiplier will be changing for the CS2212 in order to allow the A or B operand to be latched at the O register. This effectively bypasses the multiplication operation. This will require the addition of one bit to the 'muxmultlsmsel' ■ field in the MULT CSM. The signal 'muxmultlsmsel' will select the input to the O register in the following fashion:

This functionality allows the user to employ the multiplier as a dynamically configurable routing resource when it is not being used for its primary function.

CS2212 Pipeline Register Specification

The CS2112 has registers that can be used as either mask registers or pipeline registers, hi order to allow the user to use pipeline registers in the A and B operand paths, and use the mask registers, the CS2212 will include additional registers. These registers are inserted after the A and B input and will be referred to as 'apipe' and 'bpipe'. These registers can be bypassed by the signals 'muxapipe' and 'muxbpipe' respectively. Refer to the CS2212 DPU Block Diagram for the placement of these registers and muxes. The muxes are selected in the following fashion:

CS2212 LSM Write Data Mux Specification

The CS2212 will be able to write to the LSM with the shifter output, as well as with the ALU output. In order to facilitate this added functionality, a mux will be added to the LSM write data path. This mux will be referred to as 'muxlsmwd', and will be selected by 'muxlsmwdseP in the following fashion:

Refer to the CS2212 Block Diagram for the placement of 'muxlsmwd'.

2.1 General Description

The fabric is reconfigurable and it is controlled by config bits. The config bits are loaded into the fabric by issuing arc instructions (through load store) and then the config controller will transfer the config bits into the fabric's configuration plane.

The following table is to provide software information about what address does each config signal correspond to in the address space. So far the base address of the configuration has not been determined yet and so the following address will start from 0.

2.2 Details

• The top 16 bits will be the embedded address

• The top bit (bit[127]) is the parity bit. The hardware will check for even parity in each line of 128 bit. For behaviour of parity, please check ARC extension spec by Dani.

• The address below is relative to some base_address

• Each 128bit line will carry 112 bits of config data

• During config loading, the hardware can store at most 112 bit line each cycle

• For the lines which are not needed for a certain configuration, those particular line(s) can be skipped.

• The slice address will not be embedded in the current address map and will be erased from the current mapping for now. User should refer to ARC extension spec to see how to configure multiple slice in one operation.

2.3 Address Map

Input_mux Slice 0 PLAO ( each bit has individual enables) PLAin[0].is the multiplexer input associated with DPUO PLAin[l] is the multiplexer input associated with DPUO STATE0[n] is the primary state output of slice 0 LSTATEOfn] is the lower state output of slice 0 FLAG[n] is the primary flag output of slice 0 LSTATE0[n] is the lower flag output of slice 0 HBIT0[n] is the Horizontal State bus^' HBIT0[n] needs an optional register before the input mux. IO[7:0] are 8 I/O bits coming from the pins associated with each slice.

Bit 0 input, DATA, is the hortnet mux output from the datapath. Each tile has 8 hortnet mux. The control will pick up the lower 16 bit hortnet mux 7 from each tile. Notice it is the value at the output of the mux 7, input of the tristate. • Tile D is taken out and so data it provides (STATE*[31:24],FLAG[27:21]...) are connected to ground)

The PLA_in_sel are 64tol mux select. There are 16 of them for each PLA (each bit are individually . controlled).

• Horzjnux SliceO PLAO (each bit has individual enables)

• HMUX[0] is one of 16 Horizontal State Lines;

• Each mux needs also tristate enable.

Claims

WHAT IS CLAIMED IS:

1. A reconfigurable chip including:

Multiple reconfigurable functional units adapted to implement different functions, the reconfigurable functional units including multiplexers, at least one shifter unit and at least one arithmetic logic unit, the reconfigurable functional units being configured by a reconfigurable functional unit instruction, the instruction controlling the configuration of the multiplexers, shifter unit and arithmetic logic unit; and

Interconnect elements adapted to selectively connect together some of the reconfigurable functional units.

2. The reconfigurable chip of Claim 1 wherein the reconfigurable functional unit instruction is divided into a number of fields, including a multiplexer field, a shifter unit field and an arithmetic logic unit field.

3. The reconfigurable chip of Claim 1 wherein the reconfigurable functional unit comprised of the data path unit.

4. The reconfigurable chip of Claim 1 wherein the interconnect element are adapted to transfer word length data.

5. The reconfigurable chip of Claim 4 wherein the word length data are 32 bits long or greater.

6. The reconfigurable chip of Claim 1 further comprising an instruction memory storing multiple instructions for the reconfigurable functional units.

7. The reconfigurable chip of Claim 1 wherein the shifter unit is configurable with a number of modes.

8. The reconfigurable chip of Claim 7 wherein the reconfigurable functional unit instruction includes a shifter unit field which controls the mode of the shifter unit.

9. The reconfigurable chip of Claim 1 wherein at least one of the multiplexers is associated with a delay unit input and any input that bypasses the delay unit to implement variable delay system.

10. The reconfigurable chip of Claim 1 wherem the reconfigurable functional unit include registers for temporarily storing values within the reconfigurable functional unit.

11. A reconfigurable chip including:

Multiple reconfigurable functional units, the reconfigurable functional units including multiplexers, at least one shifter unit and at least one arithmetic logic unit, the shifter unit adapted to allow the arithmetic logic units to operate on different bits within the word-length input data of the reconfigurable functional unit; and

Interconnect elements adapted to selectively connect together some of the reconfigurable functional units, the interconnect elements adapted to transfer word-length data.

12. The reconfigurable chip of Claim 11 wherein the word length data are 32 bits or greater.

13. The reconfigurable chip of Claim 12 wherein the word length data are 32 bits long.

14. The reconfigurable chip of Claim 11 wherein the reconfigurable functional units are configured by reconfigurable functional unit instruction. The instruction controlling the configuration of the multiplexers, shifter unit and arithmetic logic unit.

15. The reconfigurable chip of Claim 11 wherein the reconfigurable chip further comprises an instruction memory storing multiple instructions for the reconfigurable functional unit.

16. The reconfigurable chip of Claim 11 wherein the shifter unit is configurable with a number of different modes.

17. The reconfigurable chip of Claim 11 wherein some of the multiplexers are associated with a delay unit input and an input that bypasses the delay unit.

18. A reconfigurable chip including:

Multiple reconfigurable functional units, the reconfigurable functional units including multiplexers, at least one shifter unit and at least one arithmetic logic unit, the reconfigurable functional units being configured by a reconfigurable functional unit instruction, the instruction controlling the configuration of the multiplexers, shifter unit and arithmetic control unit; and

An instruction memory storing multiple instructions for the reconfigurable functional units.

19. The reconfigurable chip of Claim 18 wherein an instruction memory is associated with each reconfigurable functional unit.

20. The reconfigurable chip of Claim 18 wherein the instruction memory is associated with a state machine producing an address for the instruction memory.

21. The reconfigurable chip of Claim 18 wherein the reconfigurable functional unit instruction includes fields for configuring the multiplexer, a shifter unit control field and an arithmetic logic unit control field.

22. The reconfigurable chip of Claim 18 further comprising an interconnect elements adapted to selectively connect together some of the reconfigurable functional units.

23. The reconfigurable chip of Claim 22 wherein the interconnect units adapted to transfer word length data.

24. The reconfigurable chip of Claim 18 wherein the shifter unit is configurable with a number of modes.

25. The reconfigurable chip of Claim 24 wherein the shifter unit is controlled by a shifter unit field, the reconfigurable unit instruction.

26. The reconfigurable chip of Claim 18 wherein at least one of the multiplexers is associated with a delay unit input and an input that bypasses the delay unit so that a variable delay can be implemented.

27. A reconfigurable chip including:

Multiple reconfigurable functional units, the reconfigurable functional units including multiplexers, at least one shifter unit and at least one arithmetic logic unit, the shifter unit being configurable with a number of modes; and Interconnect elements adapted to selectively connect together some of the reconfigurable functional units.

28. The reconfigurable of Claim 27 wherem the shifter modes include modes other than logical and arithmetic left and right shifts.

29. The reconfigurable chip of Claim 27 wherein at least one mode rearranges blocks of the input word.

30. The reconfigurable chip of Claim 27 wherein one of the modes comprises a constant generation.

31. The reconfigurable chip of Claim 27 wherein one of the modes comprises the duplication of one set of bits to another set of bits.

32. The reconfigurable chip of Claim 27 wherein one of the modes comprises swapping some of the groups of bits with other groups of bits.

33. The reconfigurable chip of Claim 27 wherein the reconfigurable functional units are configured by reconfigurable functional unit instructions. The reconfigurable functional unit instruction configuring the arithmetic logic unit, shifter unit and multiplexers.

34. The reconfigurable chip of Claim 33 wherein the reconfigurable functional unit instruction includes a field for controlling the shifter unit which controls the mode of the shifter unit.

35. The reconfigurable chip of Claim 27 wherein the interconnect elements are adapted to transfer word length data.

36. The reconfigurable chip of Claim 27 wherein the further comprising instruction memory storing instructions for the reconfigurable functional unit.

37. The reconfigurable chip of Claim 27 wherein at least one of the multiplexers is associated with the delay input unit and an input that bypasses the delay unit so as to implement a variable delay.

38. A reconfigurable chip including:

Multiple reconfigurable functional units, the reconfigurable functional units including multiplexers, at least one shifter unit and at least one arithmetic logic unit, wherein at least one of the multiplexers are associated with a delay unit input and an input that bypasses the delay unit ; and

39. The reconfigurable chip of Claim 38 wherein the reconfigurable functional units are reconfigured by a reconfigurable functional unit instruction, the instruction controlling the configuration of the multiplexer, shift unit and arithmetic logic unit.

40. The reconfigurable chip of Claim 39 wherein the reconfigurable functional unit instruction includes a number of different fields for controlling the configuration of the multiplexers, shifter unit and arithmetic logic unit.

41. The reconfigurable chip of Claim 39 wherein a field of an instruction for the reconfigurable functional unit indicates the mode of the abstract.

42. The reconfigurable chip of Claim 38 wherein the interconnect elements are adapted to transfer word length data.

43. The reconfigurable chip of Claim 38 wherein further comprising instruction memory storing multiple instructions for the reconfigurable functional units.

44. The reconfigurable chip of Claim 38 wherein the reconfigurable functional units include a shifter unit configurable with a number of different modes.