WO2003003472A3 - Transistor-anordnung, verfahren zum betreiben einer transistor-anordnung als datenspeicher und verfahren zum herstellen einer transistor-anordnung - Google Patents

Transistor-anordnung, verfahren zum betreiben einer transistor-anordnung als datenspeicher und verfahren zum herstellen einer transistor-anordnung Download PDF

Info

Publication number
WO2003003472A3
WO2003003472A3 PCT/DE2002/002263 DE0202263W WO03003472A3 WO 2003003472 A3 WO2003003472 A3 WO 2003003472A3 DE 0202263 W DE0202263 W DE 0202263W WO 03003472 A3 WO03003472 A3 WO 03003472A3
Authority
WO
WIPO (PCT)
Prior art keywords
transistor
arrangement
producing
operating
data storage
Prior art date
Application number
PCT/DE2002/002263
Other languages
English (en)
French (fr)
Other versions
WO2003003472A2 (de
Inventor
Franz Hofmann
Josef Willer
Original Assignee
Infineon Technologies Ag
Franz Hofmann
Josef Willer
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies Ag, Franz Hofmann, Josef Willer filed Critical Infineon Technologies Ag
Priority to KR1020037016897A priority Critical patent/KR100579347B1/ko
Priority to US10/481,278 priority patent/US7154138B2/en
Priority to JP2003509546A priority patent/JP2004533126A/ja
Priority to EP02758056A priority patent/EP1399973A2/de
Publication of WO2003003472A2 publication Critical patent/WO2003003472A2/de
Publication of WO2003003472A3 publication Critical patent/WO2003003472A3/de

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/73—Bipolar junction transistors
    • H01L29/732—Vertical transistors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5671—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge trapping in an insulator
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0466—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS]
    • G11C16/0475—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] comprising two or more independent storage sites which store independent data
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66833—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a charge trapping gate insulator, e.g. MNOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
    • H01L29/7923—Programmable transistors with more than two possible different levels of programmation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

Die Erfindung betrifft eine Transistor-Anordnung (200) mit einem Substrat (201) und einem Vertikal-Transistor mit: einen ersten Elektrodenbereich (204), einen im Wesentlichen darüber angeordneten zweiten Elektrodenbereich (205) und dazwischen einen Kanalbereich (203), sowie einen Gate-Bereich (207) neben dem Kanalbereich (203) und dazwischen eine elektrisch isolierende Schichtenfolge (206), wobei zwei voneinander räumlich getrennte Abschnitte (208, 209) der elektrisch isolierenden Schichtenfolge (206) jeweils zur Speicherung von Ladungsträgern dienen.
PCT/DE2002/002263 2001-06-26 2002-06-20 Transistor-anordnung, verfahren zum betreiben einer transistor-anordnung als datenspeicher und verfahren zum herstellen einer transistor-anordnung WO2003003472A2 (de)

Priority Applications (4)

Application Number Priority Date Filing Date Title
KR1020037016897A KR100579347B1 (ko) 2001-06-26 2002-06-20 트랜지스터 장치, 트랜지스터 장치를 데이터 메모리로서작동시키는 방법 및 트랜지스터 장치의 제조 방법
US10/481,278 US7154138B2 (en) 2001-06-26 2002-06-20 Transistor-arrangement, method for operating a transistor arrangement as a data storage element and method for producing a transistor-arrangement
JP2003509546A JP2004533126A (ja) 2001-06-26 2002-06-20 トランジスタ構成、トランジスタ構成をデータメモリとして動作するための方法、およびトランジスタ構成製造するための方法
EP02758056A EP1399973A2 (de) 2001-06-26 2002-06-20 Transistor-anordnung, verfahren zum betreiben einer transistor-anordnung als datenspeicher und verfahren zum herstellen einer transistor-anordnung

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE10130765A DE10130765A1 (de) 2001-06-26 2001-06-26 Transistor-Anordnung, Verfahren zum Betreiben einer Transistor-Anordnung als Datenspeicher und Verfahren zum Herstellen einer Transistor-Anordnung
DE10130765.9 2001-06-26

Publications (2)

Publication Number Publication Date
WO2003003472A2 WO2003003472A2 (de) 2003-01-09
WO2003003472A3 true WO2003003472A3 (de) 2003-10-30

Family

ID=7689490

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/DE2002/002263 WO2003003472A2 (de) 2001-06-26 2002-06-20 Transistor-anordnung, verfahren zum betreiben einer transistor-anordnung als datenspeicher und verfahren zum herstellen einer transistor-anordnung

Country Status (7)

Country Link
US (1) US7154138B2 (de)
EP (1) EP1399973A2 (de)
JP (1) JP2004533126A (de)
KR (1) KR100579347B1 (de)
DE (1) DE10130765A1 (de)
TW (1) TW556345B (de)
WO (1) WO2003003472A2 (de)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7087954B2 (en) * 2001-08-30 2006-08-08 Micron Technology, Inc. In service programmable logic arrays with low tunnel barrier interpoly insulators
US6963103B2 (en) 2001-08-30 2005-11-08 Micron Technology, Inc. SRAM cells with repressed floating gate memory, low tunnel barrier interpoly insulators
DE102004006676A1 (de) * 2004-02-11 2005-05-04 Infineon Technologies Ag Dynamische Speicherzelle
US7087950B2 (en) * 2004-04-30 2006-08-08 Infineon Technologies Ag Flash memory cell, flash memory device and manufacturing method thereof
US7256098B2 (en) * 2005-04-11 2007-08-14 Infineon Technologies Ag Method of manufacturing a memory device
US7927948B2 (en) 2005-07-20 2011-04-19 Micron Technology, Inc. Devices with nanocrystals and methods of formation
US8110469B2 (en) 2005-08-30 2012-02-07 Micron Technology, Inc. Graded dielectric layers
US20070114619A1 (en) * 2005-11-21 2007-05-24 International Business Machines Corporation Sidewall mosfets with embedded strained source/drain
US20070178684A1 (en) * 2006-01-31 2007-08-02 Torsten Mueller Method for producing conductor arrays on semiconductor devices
KR101363272B1 (ko) * 2011-09-01 2014-02-14 서울대학교산학협력단 수직채널을 갖는 모스펫 및 이를 이용한 논리 게이트 소자

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08162547A (ja) * 1994-11-30 1996-06-21 Toshiba Corp 半導体記憶装置
WO1998006139A1 (de) * 1996-08-01 1998-02-12 Siemens Aktiengesellschaft Nichtflüchtige speicherzelle
US6157061A (en) * 1997-08-29 2000-12-05 Nec Corporation Nonvolatile semiconductor memory device and method of manufacturing the same
JP2001156188A (ja) * 1999-03-08 2001-06-08 Toshiba Corp 半導体記憶装置およびその製造方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05251669A (ja) * 1992-03-06 1993-09-28 Matsushita Electron Corp 半導体記憶装置およびその書き換え方法
US5386132A (en) * 1992-11-02 1995-01-31 Wong; Chun C. D. Multimedia storage system with highly compact memory device
DE19600423C2 (de) * 1996-01-08 2001-07-05 Siemens Ag Elektrisch programmierbare Speicherzellenanordnung und Verfahren zu deren Herstellung
US5969383A (en) * 1997-06-16 1999-10-19 Motorola, Inc. Split-gate memory device and method for accessing the same
US6087222A (en) * 1998-03-05 2000-07-11 Taiwan Semiconductor Manufacturing Company Method of manufacture of vertical split gate flash memory device
US6204529B1 (en) * 1999-08-27 2001-03-20 Hsing Lan Lung 8 bit per cell non-volatile semiconductor memory structure utilizing trench technology and dielectric floating gate
DE10036911C2 (de) * 2000-07-28 2002-06-06 Infineon Technologies Ag Verfahren zur Herstellung einer Multi-Bit-Speicherzelle

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08162547A (ja) * 1994-11-30 1996-06-21 Toshiba Corp 半導体記憶装置
WO1998006139A1 (de) * 1996-08-01 1998-02-12 Siemens Aktiengesellschaft Nichtflüchtige speicherzelle
US6157061A (en) * 1997-08-29 2000-12-05 Nec Corporation Nonvolatile semiconductor memory device and method of manufacturing the same
JP2001156188A (ja) * 1999-03-08 2001-06-08 Toshiba Corp 半導体記憶装置およびその製造方法
US6335554B1 (en) * 1999-03-08 2002-01-01 Kabushiki Kaisha Toshiba Semiconductor Memory

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 1996, no. 10 31 October 1996 (1996-10-31) *
PATENT ABSTRACTS OF JAPAN vol. 2000, no. 23 10 February 2001 (2001-02-10) *

Also Published As

Publication number Publication date
US20040207038A1 (en) 2004-10-21
EP1399973A2 (de) 2004-03-24
KR100579347B1 (ko) 2006-05-12
US7154138B2 (en) 2006-12-26
JP2004533126A (ja) 2004-10-28
TW556345B (en) 2003-10-01
DE10130765A1 (de) 2003-01-09
KR20040030705A (ko) 2004-04-09
WO2003003472A2 (de) 2003-01-09

Similar Documents

Publication Publication Date Title
TW200505033A (en) Capacitor and method of fabricating the same
EP1265286A3 (de) Integrierte Schaltkreisstruktur
WO2004061417A3 (en) Device structure for closely spaced electrodes
WO2003079463A3 (en) Programmable structure, an array including the structure, and methods of forming the same
AU2003212907A1 (en) Multiple data state memory cell
AU2002367718A8 (en) Molehole embedded 3-d crossbar architecture used in electrochemical molecular memory device
WO2008079077A3 (en) Nanoelectronic structure and method of producing such
ATE355530T1 (de) Mikromechanisches bauelement
WO2007051765A3 (en) Electrically programmable fuse
WO2004023519A3 (de) Hochdichter nrom-finfet
WO2003098700A3 (en) Resurf super-junction devices having trenches
WO2006059313A3 (en) Non-volatile memory
WO2003003472A3 (de) Transistor-anordnung, verfahren zum betreiben einer transistor-anordnung als datenspeicher und verfahren zum herstellen einer transistor-anordnung
AU2003227435A1 (en) Hydrogen-containing electrically conductive organic compound
EP1178595A3 (de) Induktivitätsarme Schaltungsanordnung
WO2005034207A3 (en) Varying carrier mobility on finfet active surfaces to achieve overall design goals
WO2008146461A1 (ja) 不揮発性記憶素子およびその製造方法、並びにその不揮発性記憶素子を用いた不揮発性半導体装置
WO2003019649A3 (de) Leiterbahnanordnung und verfahren zum herstellen einer leiterbahnanordnung
WO2005034186A3 (en) Method for forming a semiconductor device having isolation regions
WO2003058327A8 (fr) Modulateur optique du type a surface et son procede de fabrication
WO2006114746A3 (en) Bipolar transistor and method of fabricating the same
TW200501381A (en) Parasitic capacitance-preventing dummy solder bump structure and method of making the same
WO2005057664A3 (en) Power mosfet and methods of making same
TWI229446B (en) Memory module with improved electrical properties
WO2002082550A3 (de) Speicherzellenarray und verfahren zur herstellung desselben

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A2

Designated state(s): BR CA CN IL IN JP KR MX RU UA US

AL Designated countries for regional patents

Kind code of ref document: A2

Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE TR

121 Ep: the epo has been informed by wipo that ep was designated in this application
DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
WWE Wipo information: entry into national phase

Ref document number: 2002758056

Country of ref document: EP

WWE Wipo information: entry into national phase

Ref document number: 1020037016897

Country of ref document: KR

WWE Wipo information: entry into national phase

Ref document number: 2003509546

Country of ref document: JP

WWP Wipo information: published in national office

Ref document number: 2002758056

Country of ref document: EP

WWE Wipo information: entry into national phase

Ref document number: 10481278

Country of ref document: US